[linux-2.6-block.git] / include / linux / mlx4 / device.h

/*
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_DEVICE_H
#define MLX4_DEVICE_H

#include <linux/pci.h>
#include <linux/completion.h>
#include <linux/radix-tree.h>

#include <asm/atomic.h>

#define MAX_MSIX_P_PORT		17
#define MAX_MSIX		64
#define MSIX_LEGACY_SZ		4
#define MIN_MSIX_P_PORT		5

enum {
	MLX4_FLAG_MSI_X		= 1 << 0,
	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
};

enum {
	MLX4_MAX_PORTS		= 2
};

enum {
	MLX4_BOARD_ID_LEN = 64
};

enum {
	MLX4_DEV_CAP_FLAG_RC		= 1 <<  0,
	MLX4_DEV_CAP_FLAG_UC		= 1 <<  1,
	MLX4_DEV_CAP_FLAG_UD		= 1 <<  2,
	MLX4_DEV_CAP_FLAG_SRQ		= 1 <<  6,
	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1 <<  7,
	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1 <<  8,
	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1 <<  9,
	MLX4_DEV_CAP_FLAG_DPDP		= 1 << 12,
	MLX4_DEV_CAP_FLAG_BLH		= 1 << 15,
	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1 << 16,
	MLX4_DEV_CAP_FLAG_APM		= 1 << 17,
	MLX4_DEV_CAP_FLAG_ATOMIC	= 1 << 18,
	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1 << 19,
	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1 << 20,
	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1 << 21,
	MLX4_DEV_CAP_FLAG_IBOE		= 1 << 30
};

enum {
	MLX4_BMME_FLAG_LOCAL_INV	= 1 <<  6,
	MLX4_BMME_FLAG_REMOTE_INV	= 1 <<  7,
	MLX4_BMME_FLAG_TYPE_2_WIN	= 1 <<  9,
	MLX4_BMME_FLAG_RESERVED_LKEY	= 1 << 10,
	MLX4_BMME_FLAG_FAST_REG_WR	= 1 << 11,
};

enum mlx4_event {
	MLX4_EVENT_TYPE_COMP		   = 0x00,
	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
	MLX4_EVENT_TYPE_CMD		   = 0x0a
};

enum {
	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
};

enum {
	MLX4_PERM_LOCAL_READ	= 1 << 10,
	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
	MLX4_PERM_REMOTE_READ	= 1 << 12,
	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
	MLX4_PERM_ATOMIC	= 1 << 14
};

enum {
	MLX4_OPCODE_NOP			= 0x00,
	MLX4_OPCODE_SEND_INVAL		= 0x01,
	MLX4_OPCODE_RDMA_WRITE		= 0x08,
	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
	MLX4_OPCODE_SEND		= 0x0a,
	MLX4_OPCODE_SEND_IMM		= 0x0b,
	MLX4_OPCODE_LSO			= 0x0e,
	MLX4_OPCODE_RDMA_READ		= 0x10,
	MLX4_OPCODE_ATOMIC_CS		= 0x11,
	MLX4_OPCODE_ATOMIC_FA		= 0x12,
	MLX4_OPCODE_MASKED_ATOMIC_CS	= 0x14,
	MLX4_OPCODE_MASKED_ATOMIC_FA	= 0x15,
	MLX4_OPCODE_BIND_MW		= 0x18,
	MLX4_OPCODE_FMR			= 0x19,
	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
	MLX4_OPCODE_CONFIG_CMD		= 0x1f,

	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
	MLX4_RECV_OPCODE_SEND		= 0x01,
	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,

	MLX4_CQE_OPCODE_ERROR		= 0x1e,
	MLX4_CQE_OPCODE_RESIZE		= 0x16,
};

enum {
	MLX4_STAT_RATE_OFFSET	= 5
};

enum mlx4_protocol {
	MLX4_PROTOCOL_IB,
	MLX4_PROTOCOL_EN,
};

enum {
	MLX4_MTT_FLAG_PRESENT		= 1
};

enum mlx4_qp_region {
	MLX4_QP_REGION_FW = 0,
	MLX4_QP_REGION_ETH_ADDR,
	MLX4_QP_REGION_FC_ADDR,
	MLX4_QP_REGION_FC_EXCH,
	MLX4_NUM_QP_REGION
};

enum mlx4_port_type {
	MLX4_PORT_TYPE_IB	= 1,
	MLX4_PORT_TYPE_ETH	= 2,
	MLX4_PORT_TYPE_AUTO	= 3
};

enum mlx4_special_vlan_idx {
	MLX4_NO_VLAN_IDX        = 0,
	MLX4_VLAN_MISS_IDX,
	MLX4_VLAN_REGULAR
};

enum {
	MLX4_NUM_FEXCH          = 64 * 1024,
};

enum {
	MLX4_MAX_FAST_REG_PAGES = 511,
};

static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
{
	return (major << 32) | (minor << 16) | subminor;
}

struct mlx4_caps {
	u64			fw_ver;
	int			num_ports;
	int			vl_cap[MLX4_MAX_PORTS + 1];
	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
	__be32			ib_port_def_cap[MLX4_MAX_PORTS + 1];
	u64			def_mac[MLX4_MAX_PORTS + 1];
	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
	int			gid_table_len[MLX4_MAX_PORTS + 1];
	int			pkey_table_len[MLX4_MAX_PORTS + 1];
	int			trans_type[MLX4_MAX_PORTS + 1];
	int			vendor_oui[MLX4_MAX_PORTS + 1];
	int			wavelength[MLX4_MAX_PORTS + 1];
	u64			trans_code[MLX4_MAX_PORTS + 1];
	int			local_ca_ack_delay;
	int			num_uars;
	int			bf_reg_size;
	int			bf_regs_per_page;
	int			max_sq_sg;
	int			max_rq_sg;
	int			num_qps;
	int			max_wqes;
	int			max_sq_desc_sz;
	int			max_rq_desc_sz;
	int			max_qp_init_rdma;
	int			max_qp_dest_rdma;
	int			sqp_start;
	int			num_srqs;
	int			max_srq_wqes;
	int			max_srq_sge;
	int			reserved_srqs;
	int			num_cqs;
	int			max_cqes;
	int			reserved_cqs;
	int			num_eqs;
	int			reserved_eqs;
	int			num_comp_vectors;
	int			comp_pool;
	int			num_mpts;
	int			num_mtt_segs;
	int			mtts_per_seg;
	int			fmr_reserved_mtts;
	int			reserved_mtts;
	int			reserved_mrws;
	int			reserved_uars;
	int			num_mgms;
	int			num_amgms;
	int			reserved_mcgs;
	int			num_qp_per_mgm;
	int			num_pds;
	int			reserved_pds;
	int			mtt_entry_sz;
	u32			max_msg_sz;
	u32			page_size_cap;
	u32			flags;
	u32			bmme_flags;
	u32			reserved_lkey;
	u16			stat_rate_support;
	int			udp_rss;
	int			loopback_support;
	u8			port_width_cap[MLX4_MAX_PORTS + 1];
	int			max_gso_sz;
	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
	int			reserved_qps;
	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
	int                     log_num_macs;
	int                     log_num_vlans;
	int                     log_num_prios;
	enum mlx4_port_type	port_type[MLX4_MAX_PORTS + 1];
	u8			supported_type[MLX4_MAX_PORTS + 1];
	u32			port_mask;
	enum mlx4_port_type	possible_type[MLX4_MAX_PORTS + 1];
};

struct mlx4_buf_list {
	void		       *buf;
	dma_addr_t		map;
};

struct mlx4_buf {
	struct mlx4_buf_list	direct;
	struct mlx4_buf_list   *page_list;
	int			nbufs;
	int			npages;
	int			page_shift;
};

struct mlx4_mtt {
	u32			first_seg;
	int			order;
	int			page_shift;
};

enum {
	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
};

struct mlx4_db_pgdir {
	struct list_head	list;
	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	unsigned long	       *bits[2];
	__be32		       *db_page;
	dma_addr_t		db_dma;
};

struct mlx4_ib_user_db_page;

struct mlx4_db {
	__be32			*db;
	union {
		struct mlx4_db_pgdir		*pgdir;
		struct mlx4_ib_user_db_page	*user_page;
	}			u;
	dma_addr_t		dma;
	int			index;
	int			order;
};

struct mlx4_hwq_resources {
	struct mlx4_db		db;
	struct mlx4_mtt		mtt;
	struct mlx4_buf		buf;
};

struct mlx4_mr {
	struct mlx4_mtt		mtt;
	u64			iova;
	u64			size;
	u32			key;
	u32			pd;
	u32			access;
	int			enabled;
};

struct mlx4_fmr {
	struct mlx4_mr		mr;
	struct mlx4_mpt_entry  *mpt;
	__be64		       *mtts;
	dma_addr_t		dma_handle;
	int			max_pages;
	int			max_maps;
	int			maps;
	u8			page_shift;
};

struct mlx4_uar {
	unsigned long		pfn;
	int			index;
};

struct mlx4_cq {
	void (*comp)		(struct mlx4_cq *);
	void (*event)		(struct mlx4_cq *, enum mlx4_event);

	struct mlx4_uar	       *uar;

	u32			cons_index;

	__be32		       *set_ci_db;
	__be32		       *arm_db;
	int			arm_sn;

	int			cqn;
	unsigned		vector;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_qp {
	void (*event)		(struct mlx4_qp *, enum mlx4_event);

	int			qpn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_srq {
	void (*event)		(struct mlx4_srq *, enum mlx4_event);

	int			srqn;
	int			max;
	int			max_gs;
	int			wqe_shift;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_av {
	__be32			port_pd;
	u8			reserved1;
	u8			g_slid;
	__be16			dlid;
	u8			reserved2;
	u8			gid_index;
	u8			stat_rate;
	u8			hop_limit;
	__be32			sl_tclass_flowlabel;
	u8			dgid[16];
};

struct mlx4_eth_av {
	__be32		port_pd;
	u8		reserved1;
	u8		smac_idx;
	u16		reserved2;
	u8		reserved3;
	u8		gid_index;
	u8		stat_rate;
	u8		hop_limit;
	__be32		sl_tclass_flowlabel;
	u8		dgid[16];
	u32		reserved4[2];
	__be16		vlan;
	u8		mac[6];
};

union mlx4_ext_av {
	struct mlx4_av		ib;
	struct mlx4_eth_av	eth;
};

struct mlx4_dev {
	struct pci_dev	       *pdev;
	unsigned long		flags;
	struct mlx4_caps	caps;
	struct radix_tree_root	qp_table_tree;
	u32			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

struct mlx4_init_port_param {
	int			set_guid0;
	int			set_node_guid;
	int			set_si_guid;
	u16			mtu;
	int			port_width_cap;
	u16			vl_cap;
	u16			max_gid;
	u16			max_pkey;
	u64			guid0;
	u64			node_guid;
	u64			si_guid;
};

#define mlx4_foreach_port(port, dev, type)				\
	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
		if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
		     ~(dev)->caps.port_mask) & 1 << ((port) - 1))

#define mlx4_foreach_ib_transport_port(port, dev)			\
	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
		if (((dev)->caps.port_mask & 1 << ((port) - 1)) ||	\
		    ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))


int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
		   struct mlx4_buf *buf);
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
{
	if (BITS_PER_LONG == 64 || buf->nbufs == 1)
		return buf->direct.buf + offset;
	else
		return buf->page_list[offset >> PAGE_SHIFT].buf +
			(offset & (PAGE_SIZE - 1));
}

int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);

int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt);
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr);
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list);
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf);

int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);

int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
		       int size, int max_direct);
void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
		       int size);

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
		  unsigned vector, int collapsed);
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);

int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);

int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);

int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
		   u64 db_rec, struct mlx4_srq *srq);
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);

int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);

int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  int block_mcast_loopback, enum mlx4_protocol protocol);
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  enum mlx4_protocol protocol);

int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);

int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);

int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
		      int npages, u64 iova, u32 *lkey, u32 *rkey);
int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
		   int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
		    u32 *lkey, u32 *rkey);
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
int mlx4_SYNC_TPT(struct mlx4_dev *dev);
int mlx4_test_interrupts(struct mlx4_dev *dev);
int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
void mlx4_release_eq(struct mlx4_dev *dev, int vec);

#endif /* MLX4_DEVICE_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_DEVICE_H
	34	#define MLX4_DEVICE_H
	35
	36	#include <linux/pci.h>
	37	#include <linux/completion.h>
	38	#include <linux/radix-tree.h>
	39
	40	#include <asm/atomic.h>
	41
0b7ca5a9 YP	42	#define MAX_MSIX_P_PORT 17
	43	#define MAX_MSIX 64
	44	#define MSIX_LEGACY_SZ 4
	45	#define MIN_MSIX_P_PORT 5
	46
225c7b1f RD	47	enum {
225c7b1f RD	48	MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8	49	MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
225c7b1f RD	50	};
	51
	52	enum {
	53	MLX4_MAX_PORTS = 2
	54	};
	55
cd9281d8 JM	56	enum {
	57	MLX4_BOARD_ID_LEN = 64
	58	};
	59
225c7b1f RD	60	enum {
	61	MLX4_DEV_CAP_FLAG_RC = 1 << 0,
	62	MLX4_DEV_CAP_FLAG_UC = 1 << 1,
	63	MLX4_DEV_CAP_FLAG_UD = 1 << 2,
	64	MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
	65	MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
	66	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
	67	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
7ff93f8b	68	MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
417608c2	69	MLX4_DEV_CAP_FLAG_BLH = 1 << 15,
225c7b1f RD	70	MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
	71	MLX4_DEV_CAP_FLAG_APM = 1 << 17,
	72	MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
	73	MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
	74	MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
96dfa684 EC	75	MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21,
96dfa684 EC	76	MLX4_DEV_CAP_FLAG_IBOE = 1 << 30
225c7b1f RD	77	};
225c7b1f RD	78
95d04f07 RD	79	enum {
	80	MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
	81	MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
	82	MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
	83	MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
	84	MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
	85	};
	86
225c7b1f RD	87	enum mlx4_event {
	88	MLX4_EVENT_TYPE_COMP = 0x00,
	89	MLX4_EVENT_TYPE_PATH_MIG = 0x01,
	90	MLX4_EVENT_TYPE_COMM_EST = 0x02,
	91	MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
	92	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
	93	MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
	94	MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
	95	MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
	96	MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
	97	MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
	98	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	99	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
	100	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
	101	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
	102	MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
	103	MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
	104	MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
	105	MLX4_EVENT_TYPE_CMD = 0x0a
	106	};
	107
	108	enum {
	109	MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
	110	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
	111	};
	112
	113	enum {
	114	MLX4_PERM_LOCAL_READ = 1 << 10,
	115	MLX4_PERM_LOCAL_WRITE = 1 << 11,
	116	MLX4_PERM_REMOTE_READ = 1 << 12,
	117	MLX4_PERM_REMOTE_WRITE = 1 << 13,
	118	MLX4_PERM_ATOMIC = 1 << 14
	119	};
	120
	121	enum {
	122	MLX4_OPCODE_NOP = 0x00,
	123	MLX4_OPCODE_SEND_INVAL = 0x01,
	124	MLX4_OPCODE_RDMA_WRITE = 0x08,
	125	MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
	126	MLX4_OPCODE_SEND = 0x0a,
	127	MLX4_OPCODE_SEND_IMM = 0x0b,
	128	MLX4_OPCODE_LSO = 0x0e,
	129	MLX4_OPCODE_RDMA_READ = 0x10,
	130	MLX4_OPCODE_ATOMIC_CS = 0x11,
	131	MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719 VS	132	MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
6fa8f719 VS	133	MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f RD	134	MLX4_OPCODE_BIND_MW = 0x18,
	135	MLX4_OPCODE_FMR = 0x19,
	136	MLX4_OPCODE_LOCAL_INVAL = 0x1b,
	137	MLX4_OPCODE_CONFIG_CMD = 0x1f,
	138
	139	MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
	140	MLX4_RECV_OPCODE_SEND = 0x01,
	141	MLX4_RECV_OPCODE_SEND_IMM = 0x02,
	142	MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
	143
	144	MLX4_CQE_OPCODE_ERROR = 0x1e,
	145	MLX4_CQE_OPCODE_RESIZE = 0x16,
	146	};
	147
	148	enum {
	149	MLX4_STAT_RATE_OFFSET = 5
	150	};
	151
da995a8a AS	152	enum mlx4_protocol {
	153	MLX4_PROTOCOL_IB,
	154	MLX4_PROTOCOL_EN,
	155	};
	156
29bdc883 VS	157	enum {
	158	MLX4_MTT_FLAG_PRESENT = 1
	159	};
	160
93fc9e1b YP	161	enum mlx4_qp_region {
	162	MLX4_QP_REGION_FW = 0,
	163	MLX4_QP_REGION_ETH_ADDR,
	164	MLX4_QP_REGION_FC_ADDR,
	165	MLX4_QP_REGION_FC_EXCH,
	166	MLX4_NUM_QP_REGION
	167	};
	168
7ff93f8b	169	enum mlx4_port_type {
27bf91d6 YP	170	MLX4_PORT_TYPE_IB = 1,
	171	MLX4_PORT_TYPE_ETH = 2,
	172	MLX4_PORT_TYPE_AUTO = 3
7ff93f8b YP	173	};
7ff93f8b YP	174
2a2336f8 YP	175	enum mlx4_special_vlan_idx {
	176	MLX4_NO_VLAN_IDX = 0,
	177	MLX4_VLAN_MISS_IDX,
	178	MLX4_VLAN_REGULAR
	179	};
	180
93fc9e1b YP	181	enum {
	182	MLX4_NUM_FEXCH = 64 * 1024,
	183	};
	184
5a0fd094 EC	185	enum {
	186	MLX4_MAX_FAST_REG_PAGES = 511,
	187	};
	188
ea54b10c JM	189	static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
	190	{
	191	return (major << 32) \| (minor << 16) \| subminor;
	192	}
	193
225c7b1f RD	194	struct mlx4_caps {
	195	u64 fw_ver;
	196	int num_ports;
5ae2a7a8	197	int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49	198	int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622	199	__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49 YP	200	u64 def_mac[MLX4_MAX_PORTS + 1];
b79acb49 YP	201	int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	202	int gid_table_len[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	203	int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d YP	204	int trans_type[MLX4_MAX_PORTS + 1];
	205	int vendor_oui[MLX4_MAX_PORTS + 1];
	206	int wavelength[MLX4_MAX_PORTS + 1];
	207	u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f RD	208	int local_ca_ack_delay;
	209	int num_uars;
	210	int bf_reg_size;
	211	int bf_regs_per_page;
	212	int max_sq_sg;
	213	int max_rq_sg;
	214	int num_qps;
	215	int max_wqes;
	216	int max_sq_desc_sz;
	217	int max_rq_desc_sz;
	218	int max_qp_init_rdma;
	219	int max_qp_dest_rdma;
225c7b1f RD	220	int sqp_start;
	221	int num_srqs;
	222	int max_srq_wqes;
	223	int max_srq_sge;
	224	int reserved_srqs;
	225	int num_cqs;
	226	int max_cqes;
	227	int reserved_cqs;
	228	int num_eqs;
	229	int reserved_eqs;
b8dd786f	230	int num_comp_vectors;
0b7ca5a9	231	int comp_pool;
225c7b1f RD	232	int num_mpts;
225c7b1f RD	233	int num_mtt_segs;
ab6bf42e	234	int mtts_per_seg;
225c7b1f RD	235	int fmr_reserved_mtts;
	236	int reserved_mtts;
	237	int reserved_mrws;
	238	int reserved_uars;
	239	int num_mgms;
	240	int num_amgms;
	241	int reserved_mcgs;
	242	int num_qp_per_mgm;
	243	int num_pds;
	244	int reserved_pds;
	245	int mtt_entry_sz;
149983af	246	u32 max_msg_sz;
225c7b1f RD	247	u32 page_size_cap;
225c7b1f RD	248	u32 flags;
95d04f07 RD	249	u32 bmme_flags;
95d04f07 RD	250	u32 reserved_lkey;
225c7b1f	251	u16 stat_rate_support;
0533943c	252	int udp_rss;
e7c1c2c4	253	int loopback_support;
5ae2a7a8	254	u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e	255	int max_gso_sz;
93fc9e1b YP	256	int reserved_qps_cnt[MLX4_NUM_QP_REGION];
	257	int reserved_qps;
	258	int reserved_qps_base[MLX4_NUM_QP_REGION];
	259	int log_num_macs;
	260	int log_num_vlans;
	261	int log_num_prios;
7ff93f8b YP	262	enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
	263	u8 supported_type[MLX4_MAX_PORTS + 1];
	264	u32 port_mask;
27bf91d6	265	enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
225c7b1f RD	266	};
	267
	268	struct mlx4_buf_list {
	269	void *buf;
	270	dma_addr_t map;
	271	};
	272
	273	struct mlx4_buf {
b57aacfa RD	274	struct mlx4_buf_list direct;
b57aacfa RD	275	struct mlx4_buf_list *page_list;
225c7b1f RD	276	int nbufs;
	277	int npages;
	278	int page_shift;
	279	};
	280
	281	struct mlx4_mtt {
	282	u32 first_seg;
	283	int order;
	284	int page_shift;
	285	};
	286
6296883c YP	287	enum {
	288	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
	289	};
	290
	291	struct mlx4_db_pgdir {
	292	struct list_head list;
	293	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	294	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	295	unsigned long *bits[2];
	296	__be32 *db_page;
	297	dma_addr_t db_dma;
	298	};
	299
	300	struct mlx4_ib_user_db_page;
	301
	302	struct mlx4_db {
	303	__be32 *db;
	304	union {
	305	struct mlx4_db_pgdir *pgdir;
	306	struct mlx4_ib_user_db_page *user_page;
	307	} u;
	308	dma_addr_t dma;
	309	int index;
	310	int order;
	311	};
	312
38ae6a53 YP	313	struct mlx4_hwq_resources {
	314	struct mlx4_db db;
	315	struct mlx4_mtt mtt;
	316	struct mlx4_buf buf;
	317	};
	318
225c7b1f RD	319	struct mlx4_mr {
	320	struct mlx4_mtt mtt;
	321	u64 iova;
	322	u64 size;
	323	u32 key;
	324	u32 pd;
	325	u32 access;
	326	int enabled;
	327	};
	328
8ad11fb6 JM	329	struct mlx4_fmr {
	330	struct mlx4_mr mr;
	331	struct mlx4_mpt_entry *mpt;
	332	__be64 *mtts;
	333	dma_addr_t dma_handle;
	334	int max_pages;
	335	int max_maps;
	336	int maps;
	337	u8 page_shift;
	338	};
	339
225c7b1f RD	340	struct mlx4_uar {
	341	unsigned long pfn;
	342	int index;
	343	};
	344
	345	struct mlx4_cq {
	346	void (comp) (struct mlx4_cq );
	347	void (event) (struct mlx4_cq , enum mlx4_event);
	348
	349	struct mlx4_uar *uar;
	350
	351	u32 cons_index;
	352
	353	__be32 *set_ci_db;
	354	__be32 *arm_db;
	355	int arm_sn;
	356
	357	int cqn;
b8dd786f	358	unsigned vector;
225c7b1f RD	359
	360	atomic_t refcount;
	361	struct completion free;
	362	};
	363
	364	struct mlx4_qp {
	365	void (event) (struct mlx4_qp , enum mlx4_event);
	366
	367	int qpn;
	368
	369	atomic_t refcount;
	370	struct completion free;
	371	};
	372
	373	struct mlx4_srq {
	374	void (event) (struct mlx4_srq , enum mlx4_event);
	375
	376	int srqn;
	377	int max;
	378	int max_gs;
	379	int wqe_shift;
	380
	381	atomic_t refcount;
	382	struct completion free;
	383	};
	384
	385	struct mlx4_av {
	386	__be32 port_pd;
	387	u8 reserved1;
	388	u8 g_slid;
	389	__be16 dlid;
	390	u8 reserved2;
	391	u8 gid_index;
	392	u8 stat_rate;
	393	u8 hop_limit;
	394	__be32 sl_tclass_flowlabel;
	395	u8 dgid[16];
	396	};
	397
fa417f7b EC	398	struct mlx4_eth_av {
	399	__be32 port_pd;
	400	u8 reserved1;
	401	u8 smac_idx;
	402	u16 reserved2;
	403	u8 reserved3;
	404	u8 gid_index;
	405	u8 stat_rate;
	406	u8 hop_limit;
	407	__be32 sl_tclass_flowlabel;
	408	u8 dgid[16];
	409	u32 reserved4[2];
	410	__be16 vlan;
	411	u8 mac[6];
	412	};
	413
	414	union mlx4_ext_av {
	415	struct mlx4_av ib;
	416	struct mlx4_eth_av eth;
	417	};
	418
225c7b1f RD	419	struct mlx4_dev {
	420	struct pci_dev *pdev;
	421	unsigned long flags;
	422	struct mlx4_caps caps;
	423	struct radix_tree_root qp_table_tree;
cd9281d8 JM	424	u32 rev_id;
cd9281d8 JM	425	char board_id[MLX4_BOARD_ID_LEN];
225c7b1f RD	426	};
	427
	428	struct mlx4_init_port_param {
	429	int set_guid0;
	430	int set_node_guid;
	431	int set_si_guid;
	432	u16 mtu;
	433	int port_width_cap;
	434	u16 vl_cap;
	435	u16 max_gid;
	436	u16 max_pkey;
	437	u64 guid0;
	438	u64 node_guid;
	439	u64 si_guid;
	440	};
	441
7ff93f8b YP	442	#define mlx4_foreach_port(port, dev, type) \
	443	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
	444	if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
	445	~(dev)->caps.port_mask) & 1 << ((port) - 1))
	446
fa417f7b EC	447	#define mlx4_foreach_ib_transport_port(port, dev) \
	448	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
	449	if (((dev)->caps.port_mask & 1 << ((port) - 1)) \|\| \
	450	((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
	451
	452
225c7b1f RD	453	int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
	454	struct mlx4_buf *buf);
	455	void mlx4_buf_free(struct mlx4_dev dev, int size, struct mlx4_buf buf);
1c69fc2a RD	456	static inline void mlx4_buf_offset(struct mlx4_buf buf, int offset)
1c69fc2a RD	457	{
313abe55	458	if (BITS_PER_LONG == 64 \|\| buf->nbufs == 1)
b57aacfa	459	return buf->direct.buf + offset;
1c69fc2a	460	else
b57aacfa	461	return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a RD	462	(offset & (PAGE_SIZE - 1));
1c69fc2a RD	463	}
225c7b1f RD	464
	465	int mlx4_pd_alloc(struct mlx4_dev dev, u32 pdn);
	466	void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
	467
	468	int mlx4_uar_alloc(struct mlx4_dev dev, struct mlx4_uar uar);
	469	void mlx4_uar_free(struct mlx4_dev dev, struct mlx4_uar uar);
	470
	471	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
	472	struct mlx4_mtt *mtt);
	473	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt);
	474	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt);
	475
	476	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
	477	int npages, int page_shift, struct mlx4_mr *mr);
	478	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr);
	479	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr);
	480	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	481	int start_index, int npages, u64 *page_list);
	482	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	483	struct mlx4_buf *buf);
	484
6296883c YP	485	int mlx4_db_alloc(struct mlx4_dev dev, struct mlx4_db db, int order);
	486	void mlx4_db_free(struct mlx4_dev dev, struct mlx4_db db);
	487
38ae6a53 YP	488	int mlx4_alloc_hwq_res(struct mlx4_dev dev, struct mlx4_hwq_resources wqres,
	489	int size, int max_direct);
	490	void mlx4_free_hwq_res(struct mlx4_dev mdev, struct mlx4_hwq_resources wqres,
	491	int size);
	492
225c7b1f	493	int mlx4_cq_alloc(struct mlx4_dev dev, int nent, struct mlx4_mtt mtt,
e463c7b1	494	struct mlx4_uar uar, u64 db_rec, struct mlx4_cq cq,
b8dd786f	495	unsigned vector, int collapsed);
225c7b1f RD	496	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq);
225c7b1f RD	497
a3cdcbfa YP	498	int mlx4_qp_reserve_range(struct mlx4_dev dev, int cnt, int align, int base);
	499	void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
	500
	501	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp);
225c7b1f RD	502	void mlx4_qp_free(struct mlx4_dev dev, struct mlx4_qp qp);
	503
	504	int mlx4_srq_alloc(struct mlx4_dev dev, u32 pdn, struct mlx4_mtt mtt,
	505	u64 db_rec, struct mlx4_srq *srq);
	506	void mlx4_srq_free(struct mlx4_dev dev, struct mlx4_srq srq);
	507	int mlx4_srq_arm(struct mlx4_dev dev, struct mlx4_srq srq, int limit_watermark);
65541cb7	508	int mlx4_srq_query(struct mlx4_dev dev, struct mlx4_srq srq, int *limit_watermark);
225c7b1f	509
5ae2a7a8	510	int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	511	int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	512
521e575b	513	int mlx4_multicast_attach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
da995a8a AS	514	int block_mcast_loopback, enum mlx4_protocol protocol);
	515	int mlx4_multicast_detach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
	516	enum mlx4_protocol protocol);
225c7b1f	517
2a2336f8 YP	518	int mlx4_register_mac(struct mlx4_dev dev, u8 port, u64 mac, int index);
	519	void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
	520
4c3eb3ca	521	int mlx4_find_cached_vlan(struct mlx4_dev dev, u8 port, u16 vid, int idx);
2a2336f8 YP	522	int mlx4_register_vlan(struct mlx4_dev dev, u8 port, u16 vlan, int index);
	523	void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
	524
8ad11fb6 JM	525	int mlx4_map_phys_fmr(struct mlx4_dev dev, struct mlx4_fmr fmr, u64 *page_list,
	526	int npages, u64 iova, u32 lkey, u32 rkey);
	527	int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
	528	int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
	529	int mlx4_fmr_enable(struct mlx4_dev dev, struct mlx4_fmr fmr);
	530	void mlx4_fmr_unmap(struct mlx4_dev dev, struct mlx4_fmr fmr,
	531	u32 lkey, u32 rkey);
	532	int mlx4_fmr_free(struct mlx4_dev dev, struct mlx4_fmr fmr);
	533	int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4	534	int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9 YP	535	int mlx4_assign_eq(struct mlx4_dev dev, char name , int* vector);
0b7ca5a9 YP	536	void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6	537
225c7b1f	538	#endif /* MLX4_DEVICE_H */