[linux-2.6-block.git] / include / linux / mlx4 / cmd.h

/*
 * Copyright (c) 2006 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_CMD_H
#define MLX4_CMD_H

#include <linux/dma-mapping.h>
#include <linux/if_link.h>

enum {
	/* initialization and general commands */
	MLX4_CMD_SYS_EN		 = 0x1,
	MLX4_CMD_SYS_DIS	 = 0x2,
	MLX4_CMD_MAP_FA		 = 0xfff,
	MLX4_CMD_UNMAP_FA	 = 0xffe,
	MLX4_CMD_RUN_FW		 = 0xff6,
	MLX4_CMD_MOD_STAT_CFG	 = 0x34,
	MLX4_CMD_QUERY_DEV_CAP	 = 0x3,
	MLX4_CMD_QUERY_FW	 = 0x4,
	MLX4_CMD_ENABLE_LAM	 = 0xff8,
	MLX4_CMD_DISABLE_LAM	 = 0xff7,
	MLX4_CMD_QUERY_DDR	 = 0x5,
	MLX4_CMD_QUERY_ADAPTER	 = 0x6,
	MLX4_CMD_INIT_HCA	 = 0x7,
	MLX4_CMD_CLOSE_HCA	 = 0x8,
	MLX4_CMD_INIT_PORT	 = 0x9,
	MLX4_CMD_CLOSE_PORT	 = 0xa,
	MLX4_CMD_QUERY_HCA	 = 0xb,
	MLX4_CMD_QUERY_PORT	 = 0x43,
	MLX4_CMD_SENSE_PORT	 = 0x4d,
	MLX4_CMD_HW_HEALTH_CHECK = 0x50,
	MLX4_CMD_SET_PORT	 = 0xc,
	MLX4_CMD_SET_NODE	 = 0x5a,
	MLX4_CMD_QUERY_FUNC	 = 0x56,
	MLX4_CMD_ACCESS_DDR	 = 0x2e,
	MLX4_CMD_MAP_ICM	 = 0xffa,
	MLX4_CMD_UNMAP_ICM	 = 0xff9,
	MLX4_CMD_MAP_ICM_AUX	 = 0xffc,
	MLX4_CMD_UNMAP_ICM_AUX	 = 0xffb,
	MLX4_CMD_SET_ICM_SIZE	 = 0xffd,
	MLX4_CMD_ACCESS_REG	 = 0x3b,

	/*master notify fw on finish for slave's flr*/
	MLX4_CMD_INFORM_FLR_DONE = 0x5b,
	MLX4_CMD_GET_OP_REQ      = 0x59,

	/* TPT commands */
	MLX4_CMD_SW2HW_MPT	 = 0xd,
	MLX4_CMD_QUERY_MPT	 = 0xe,
	MLX4_CMD_HW2SW_MPT	 = 0xf,
	MLX4_CMD_READ_MTT	 = 0x10,
	MLX4_CMD_WRITE_MTT	 = 0x11,
	MLX4_CMD_SYNC_TPT	 = 0x2f,

	/* EQ commands */
	MLX4_CMD_MAP_EQ		 = 0x12,
	MLX4_CMD_SW2HW_EQ	 = 0x13,
	MLX4_CMD_HW2SW_EQ	 = 0x14,
	MLX4_CMD_QUERY_EQ	 = 0x15,

	/* CQ commands */
	MLX4_CMD_SW2HW_CQ	 = 0x16,
	MLX4_CMD_HW2SW_CQ	 = 0x17,
	MLX4_CMD_QUERY_CQ	 = 0x18,
	MLX4_CMD_MODIFY_CQ	 = 0x2c,

	/* SRQ commands */
	MLX4_CMD_SW2HW_SRQ	 = 0x35,
	MLX4_CMD_HW2SW_SRQ	 = 0x36,
	MLX4_CMD_QUERY_SRQ	 = 0x37,
	MLX4_CMD_ARM_SRQ	 = 0x40,

	/* QP/EE commands */
	MLX4_CMD_RST2INIT_QP	 = 0x19,
	MLX4_CMD_INIT2RTR_QP	 = 0x1a,
	MLX4_CMD_RTR2RTS_QP	 = 0x1b,
	MLX4_CMD_RTS2RTS_QP	 = 0x1c,
	MLX4_CMD_SQERR2RTS_QP	 = 0x1d,
	MLX4_CMD_2ERR_QP	 = 0x1e,
	MLX4_CMD_RTS2SQD_QP	 = 0x1f,
	MLX4_CMD_SQD2SQD_QP	 = 0x38,
	MLX4_CMD_SQD2RTS_QP	 = 0x20,
	MLX4_CMD_2RST_QP	 = 0x21,
	MLX4_CMD_QUERY_QP	 = 0x22,
	MLX4_CMD_INIT2INIT_QP	 = 0x2d,
	MLX4_CMD_SUSPEND_QP	 = 0x32,
	MLX4_CMD_UNSUSPEND_QP	 = 0x33,
	MLX4_CMD_UPDATE_QP	 = 0x61,
	/* special QP and management commands */
	MLX4_CMD_CONF_SPECIAL_QP = 0x23,
	MLX4_CMD_MAD_IFC	 = 0x24,
	MLX4_CMD_MAD_DEMUX	 = 0x203,

	/* multicast commands */
	MLX4_CMD_READ_MCG	 = 0x25,
	MLX4_CMD_WRITE_MCG	 = 0x26,
	MLX4_CMD_MGID_HASH	 = 0x27,

	/* miscellaneous commands */
	MLX4_CMD_DIAG_RPRT	 = 0x30,
	MLX4_CMD_NOP		 = 0x31,
	MLX4_CMD_CONFIG_DEV	 = 0x3a,
	MLX4_CMD_ACCESS_MEM	 = 0x2e,
	MLX4_CMD_SET_VEP	 = 0x52,

	/* Ethernet specific commands */
	MLX4_CMD_SET_VLAN_FLTR	 = 0x47,
	MLX4_CMD_SET_MCAST_FLTR	 = 0x48,
	MLX4_CMD_DUMP_ETH_STATS	 = 0x49,

	/* Communication channel commands */
	MLX4_CMD_ARM_COMM_CHANNEL = 0x57,
	MLX4_CMD_GEN_EQE	 = 0x58,

	/* virtual commands */
	MLX4_CMD_ALLOC_RES	 = 0xf00,
	MLX4_CMD_FREE_RES	 = 0xf01,
	MLX4_CMD_MCAST_ATTACH	 = 0xf05,
	MLX4_CMD_UCAST_ATTACH	 = 0xf06,
	MLX4_CMD_PROMISC         = 0xf08,
	MLX4_CMD_QUERY_FUNC_CAP  = 0xf0a,
	MLX4_CMD_QP_ATTACH	 = 0xf0b,

	/* debug commands */
	MLX4_CMD_QUERY_DEBUG_MSG = 0x2a,
	MLX4_CMD_SET_DEBUG_MSG	 = 0x2b,

	/* statistics commands */
	MLX4_CMD_QUERY_IF_STAT	 = 0X54,
	MLX4_CMD_SET_IF_STAT	 = 0X55,

	/* register/delete flow steering network rules */
	MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
	MLX4_QP_FLOW_STEERING_DETACH = 0x66,
	MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
};

enum {
	MLX4_CMD_TIME_CLASS_A	= 10000,
	MLX4_CMD_TIME_CLASS_B	= 10000,
	MLX4_CMD_TIME_CLASS_C	= 10000,
};

enum {
	MLX4_MAILBOX_SIZE	= 4096,
	MLX4_ACCESS_MEM_ALIGN	= 256,
};

enum {
	/* set port opcode modifiers */
	MLX4_SET_PORT_GENERAL   = 0x0,
	MLX4_SET_PORT_RQP_CALC  = 0x1,
	MLX4_SET_PORT_MAC_TABLE = 0x2,
	MLX4_SET_PORT_VLAN_TABLE = 0x3,
	MLX4_SET_PORT_PRIO_MAP  = 0x4,
	MLX4_SET_PORT_GID_TABLE = 0x5,
	MLX4_SET_PORT_PRIO2TC	= 0x8,
	MLX4_SET_PORT_SCHEDULER = 0x9,
	MLX4_SET_PORT_VXLAN	= 0xB
};

enum {
	MLX4_CMD_MAD_DEMUX_CONFIG	= 0,
	MLX4_CMD_MAD_DEMUX_QUERY_STATE	= 1,
	MLX4_CMD_MAD_DEMUX_QUERY_RESTR	= 2, /* Query mad demux restrictions */
};

enum {
	MLX4_CMD_WRAPPED,
	MLX4_CMD_NATIVE
};

/*
 * MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP -
 * Receive checksum value is reported in CQE also for non TCP/UDP packets.
 *
 * MLX4_RX_CSUM_MODE_L4 -
 * L4_CSUM bit in CQE, which indicates whether or not L4 checksum
 * was validated correctly, is supported.
 *
 * MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP -
 * IP_OK CQE's field is supported also for non TCP/UDP IP packets.
 *
 * MLX4_RX_CSUM_MODE_MULTI_VLAN -
 * Receive Checksum offload is supported for packets with more than 2 vlan headers.
 */
enum mlx4_rx_csum_mode {
	MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP		= 1UL << 0,
	MLX4_RX_CSUM_MODE_L4				= 1UL << 1,
	MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP		= 1UL << 2,
	MLX4_RX_CSUM_MODE_MULTI_VLAN			= 1UL << 3
};

struct mlx4_config_dev_params {
	u16	vxlan_udp_dport;
	u8	rx_csum_flags_port_1;
	u8	rx_csum_flags_port_2;
};

struct mlx4_dev;

struct mlx4_cmd_mailbox {
	void		       *buf;
	dma_addr_t		dma;
};

int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
	       int out_is_imm, u32 in_modifier, u8 op_modifier,
	       u16 op, unsigned long timeout, int native);

/* Invoke a command with no output parameter */
static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier,
			   u8 op_modifier, u16 op, unsigned long timeout,
			   int native)
{
	return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier,
			  op_modifier, op, timeout, native);
}

/* Invoke a command with an output mailbox */
static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param,
			       u32 in_modifier, u8 op_modifier, u16 op,
			       unsigned long timeout, int native)
{
	return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier,
			  op_modifier, op, timeout, native);
}

/*
 * Invoke a command with an immediate output parameter (and copy the
 * output into the caller's out_param pointer after the command
 * executes).
 */
static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
			       u32 in_modifier, u8 op_modifier, u16 op,
			       unsigned long timeout, int native)
{
	return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier,
			  op_modifier, op, timeout, native);
}

struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);

u32 mlx4_comm_get_version(void);
int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac);
int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos);
int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf);
int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state);
int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
			      struct mlx4_config_dev_params *params);
void mlx4_cmd_wake_completions(struct mlx4_dev *dev);
void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev);
/*
 * mlx4_get_slave_default_vlan -
 * return true if VST ( default vlan)
 * if VST, will return vlan & qos (if not NULL)
 */
bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
				 u16 *vlan, u8 *qos);

#define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8)
#define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17)

#endif /* MLX4_CMD_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2006 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_CMD_H
	34	#define MLX4_CMD_H
	35
	36	#include <linux/dma-mapping.h>
2cccb9e4	37	#include <linux/if_link.h>
225c7b1f RD	38
	39	enum {
	40	/* initialization and general commands */
	41	MLX4_CMD_SYS_EN = 0x1,
	42	MLX4_CMD_SYS_DIS = 0x2,
	43	MLX4_CMD_MAP_FA = 0xfff,
	44	MLX4_CMD_UNMAP_FA = 0xffe,
	45	MLX4_CMD_RUN_FW = 0xff6,
	46	MLX4_CMD_MOD_STAT_CFG = 0x34,
	47	MLX4_CMD_QUERY_DEV_CAP = 0x3,
	48	MLX4_CMD_QUERY_FW = 0x4,
	49	MLX4_CMD_ENABLE_LAM = 0xff8,
	50	MLX4_CMD_DISABLE_LAM = 0xff7,
	51	MLX4_CMD_QUERY_DDR = 0x5,
	52	MLX4_CMD_QUERY_ADAPTER = 0x6,
	53	MLX4_CMD_INIT_HCA = 0x7,
	54	MLX4_CMD_CLOSE_HCA = 0x8,
	55	MLX4_CMD_INIT_PORT = 0x9,
	56	MLX4_CMD_CLOSE_PORT = 0xa,
	57	MLX4_CMD_QUERY_HCA = 0xb,
5ae2a7a8	58	MLX4_CMD_QUERY_PORT = 0x43,
27bf91d6	59	MLX4_CMD_SENSE_PORT = 0x4d,
e7c1c2c4	60	MLX4_CMD_HW_HEALTH_CHECK = 0x50,
225c7b1f	61	MLX4_CMD_SET_PORT = 0xc,
d0d68b86	62	MLX4_CMD_SET_NODE = 0x5a,
623ed84b	63	MLX4_CMD_QUERY_FUNC = 0x56,
225c7b1f RD	64	MLX4_CMD_ACCESS_DDR = 0x2e,
	65	MLX4_CMD_MAP_ICM = 0xffa,
	66	MLX4_CMD_UNMAP_ICM = 0xff9,
	67	MLX4_CMD_MAP_ICM_AUX = 0xffc,
	68	MLX4_CMD_UNMAP_ICM_AUX = 0xffb,
	69	MLX4_CMD_SET_ICM_SIZE = 0xffd,
adbc7ac5 SM	70	MLX4_CMD_ACCESS_REG = 0x3b,
adbc7ac5 SM	71
623ed84b JM	72	/master notify fw on finish for slave's flr/
623ed84b JM	73	MLX4_CMD_INFORM_FLR_DONE = 0x5b,
fe6f700d	74	MLX4_CMD_GET_OP_REQ = 0x59,
225c7b1f RD	75
	76	/* TPT commands */
	77	MLX4_CMD_SW2HW_MPT = 0xd,
	78	MLX4_CMD_QUERY_MPT = 0xe,
	79	MLX4_CMD_HW2SW_MPT = 0xf,
	80	MLX4_CMD_READ_MTT = 0x10,
	81	MLX4_CMD_WRITE_MTT = 0x11,
	82	MLX4_CMD_SYNC_TPT = 0x2f,
	83
	84	/* EQ commands */
	85	MLX4_CMD_MAP_EQ = 0x12,
	86	MLX4_CMD_SW2HW_EQ = 0x13,
	87	MLX4_CMD_HW2SW_EQ = 0x14,
	88	MLX4_CMD_QUERY_EQ = 0x15,
	89
	90	/* CQ commands */
	91	MLX4_CMD_SW2HW_CQ = 0x16,
	92	MLX4_CMD_HW2SW_CQ = 0x17,
	93	MLX4_CMD_QUERY_CQ = 0x18,
3fdcb97f	94	MLX4_CMD_MODIFY_CQ = 0x2c,
225c7b1f RD	95
	96	/* SRQ commands */
	97	MLX4_CMD_SW2HW_SRQ = 0x35,
	98	MLX4_CMD_HW2SW_SRQ = 0x36,
	99	MLX4_CMD_QUERY_SRQ = 0x37,
	100	MLX4_CMD_ARM_SRQ = 0x40,
	101
	102	/* QP/EE commands */
	103	MLX4_CMD_RST2INIT_QP = 0x19,
	104	MLX4_CMD_INIT2RTR_QP = 0x1a,
	105	MLX4_CMD_RTR2RTS_QP = 0x1b,
	106	MLX4_CMD_RTS2RTS_QP = 0x1c,
	107	MLX4_CMD_SQERR2RTS_QP = 0x1d,
	108	MLX4_CMD_2ERR_QP = 0x1e,
	109	MLX4_CMD_RTS2SQD_QP = 0x1f,
	110	MLX4_CMD_SQD2SQD_QP = 0x38,
	111	MLX4_CMD_SQD2RTS_QP = 0x20,
	112	MLX4_CMD_2RST_QP = 0x21,
	113	MLX4_CMD_QUERY_QP = 0x22,
	114	MLX4_CMD_INIT2INIT_QP = 0x2d,
	115	MLX4_CMD_SUSPEND_QP = 0x32,
	116	MLX4_CMD_UNSUSPEND_QP = 0x33,
b01978ca	117	MLX4_CMD_UPDATE_QP = 0x61,
225c7b1f RD	118	/* special QP and management commands */
	119	MLX4_CMD_CONF_SPECIAL_QP = 0x23,
	120	MLX4_CMD_MAD_IFC = 0x24,
114840c3	121	MLX4_CMD_MAD_DEMUX = 0x203,
225c7b1f RD	122
	123	/* multicast commands */
	124	MLX4_CMD_READ_MCG = 0x25,
	125	MLX4_CMD_WRITE_MCG = 0x26,
	126	MLX4_CMD_MGID_HASH = 0x27,
	127
	128	/* miscellaneous commands */
	129	MLX4_CMD_DIAG_RPRT = 0x30,
	130	MLX4_CMD_NOP = 0x31,
d18f141a	131	MLX4_CMD_CONFIG_DEV = 0x3a,
623ed84b JM	132	MLX4_CMD_ACCESS_MEM = 0x2e,
	133	MLX4_CMD_SET_VEP = 0x52,
	134
	135	/* Ethernet specific commands */
	136	MLX4_CMD_SET_VLAN_FLTR = 0x47,
	137	MLX4_CMD_SET_MCAST_FLTR = 0x48,
	138	MLX4_CMD_DUMP_ETH_STATS = 0x49,
	139
	140	/* Communication channel commands */
	141	MLX4_CMD_ARM_COMM_CHANNEL = 0x57,
	142	MLX4_CMD_GEN_EQE = 0x58,
	143
	144	/* virtual commands */
	145	MLX4_CMD_ALLOC_RES = 0xf00,
	146	MLX4_CMD_FREE_RES = 0xf01,
	147	MLX4_CMD_MCAST_ATTACH = 0xf05,
	148	MLX4_CMD_UCAST_ATTACH = 0xf06,
	149	MLX4_CMD_PROMISC = 0xf08,
	150	MLX4_CMD_QUERY_FUNC_CAP = 0xf0a,
	151	MLX4_CMD_QP_ATTACH = 0xf0b,
225c7b1f RD	152
	153	/* debug commands */
	154	MLX4_CMD_QUERY_DEBUG_MSG = 0x2a,
	155	MLX4_CMD_SET_DEBUG_MSG = 0x2b,
f2a3f6a3 OG	156
	157	/* statistics commands */
	158	MLX4_CMD_QUERY_IF_STAT = 0X54,
623ed84b	159	MLX4_CMD_SET_IF_STAT = 0X55,
e5395e92	160
8fcfb4db HHZ	161	/* register/delete flow steering network rules */
	162	MLX4_QP_FLOW_STEERING_ATTACH = 0x65,
	163	MLX4_QP_FLOW_STEERING_DETACH = 0x66,
4de65803	164	MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64,
225c7b1f RD	165	};
	166
	167	enum {
	168	MLX4_CMD_TIME_CLASS_A = 10000,
	169	MLX4_CMD_TIME_CLASS_B = 10000,
	170	MLX4_CMD_TIME_CLASS_C = 10000,
	171	};
	172
	173	enum {
623ed84b JM	174	MLX4_MAILBOX_SIZE = 4096,
623ed84b JM	175	MLX4_ACCESS_MEM_ALIGN = 256,
225c7b1f RD	176	};
225c7b1f RD	177
2a2336f8 YP	178	enum {
	179	/* set port opcode modifiers */
	180	MLX4_SET_PORT_GENERAL = 0x0,
	181	MLX4_SET_PORT_RQP_CALC = 0x1,
	182	MLX4_SET_PORT_MAC_TABLE = 0x2,
	183	MLX4_SET_PORT_VLAN_TABLE = 0x3,
	184	MLX4_SET_PORT_PRIO_MAP = 0x4,
96dfa684	185	MLX4_SET_PORT_GID_TABLE = 0x5,
5930e8d0 OG	186	MLX4_SET_PORT_PRIO2TC = 0x8,
5930e8d0 OG	187	MLX4_SET_PORT_SCHEDULER = 0x9,
7ffdf726	188	MLX4_SET_PORT_VXLAN = 0xB
2a2336f8 YP	189	};
2a2336f8 YP	190
114840c3 JM	191	enum {
	192	MLX4_CMD_MAD_DEMUX_CONFIG = 0,
	193	MLX4_CMD_MAD_DEMUX_QUERY_STATE = 1,
	194	MLX4_CMD_MAD_DEMUX_QUERY_RESTR = 2, /* Query mad demux restrictions */
	195	};
	196
f9baff50 JM	197	enum {
	198	MLX4_CMD_WRAPPED,
	199	MLX4_CMD_NATIVE
	200	};
	201
d475c95b MB	202	/*
	203	* MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP -
	204	* Receive checksum value is reported in CQE also for non TCP/UDP packets.
	205	*
	206	* MLX4_RX_CSUM_MODE_L4 -
	207	* L4_CSUM bit in CQE, which indicates whether or not L4 checksum
	208	* was validated correctly, is supported.
	209	*
	210	* MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP -
	211	* IP_OK CQE's field is supported also for non TCP/UDP IP packets.
	212	*
	213	* MLX4_RX_CSUM_MODE_MULTI_VLAN -
	214	* Receive Checksum offload is supported for packets with more than 2 vlan headers.
	215	*/
	216	enum mlx4_rx_csum_mode {
	217	MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP = 1UL << 0,
	218	MLX4_RX_CSUM_MODE_L4 = 1UL << 1,
	219	MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP = 1UL << 2,
	220	MLX4_RX_CSUM_MODE_MULTI_VLAN = 1UL << 3
	221	};
	222
	223	struct mlx4_config_dev_params {
	224	u16 vxlan_udp_dport;
	225	u8 rx_csum_flags_port_1;
	226	u8 rx_csum_flags_port_2;
	227	};
	228
225c7b1f RD	229	struct mlx4_dev;
	230
	231	struct mlx4_cmd_mailbox {
	232	void *buf;
	233	dma_addr_t dma;
	234	};
	235
	236	int __mlx4_cmd(struct mlx4_dev dev, u64 in_param, u64 out_param,
	237	int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50	238	u16 op, unsigned long timeout, int native);
225c7b1f RD	239
	240	/* Invoke a command with no output parameter */
	241	static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier,
f9baff50 JM	242	u8 op_modifier, u16 op, unsigned long timeout,
f9baff50 JM	243	int native)
225c7b1f RD	244	{
225c7b1f RD	245	return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier,
f9baff50	246	op_modifier, op, timeout, native);
225c7b1f RD	247	}
	248
	249	/* Invoke a command with an output mailbox */
	250	static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param,
	251	u32 in_modifier, u8 op_modifier, u16 op,
f9baff50	252	unsigned long timeout, int native)
225c7b1f RD	253	{
225c7b1f RD	254	return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier,
f9baff50	255	op_modifier, op, timeout, native);
225c7b1f RD	256	}
	257
	258	/*
	259	* Invoke a command with an immediate output parameter (and copy the
	260	* output into the caller's out_param pointer after the command
	261	* executes).
	262	*/
	263	static inline int mlx4_cmd_imm(struct mlx4_dev dev, u64 in_param, u64 out_param,
	264	u32 in_modifier, u8 op_modifier, u16 op,
f9baff50	265	unsigned long timeout, int native)
225c7b1f RD	266	{
225c7b1f RD	267	return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier,
f9baff50	268	op_modifier, op, timeout, native);
225c7b1f RD	269	}
	270
	271	struct mlx4_cmd_mailbox mlx4_alloc_cmd_mailbox(struct mlx4_dev dev);
	272	void mlx4_free_cmd_mailbox(struct mlx4_dev dev, struct mlx4_cmd_mailbox mailbox);
	273
623ed84b	274	u32 mlx4_comm_get_version(void);
8f7ba3ca	275	int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac);
3f7fb021	276	int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos);
e6b6a231	277	int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting);
2cccb9e4	278	int mlx4_get_vf_config(struct mlx4_dev dev, int port, int vf, struct ifla_vf_info ivf);
948e306d	279	int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state);
d475c95b MB	280	int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
d475c95b MB	281	struct mlx4_config_dev_params *params);
f5aef5aa	282	void mlx4_cmd_wake_completions(struct mlx4_dev *dev);
55ad3592	283	void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev);
5ea8bbfc JM	284	/*
	285	* mlx4_get_slave_default_vlan -
	286	* return true if VST ( default vlan)
	287	* if VST, will return vlan & qos (if not NULL)
	288	*/
	289	bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
	290	u16 vlan, u8 qos);
623ed84b	291
ab9c17a0	292	#define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8)
55ad3592	293	#define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17)
ab9c17a0	294
225c7b1f	295	#endif /* MLX4_CMD_H */