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1 | /* |
2 | * Copyright (C) 2015 Microchip Technology | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef _MICROCHIPPHY_H | |
19 | #define _MICROCHIPPHY_H | |
20 | ||
21 | #define LAN88XX_INT_MASK (0x19) | |
22 | #define LAN88XX_INT_MASK_MDINTPIN_EN_ (0x8000) | |
23 | #define LAN88XX_INT_MASK_SPEED_CHANGE_ (0x4000) | |
24 | #define LAN88XX_INT_MASK_LINK_CHANGE_ (0x2000) | |
25 | #define LAN88XX_INT_MASK_FDX_CHANGE_ (0x1000) | |
26 | #define LAN88XX_INT_MASK_AUTONEG_ERR_ (0x0800) | |
27 | #define LAN88XX_INT_MASK_AUTONEG_DONE_ (0x0400) | |
28 | #define LAN88XX_INT_MASK_POE_DETECT_ (0x0200) | |
29 | #define LAN88XX_INT_MASK_SYMBOL_ERR_ (0x0100) | |
30 | #define LAN88XX_INT_MASK_FAST_LINK_FAIL_ (0x0080) | |
31 | #define LAN88XX_INT_MASK_WOL_EVENT_ (0x0040) | |
32 | #define LAN88XX_INT_MASK_EXTENDED_INT_ (0x0020) | |
33 | #define LAN88XX_INT_MASK_RESERVED_ (0x0010) | |
34 | #define LAN88XX_INT_MASK_FALSE_CARRIER_ (0x0008) | |
35 | #define LAN88XX_INT_MASK_LINK_SPEED_DS_ (0x0004) | |
36 | #define LAN88XX_INT_MASK_MASTER_SLAVE_DONE_ (0x0002) | |
37 | #define LAN88XX_INT_MASK_RX__ER_ (0x0001) | |
38 | ||
39 | #define LAN88XX_INT_STS (0x1A) | |
40 | #define LAN88XX_INT_STS_INT_ACTIVE_ (0x8000) | |
41 | #define LAN88XX_INT_STS_SPEED_CHANGE_ (0x4000) | |
42 | #define LAN88XX_INT_STS_LINK_CHANGE_ (0x2000) | |
43 | #define LAN88XX_INT_STS_FDX_CHANGE_ (0x1000) | |
44 | #define LAN88XX_INT_STS_AUTONEG_ERR_ (0x0800) | |
45 | #define LAN88XX_INT_STS_AUTONEG_DONE_ (0x0400) | |
46 | #define LAN88XX_INT_STS_POE_DETECT_ (0x0200) | |
47 | #define LAN88XX_INT_STS_SYMBOL_ERR_ (0x0100) | |
48 | #define LAN88XX_INT_STS_FAST_LINK_FAIL_ (0x0080) | |
49 | #define LAN88XX_INT_STS_WOL_EVENT_ (0x0040) | |
50 | #define LAN88XX_INT_STS_EXTENDED_INT_ (0x0020) | |
51 | #define LAN88XX_INT_STS_RESERVED_ (0x0010) | |
52 | #define LAN88XX_INT_STS_FALSE_CARRIER_ (0x0008) | |
53 | #define LAN88XX_INT_STS_LINK_SPEED_DS_ (0x0004) | |
54 | #define LAN88XX_INT_STS_MASTER_SLAVE_DONE_ (0x0002) | |
55 | #define LAN88XX_INT_STS_RX_ER_ (0x0001) | |
56 | ||
57 | #define LAN88XX_EXT_PAGE_ACCESS (0x1F) | |
58 | #define LAN88XX_EXT_PAGE_SPACE_0 (0x0000) | |
59 | #define LAN88XX_EXT_PAGE_SPACE_1 (0x0001) | |
60 | #define LAN88XX_EXT_PAGE_SPACE_2 (0x0002) | |
61 | ||
62 | /* Extended Register Page 1 space */ | |
63 | #define LAN88XX_EXT_MODE_CTRL (0x13) | |
64 | #define LAN88XX_EXT_MODE_CTRL_MDIX_MASK_ (0x000C) | |
65 | #define LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_ (0x0000) | |
66 | #define LAN88XX_EXT_MODE_CTRL_MDI_ (0x0008) | |
67 | #define LAN88XX_EXT_MODE_CTRL_MDI_X_ (0x000C) | |
68 | ||
69 | /* MMD 3 Registers */ | |
70 | #define LAN88XX_MMD3_CHIP_ID (32877) | |
71 | #define LAN88XX_MMD3_CHIP_REV (32878) | |
72 | ||
1c2734b3 RC |
73 | /* DSP registers */ |
74 | #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG (0x806A) | |
75 | #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_ (0x2000) | |
76 | #define LAN88XX_EXT_PAGE_ACCESS_TR (0x52B5) | |
77 | #define LAN88XX_EXT_PAGE_TR_CR 16 | |
78 | #define LAN88XX_EXT_PAGE_TR_LOW_DATA 17 | |
79 | #define LAN88XX_EXT_PAGE_TR_HIGH_DATA 18 | |
80 | ||
792aec47 | 81 | #endif /* _MICROCHIPPHY_H */ |