block: remove QUEUE_FLAG_DISCARD
[linux-block.git] / include / linux / mhi.h
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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 */
6#ifndef _MHI_H_
7#define _MHI_H_
8
9#include <linux/device.h>
10#include <linux/dma-direction.h>
11#include <linux/mutex.h>
189ff97c 12#include <linux/skbuff.h>
0cbf2608 13#include <linux/slab.h>
e1427f32 14#include <linux/spinlock.h>
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15#include <linux/wait.h>
16#include <linux/workqueue.h>
17
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18#define MHI_MAX_OEM_PK_HASH_SEGMENTS 16
19
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20struct mhi_chan;
21struct mhi_event;
22struct mhi_ctxt;
23struct mhi_cmd;
24struct mhi_buf_info;
25
26/**
27 * enum mhi_callback - MHI callback
28 * @MHI_CB_IDLE: MHI entered idle state
29 * @MHI_CB_PENDING_DATA: New data available for client to process
30 * @MHI_CB_LPM_ENTER: MHI host entered low power mode
31 * @MHI_CB_LPM_EXIT: MHI host about to exit low power mode
32 * @MHI_CB_EE_RDDM: MHI device entered RDDM exec env
33 * @MHI_CB_EE_MISSION_MODE: MHI device entered Mission Mode exec env
34 * @MHI_CB_SYS_ERROR: MHI device entered error state (may recover)
35 * @MHI_CB_FATAL_ERROR: MHI device entered fatal error state
1d3173a3 36 * @MHI_CB_BW_REQ: Received a bandwidth switch request from device
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37 */
38enum mhi_callback {
39 MHI_CB_IDLE,
40 MHI_CB_PENDING_DATA,
41 MHI_CB_LPM_ENTER,
42 MHI_CB_LPM_EXIT,
43 MHI_CB_EE_RDDM,
44 MHI_CB_EE_MISSION_MODE,
45 MHI_CB_SYS_ERROR,
46 MHI_CB_FATAL_ERROR,
1d3173a3 47 MHI_CB_BW_REQ,
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48};
49
50/**
51 * enum mhi_flags - Transfer flags
52 * @MHI_EOB: End of buffer for bulk transfer
53 * @MHI_EOT: End of transfer
54 * @MHI_CHAIN: Linked transfer
55 */
56enum mhi_flags {
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57 MHI_EOB = BIT(0),
58 MHI_EOT = BIT(1),
59 MHI_CHAIN = BIT(2),
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60};
61
62/**
63 * enum mhi_device_type - Device types
64 * @MHI_DEVICE_XFER: Handles data transfer
65 * @MHI_DEVICE_CONTROLLER: Control device
66 */
67enum mhi_device_type {
68 MHI_DEVICE_XFER,
69 MHI_DEVICE_CONTROLLER,
70};
71
72/**
73 * enum mhi_ch_type - Channel types
74 * @MHI_CH_TYPE_INVALID: Invalid channel type
75 * @MHI_CH_TYPE_OUTBOUND: Outbound channel to the device
76 * @MHI_CH_TYPE_INBOUND: Inbound channel from the device
77 * @MHI_CH_TYPE_INBOUND_COALESCED: Coalesced channel for the device to combine
78 * multiple packets and send them as a single
79 * large packet to reduce CPU consumption
80 */
81enum mhi_ch_type {
82 MHI_CH_TYPE_INVALID = 0,
83 MHI_CH_TYPE_OUTBOUND = DMA_TO_DEVICE,
84 MHI_CH_TYPE_INBOUND = DMA_FROM_DEVICE,
85 MHI_CH_TYPE_INBOUND_COALESCED = 3,
86};
87
3000f85b 88/**
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89 * struct image_info - Firmware and RDDM table
90 * @mhi_buf: Buffer for firmware and RDDM table
91 * @entries: # of entries in table
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92 */
93struct image_info {
94 struct mhi_buf *mhi_buf;
4d12a897 95 /* private: from internal.h */
3000f85b 96 struct bhi_vec_entry *bhi_vec;
4d12a897 97 /* public: */
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98 u32 entries;
99};
100
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101/**
102 * struct mhi_link_info - BW requirement
103 * target_link_speed - Link speed as defined by TLS bits in LinkControl reg
104 * target_link_width - Link width as defined by NLW bits in LinkStatus reg
105 */
106struct mhi_link_info {
107 unsigned int target_link_speed;
108 unsigned int target_link_width;
109};
110
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111/**
112 * enum mhi_ee_type - Execution environment types
113 * @MHI_EE_PBL: Primary Bootloader
114 * @MHI_EE_SBL: Secondary Bootloader
115 * @MHI_EE_AMSS: Modem, aka the primary runtime EE
116 * @MHI_EE_RDDM: Ram dump download mode
117 * @MHI_EE_WFW: WLAN firmware mode
118 * @MHI_EE_PTHRU: Passthrough
119 * @MHI_EE_EDL: Embedded downloader
66ac7985 120 * @MHI_EE_FP: Flash Programmer Environment
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121 */
122enum mhi_ee_type {
123 MHI_EE_PBL,
124 MHI_EE_SBL,
125 MHI_EE_AMSS,
126 MHI_EE_RDDM,
127 MHI_EE_WFW,
128 MHI_EE_PTHRU,
129 MHI_EE_EDL,
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130 MHI_EE_FP,
131 MHI_EE_MAX_SUPPORTED = MHI_EE_FP,
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132 MHI_EE_DISABLE_TRANSITION, /* local EE, not related to mhi spec */
133 MHI_EE_NOT_SUPPORTED,
134 MHI_EE_MAX,
135};
136
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137/**
138 * enum mhi_state - MHI states
139 * @MHI_STATE_RESET: Reset state
140 * @MHI_STATE_READY: Ready state
141 * @MHI_STATE_M0: M0 state
142 * @MHI_STATE_M1: M1 state
143 * @MHI_STATE_M2: M2 state
144 * @MHI_STATE_M3: M3 state
145 * @MHI_STATE_M3_FAST: M3 Fast state
146 * @MHI_STATE_BHI: BHI state
147 * @MHI_STATE_SYS_ERR: System Error state
148 */
149enum mhi_state {
150 MHI_STATE_RESET = 0x0,
151 MHI_STATE_READY = 0x1,
152 MHI_STATE_M0 = 0x2,
153 MHI_STATE_M1 = 0x3,
154 MHI_STATE_M2 = 0x4,
155 MHI_STATE_M3 = 0x5,
156 MHI_STATE_M3_FAST = 0x6,
157 MHI_STATE_BHI = 0x7,
158 MHI_STATE_SYS_ERR = 0xFF,
159 MHI_STATE_MAX,
160};
161
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162/**
163 * enum mhi_ch_ee_mask - Execution environment mask for channel
164 * @MHI_CH_EE_PBL: Allow channel to be used in PBL EE
165 * @MHI_CH_EE_SBL: Allow channel to be used in SBL EE
166 * @MHI_CH_EE_AMSS: Allow channel to be used in AMSS EE
167 * @MHI_CH_EE_RDDM: Allow channel to be used in RDDM EE
168 * @MHI_CH_EE_PTHRU: Allow channel to be used in PTHRU EE
169 * @MHI_CH_EE_WFW: Allow channel to be used in WFW EE
170 * @MHI_CH_EE_EDL: Allow channel to be used in EDL EE
171 */
172enum mhi_ch_ee_mask {
173 MHI_CH_EE_PBL = BIT(MHI_EE_PBL),
174 MHI_CH_EE_SBL = BIT(MHI_EE_SBL),
175 MHI_CH_EE_AMSS = BIT(MHI_EE_AMSS),
176 MHI_CH_EE_RDDM = BIT(MHI_EE_RDDM),
177 MHI_CH_EE_PTHRU = BIT(MHI_EE_PTHRU),
178 MHI_CH_EE_WFW = BIT(MHI_EE_WFW),
179 MHI_CH_EE_EDL = BIT(MHI_EE_EDL),
180};
181
182/**
183 * enum mhi_er_data_type - Event ring data types
184 * @MHI_ER_DATA: Only client data over this ring
185 * @MHI_ER_CTRL: MHI control data and client data
186 */
187enum mhi_er_data_type {
188 MHI_ER_DATA,
189 MHI_ER_CTRL,
190};
191
192/**
193 * enum mhi_db_brst_mode - Doorbell mode
194 * @MHI_DB_BRST_DISABLE: Burst mode disable
195 * @MHI_DB_BRST_ENABLE: Burst mode enable
196 */
197enum mhi_db_brst_mode {
198 MHI_DB_BRST_DISABLE = 0x2,
199 MHI_DB_BRST_ENABLE = 0x3,
200};
201
202/**
203 * struct mhi_channel_config - Channel configuration structure for controller
204 * @name: The name of this channel
205 * @num: The number assigned to this channel
206 * @num_elements: The number of elements that can be queued to this channel
207 * @local_elements: The local ring length of the channel
a503d162 208 * @event_ring: The event ring index that services this channel
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209 * @dir: Direction that data may flow on this channel
210 * @type: Channel type
211 * @ee_mask: Execution Environment mask for this channel
212 * @pollcfg: Polling configuration for burst mode. 0 is default. milliseconds
213 for UL channels, multiple of 8 ring elements for DL channels
214 * @doorbell: Doorbell mode
215 * @lpm_notify: The channel master requires low power mode notifications
216 * @offload_channel: The client manages the channel completely
217 * @doorbell_mode_switch: Channel switches to doorbell mode on M0 transition
218 * @auto_queue: Framework will automatically queue buffers for DL traffic
da1c4f85 219 * @wake-capable: Channel capable of waking up the system
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220 */
221struct mhi_channel_config {
222 char *name;
223 u32 num;
224 u32 num_elements;
225 u32 local_elements;
226 u32 event_ring;
227 enum dma_data_direction dir;
228 enum mhi_ch_type type;
229 u32 ee_mask;
230 u32 pollcfg;
231 enum mhi_db_brst_mode doorbell;
232 bool lpm_notify;
233 bool offload_channel;
234 bool doorbell_mode_switch;
235 bool auto_queue;
da1c4f85 236 bool wake_capable;
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237};
238
239/**
240 * struct mhi_event_config - Event ring configuration structure for controller
241 * @num_elements: The number of elements that can be queued to this ring
242 * @irq_moderation_ms: Delay irq for additional events to be aggregated
243 * @irq: IRQ associated with this ring
244 * @channel: Dedicated channel number. U32_MAX indicates a non-dedicated ring
245 * @priority: Priority of this ring. Use 1 for now
246 * @mode: Doorbell mode
247 * @data_type: Type of data this ring will process
248 * @hardware_event: This ring is associated with hardware channels
249 * @client_managed: This ring is client managed
250 * @offload_channel: This ring is associated with an offloaded channel
251 */
252struct mhi_event_config {
253 u32 num_elements;
254 u32 irq_moderation_ms;
255 u32 irq;
256 u32 channel;
257 u32 priority;
258 enum mhi_db_brst_mode mode;
259 enum mhi_er_data_type data_type;
260 bool hardware_event;
261 bool client_managed;
262 bool offload_channel;
263};
264
265/**
266 * struct mhi_controller_config - Root MHI controller configuration
267 * @max_channels: Maximum number of channels supported
268 * @timeout_ms: Timeout value for operations. 0 means use default
269 * @buf_len: Size of automatically allocated buffers. 0 means use default
270 * @num_channels: Number of channels defined in @ch_cfg
271 * @ch_cfg: Array of defined channels
272 * @num_events: Number of event rings defined in @event_cfg
273 * @event_cfg: Array of defined event rings
274 * @use_bounce_buf: Use a bounce buffer pool due to limited DDR access
275 * @m2_no_db: Host is not allowed to ring DB in M2 state
276 */
277struct mhi_controller_config {
278 u32 max_channels;
279 u32 timeout_ms;
280 u32 buf_len;
281 u32 num_channels;
f38173a7 282 const struct mhi_channel_config *ch_cfg;
0cbf2608 283 u32 num_events;
fcba4b20 284 struct mhi_event_config *event_cfg;
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285 bool use_bounce_buf;
286 bool m2_no_db;
287};
288
289/**
290 * struct mhi_controller - Master MHI controller structure
291 * @cntrl_dev: Pointer to the struct device of physical bus acting as the MHI
292 * controller (required)
293 * @mhi_dev: MHI device instance for the controller
c7bd825e 294 * @debugfs_dentry: MHI controller debugfs directory
0cbf2608 295 * @regs: Base address of MHI MMIO register space (required)
6cd330ae 296 * @bhi: Points to base of MHI BHI register space
3000f85b 297 * @bhie: Points to base of MHI BHIe register space
6cd330ae 298 * @wake_db: MHI WAKE doorbell register address
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299 * @iova_start: IOMMU starting address for data (required)
300 * @iova_stop: IOMMU stop address for data (required)
4d5f5283 301 * @fw_image: Firmware image name for normal booting (optional)
0cbf2608 302 * @edl_image: Firmware image name for emergency download mode (optional)
6fdfdd27 303 * @rddm_size: RAM dump size that host should allocate for debugging purpose
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304 * @sbl_size: SBL image size downloaded through BHIe (optional)
305 * @seg_len: BHIe vector size (optional)
baa7a085 306 * @reg_len: Length of the MHI MMIO region (required)
3000f85b 307 * @fbc_image: Points to firmware image buffer
6fdfdd27 308 * @rddm_image: Points to RAM dump buffer
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309 * @mhi_chan: Points to the channel configuration table
310 * @lpm_chans: List of channels that require LPM notifications
311 * @irq: base irq # to request (required)
312 * @max_chan: Maximum number of channels the controller supports
313 * @total_ev_rings: Total # of event rings allocated
314 * @hw_ev_rings: Number of hardware event rings
315 * @sw_ev_rings: Number of software event rings
0cbf2608 316 * @nr_irqs: Number of IRQ allocated by bus master (required)
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317 * @family_number: MHI controller family number
318 * @device_number: MHI controller device number
319 * @major_version: MHI controller major revision number
320 * @minor_version: MHI controller minor revision number
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321 * @serial_number: MHI controller serial number obtained from BHI
322 * @oem_pk_hash: MHI controller OEM PK Hash obtained from BHI
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323 * @mhi_event: MHI event ring configurations table
324 * @mhi_cmd: MHI command ring configurations table
325 * @mhi_ctxt: MHI device context, shared memory between host and device
326 * @pm_mutex: Mutex for suspend/resume operation
327 * @pm_lock: Lock for protecting MHI power management state
328 * @timeout_ms: Timeout in ms for state transitions
329 * @pm_state: MHI power management state
330 * @db_access: DB access states
331 * @ee: MHI device execution environment
a6e2e352 332 * @dev_state: MHI device state
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333 * @dev_wake: Device wakeup count
334 * @pending_pkts: Pending packets for the controller
601455da 335 * @M0, M2, M3: Counters to track number of device MHI state changes
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336 * @transition_list: List of MHI state transitions
337 * @transition_lock: Lock for protecting MHI state transition list
338 * @wlock: Lock for protecting device wakeup
1d3173a3 339 * @mhi_link_info: Device bandwidth info
0cbf2608 340 * @st_worker: State transition worker
8f703978 341 * @hiprio_wq: High priority workqueue for MHI work such as state transitions
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342 * @state_event: State change event
343 * @status_cb: CB function to notify power states of the device (required)
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344 * @wake_get: CB function to assert device wake (optional)
345 * @wake_put: CB function to de-assert device wake (optional)
346 * @wake_toggle: CB function to assert and de-assert device wake (optional)
347 * @runtime_get: CB function to controller runtime resume (required)
af2e5881 348 * @runtime_put: CB function to decrement pm usage (required)
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349 * @map_single: CB function to create TRE buffer
350 * @unmap_single: CB function to destroy TRE buffer
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351 * @read_reg: Read a MHI register via the physical link (required)
352 * @write_reg: Write a MHI register via the physical link (required)
b5a8d233 353 * @reset: Controller specific reset function (optional)
0cbf2608 354 * @buffer_len: Bounce buffer length
206e7383 355 * @index: Index of the MHI controller instance
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356 * @bounce_buf: Use of bounce buffer
357 * @fbc_download: MHI host needs to do complete image transfer (optional)
0cbf2608 358 * @wake_set: Device wakeup set flag
6ffcc18d 359 * @irq_flags: irq flags passed to request_irq (optional)
5c2c8531 360 * @mru: the default MRU for the MHI device
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361 *
362 * Fields marked as (required) need to be populated by the controller driver
363 * before calling mhi_register_controller(). For the fields marked as (optional)
364 * they can be populated depending on the usecase.
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365 *
366 * The following fields are present for the purpose of implementing any device
367 * specific quirks or customizations for specific MHI revisions used in device
368 * by the controller drivers. The MHI stack will just populate these fields
369 * during mhi_register_controller():
370 * family_number
371 * device_number
372 * major_version
373 * minor_version
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374 */
375struct mhi_controller {
376 struct device *cntrl_dev;
377 struct mhi_device *mhi_dev;
c7bd825e 378 struct dentry *debugfs_dentry;
0cbf2608 379 void __iomem *regs;
6cd330ae 380 void __iomem *bhi;
3000f85b 381 void __iomem *bhie;
6cd330ae 382 void __iomem *wake_db;
a6e2e352 383
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384 dma_addr_t iova_start;
385 dma_addr_t iova_stop;
386 const char *fw_image;
387 const char *edl_image;
6fdfdd27 388 size_t rddm_size;
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389 size_t sbl_size;
390 size_t seg_len;
baa7a085 391 size_t reg_len;
3000f85b 392 struct image_info *fbc_image;
6fdfdd27 393 struct image_info *rddm_image;
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394 struct mhi_chan *mhi_chan;
395 struct list_head lpm_chans;
396 int *irq;
397 u32 max_chan;
398 u32 total_ev_rings;
399 u32 hw_ev_rings;
400 u32 sw_ev_rings;
0cbf2608 401 u32 nr_irqs;
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402 u32 family_number;
403 u32 device_number;
404 u32 major_version;
405 u32 minor_version;
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406 u32 serial_number;
407 u32 oem_pk_hash[MHI_MAX_OEM_PK_HASH_SEGMENTS];
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408
409 struct mhi_event *mhi_event;
410 struct mhi_cmd *mhi_cmd;
411 struct mhi_ctxt *mhi_ctxt;
412
413 struct mutex pm_mutex;
414 rwlock_t pm_lock;
415 u32 timeout_ms;
416 u32 pm_state;
417 u32 db_access;
418 enum mhi_ee_type ee;
a6e2e352 419 enum mhi_state dev_state;
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420 atomic_t dev_wake;
421 atomic_t pending_pkts;
601455da 422 u32 M0, M2, M3;
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423 struct list_head transition_list;
424 spinlock_t transition_lock;
425 spinlock_t wlock;
1d3173a3 426 struct mhi_link_info mhi_link_info;
0cbf2608 427 struct work_struct st_worker;
8f703978 428 struct workqueue_struct *hiprio_wq;
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429 wait_queue_head_t state_event;
430
431 void (*status_cb)(struct mhi_controller *mhi_cntrl,
432 enum mhi_callback cb);
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433 void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override);
434 void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override);
435 void (*wake_toggle)(struct mhi_controller *mhi_cntrl);
436 int (*runtime_get)(struct mhi_controller *mhi_cntrl);
437 void (*runtime_put)(struct mhi_controller *mhi_cntrl);
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438 int (*map_single)(struct mhi_controller *mhi_cntrl,
439 struct mhi_buf_info *buf);
440 void (*unmap_single)(struct mhi_controller *mhi_cntrl,
441 struct mhi_buf_info *buf);
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442 int (*read_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
443 u32 *out);
444 void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *addr,
445 u32 val);
b5a8d233 446 void (*reset)(struct mhi_controller *mhi_cntrl);
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447
448 size_t buffer_len;
206e7383 449 int index;
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450 bool bounce_buf;
451 bool fbc_download;
0cbf2608 452 bool wake_set;
6ffcc18d 453 unsigned long irq_flags;
5c2c8531 454 u32 mru;
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455};
456
457/**
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458 * struct mhi_device - Structure representing an MHI device which binds
459 * to channels or is associated with controllers
0cbf2608 460 * @id: Pointer to MHI device ID struct
5aa93f05 461 * @name: Name of the associated MHI device
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462 * @mhi_cntrl: Controller the device belongs to
463 * @ul_chan: UL channel for the device
464 * @dl_chan: DL channel for the device
465 * @dev: Driver model device node for the MHI device
466 * @dev_type: MHI device type
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467 * @ul_chan_id: MHI channel id for UL transfer
468 * @dl_chan_id: MHI channel id for DL transfer
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469 * @dev_wake: Device wakeup counter
470 */
471struct mhi_device {
472 const struct mhi_device_id *id;
5aa93f05 473 const char *name;
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474 struct mhi_controller *mhi_cntrl;
475 struct mhi_chan *ul_chan;
476 struct mhi_chan *dl_chan;
477 struct device dev;
478 enum mhi_device_type dev_type;
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479 int ul_chan_id;
480 int dl_chan_id;
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481 u32 dev_wake;
482};
483
484/**
485 * struct mhi_result - Completed buffer information
486 * @buf_addr: Address of data buffer
487 * @bytes_xferd: # of bytes transferred
488 * @dir: Channel direction
489 * @transaction_status: Status of last transaction
490 */
491struct mhi_result {
492 void *buf_addr;
493 size_t bytes_xferd;
494 enum dma_data_direction dir;
495 int transaction_status;
496};
497
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498/**
499 * struct mhi_buf - MHI Buffer description
500 * @buf: Virtual address of the buffer
501 * @name: Buffer label. For offload channel, configurations name must be:
502 * ECA - Event context array data
503 * CCA - Channel context array data
504 * @dma_addr: IOMMU address of the buffer
505 * @len: # of bytes
506 */
507struct mhi_buf {
508 void *buf;
509 const char *name;
510 dma_addr_t dma_addr;
511 size_t len;
512};
513
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514/**
515 * struct mhi_driver - Structure representing a MHI client driver
516 * @probe: CB function for client driver probe function
517 * @remove: CB function for client driver remove function
518 * @ul_xfer_cb: CB function for UL data transfer
519 * @dl_xfer_cb: CB function for DL data transfer
520 * @status_cb: CB functions for asynchronous status
521 * @driver: Device driver model driver
522 */
523struct mhi_driver {
524 const struct mhi_device_id *id_table;
525 int (*probe)(struct mhi_device *mhi_dev,
526 const struct mhi_device_id *id);
527 void (*remove)(struct mhi_device *mhi_dev);
528 void (*ul_xfer_cb)(struct mhi_device *mhi_dev,
529 struct mhi_result *result);
530 void (*dl_xfer_cb)(struct mhi_device *mhi_dev,
531 struct mhi_result *result);
532 void (*status_cb)(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb);
533 struct device_driver driver;
534};
535
536#define to_mhi_driver(drv) container_of(drv, struct mhi_driver, driver)
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537#define to_mhi_device(dev) container_of(dev, struct mhi_device, dev)
538
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539/**
540 * mhi_alloc_controller - Allocate the MHI Controller structure
541 * Allocate the mhi_controller structure using zero initialized memory
542 */
543struct mhi_controller *mhi_alloc_controller(void);
544
545/**
546 * mhi_free_controller - Free the MHI Controller structure
547 * Free the mhi_controller structure which was previously allocated
548 */
549void mhi_free_controller(struct mhi_controller *mhi_cntrl);
550
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551/**
552 * mhi_register_controller - Register MHI controller
553 * @mhi_cntrl: MHI controller to register
554 * @config: Configuration to use for the controller
555 */
556int mhi_register_controller(struct mhi_controller *mhi_cntrl,
f38173a7 557 const struct mhi_controller_config *config);
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558
559/**
560 * mhi_unregister_controller - Unregister MHI controller
561 * @mhi_cntrl: MHI controller to unregister
562 */
563void mhi_unregister_controller(struct mhi_controller *mhi_cntrl);
564
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565/*
566 * module_mhi_driver() - Helper macro for drivers that don't do
567 * anything special other than using default mhi_driver_register() and
568 * mhi_driver_unregister(). This eliminates a lot of boilerplate.
569 * Each module may only use this macro once.
570 */
571#define module_mhi_driver(mhi_drv) \
572 module_driver(mhi_drv, mhi_driver_register, \
573 mhi_driver_unregister)
574
575/*
576 * Macro to avoid include chaining to get THIS_MODULE
577 */
578#define mhi_driver_register(mhi_drv) \
579 __mhi_driver_register(mhi_drv, THIS_MODULE)
580
e755cadb 581/**
82174738 582 * __mhi_driver_register - Register driver with MHI framework
e755cadb 583 * @mhi_drv: Driver associated with the device
82174738 584 * @owner: The module owner
e755cadb 585 */
82174738 586int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner);
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587
588/**
589 * mhi_driver_unregister - Unregister a driver for mhi_devices
590 * @mhi_drv: Driver associated with the device
591 */
592void mhi_driver_unregister(struct mhi_driver *mhi_drv);
593
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594/**
595 * mhi_set_mhi_state - Set MHI device state
596 * @mhi_cntrl: MHI controller
597 * @state: State to set
598 */
599void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl,
600 enum mhi_state state);
601
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602/**
603 * mhi_notify - Notify the MHI client driver about client device status
604 * @mhi_dev: MHI device instance
605 * @cb_reason: MHI callback reason
606 */
607void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason);
608
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609/**
610 * mhi_get_free_desc_count - Get transfer ring length
611 * Get # of TD available to queue buffers
612 * @mhi_dev: Device associated with the channels
613 * @dir: Direction of the channel
614 */
615int mhi_get_free_desc_count(struct mhi_device *mhi_dev,
616 enum dma_data_direction dir);
617
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618/**
619 * mhi_prepare_for_power_up - Do pre-initialization before power up.
620 * This is optional, call this before power up if
621 * the controller does not want bus framework to
622 * automatically free any allocated memory during
623 * shutdown process.
624 * @mhi_cntrl: MHI controller
625 */
626int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl);
627
628/**
629 * mhi_async_power_up - Start MHI power up sequence
630 * @mhi_cntrl: MHI controller
631 */
632int mhi_async_power_up(struct mhi_controller *mhi_cntrl);
633
634/**
635 * mhi_sync_power_up - Start MHI power up sequence and wait till the device
4d12a897 636 * enters valid EE state
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637 * @mhi_cntrl: MHI controller
638 */
639int mhi_sync_power_up(struct mhi_controller *mhi_cntrl);
640
641/**
642 * mhi_power_down - Start MHI power down sequence
643 * @mhi_cntrl: MHI controller
644 * @graceful: Link is still accessible, so do a graceful shutdown process
645 */
646void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful);
647
648/**
649 * mhi_unprepare_after_power_down - Free any allocated memory after power down
650 * @mhi_cntrl: MHI controller
651 */
652void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl);
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653
654/**
655 * mhi_pm_suspend - Move MHI into a suspended state
656 * @mhi_cntrl: MHI controller
657 */
658int mhi_pm_suspend(struct mhi_controller *mhi_cntrl);
659
660/**
661 * mhi_pm_resume - Resume MHI from suspended state
662 * @mhi_cntrl: MHI controller
663 */
664int mhi_pm_resume(struct mhi_controller *mhi_cntrl);
3000f85b 665
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666/**
667 * mhi_pm_resume_force - Force resume MHI from suspended state
668 * @mhi_cntrl: MHI controller
669 *
670 * Resume the device irrespective of its MHI state. As per the MHI spec, devices
671 * has to be in M3 state during resume. But some devices seem to be in a
672 * different MHI state other than M3 but they continue working fine if allowed.
673 * This API is intented to be used for such devices.
674 *
675 * Return: 0 if the resume succeeds, a negative error code otherwise
676 */
677int mhi_pm_resume_force(struct mhi_controller *mhi_cntrl);
678
6fdfdd27 679/**
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680 * mhi_download_rddm_image - Download ramdump image from device for
681 * debugging purpose.
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682 * @mhi_cntrl: MHI controller
683 * @in_panic: Download rddm image during kernel panic
684 */
9e1660e5 685int mhi_download_rddm_image(struct mhi_controller *mhi_cntrl, bool in_panic);
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686
687/**
688 * mhi_force_rddm_mode - Force device into rddm mode
689 * @mhi_cntrl: MHI controller
690 */
691int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl);
692
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693/**
694 * mhi_get_exec_env - Get BHI execution environment of the device
695 * @mhi_cntrl: MHI controller
696 */
697enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl);
698
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699/**
700 * mhi_get_mhi_state - Get MHI state of the device
701 * @mhi_cntrl: MHI controller
702 */
703enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl);
704
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705/**
706 * mhi_soc_reset - Trigger a device reset. This can be used as a last resort
707 * to reset and recover a device.
708 * @mhi_cntrl: MHI controller
709 */
710void mhi_soc_reset(struct mhi_controller *mhi_cntrl);
711
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712/**
713 * mhi_device_get - Disable device low power mode
714 * @mhi_dev: Device associated with the channel
715 */
716void mhi_device_get(struct mhi_device *mhi_dev);
717
718/**
719 * mhi_device_get_sync - Disable device low power mode. Synchronously
720 * take the controller out of suspended state
721 * @mhi_dev: Device associated with the channel
722 */
723int mhi_device_get_sync(struct mhi_device *mhi_dev);
724
725/**
726 * mhi_device_put - Re-enable device low power mode
727 * @mhi_dev: Device associated with the channel
728 */
729void mhi_device_put(struct mhi_device *mhi_dev);
730
731/**
6731fefd 732 * mhi_prepare_for_transfer - Setup UL and DL channels for data transfer.
189ff97c 733 * @mhi_dev: Device associated with the channels
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734 *
735 * Allocate and initialize the channel context and also issue the START channel
736 * command to both channels. Channels can be started only if both host and
737 * device execution environments match and channels are in a DISABLED state.
189ff97c 738 */
9ebc2758 739int mhi_prepare_for_transfer(struct mhi_device *mhi_dev);
189ff97c 740
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741/**
742 * mhi_prepare_for_transfer_autoqueue - Setup UL and DL channels with auto queue
743 * buffers for DL traffic
744 * @mhi_dev: Device associated with the channels
745 *
746 * Allocate and initialize the channel context and also issue the START channel
747 * command to both channels. Channels can be started only if both host and
748 * device execution environments match and channels are in a DISABLED state.
749 * The MHI core will automatically allocate and queue buffers for the DL traffic.
750 */
751int mhi_prepare_for_transfer_autoqueue(struct mhi_device *mhi_dev);
752
189ff97c 753/**
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754 * mhi_unprepare_from_transfer - Reset UL and DL channels for data transfer.
755 * Issue the RESET channel command and let the
756 * device clean-up the context so no incoming
757 * transfers are seen on the host. Free memory
758 * associated with the context on host. If device
759 * is unresponsive, only perform a host side
760 * clean-up. Channels can be reset only if both
761 * host and device execution environments match
762 * and channels are in an ENABLED, STOPPED or
763 * SUSPENDED state.
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764 * @mhi_dev: Device associated with the channels
765 */
766void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev);
767
768/**
769 * mhi_poll - Poll for any available data in DL direction
770 * @mhi_dev: Device associated with the channels
771 * @budget: # of events to process
772 */
773int mhi_poll(struct mhi_device *mhi_dev, u32 budget);
774
775/**
776 * mhi_queue_dma - Send or receive DMA mapped buffers from client device
777 * over MHI channel
778 * @mhi_dev: Device associated with the channels
779 * @dir: DMA direction for the channel
780 * @mhi_buf: Buffer for holding the DMA mapped data
781 * @len: Buffer length
782 * @mflags: MHI transfer flags used for the transfer
783 */
784int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir,
785 struct mhi_buf *mhi_buf, size_t len, enum mhi_flags mflags);
786
787/**
788 * mhi_queue_buf - Send or receive raw buffers from client device over MHI
789 * channel
790 * @mhi_dev: Device associated with the channels
791 * @dir: DMA direction for the channel
792 * @buf: Buffer for holding the data
793 * @len: Buffer length
794 * @mflags: MHI transfer flags used for the transfer
795 */
796int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir,
797 void *buf, size_t len, enum mhi_flags mflags);
798
799/**
800 * mhi_queue_skb - Send or receive SKBs from client device over MHI channel
801 * @mhi_dev: Device associated with the channels
802 * @dir: DMA direction for the channel
803 * @skb: Buffer for holding SKBs
804 * @len: Buffer length
805 * @mflags: MHI transfer flags used for the transfer
806 */
807int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir,
808 struct sk_buff *skb, size_t len, enum mhi_flags mflags);
809
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810/**
811 * mhi_queue_is_full - Determine whether queueing new elements is possible
812 * @mhi_dev: Device associated with the channels
813 * @dir: DMA direction for the channel
814 */
815bool mhi_queue_is_full(struct mhi_device *mhi_dev, enum dma_data_direction dir);
816
0cbf2608 817#endif /* _MHI_H_ */