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1 | /* |
2 | * linux/mfd/wm831x/regulator.h -- Regulator definitons for wm831x | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics PLC. | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #ifndef __MFD_WM831X_REGULATOR_H__ | |
16 | #define __MFD_WM831X_REGULATOR_H__ | |
17 | ||
e4ee831f MB |
18 | /* |
19 | * R16462 (0x404E) - Current Sink 1 | |
20 | */ | |
21 | #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */ | |
22 | #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */ | |
23 | #define WM831X_CS1_ENA_SHIFT 15 /* CS1_ENA */ | |
24 | #define WM831X_CS1_ENA_WIDTH 1 /* CS1_ENA */ | |
25 | #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */ | |
26 | #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */ | |
27 | #define WM831X_CS1_DRIVE_SHIFT 14 /* CS1_DRIVE */ | |
28 | #define WM831X_CS1_DRIVE_WIDTH 1 /* CS1_DRIVE */ | |
29 | #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */ | |
30 | #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */ | |
31 | #define WM831X_CS1_SLPENA_SHIFT 12 /* CS1_SLPENA */ | |
32 | #define WM831X_CS1_SLPENA_WIDTH 1 /* CS1_SLPENA */ | |
33 | #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */ | |
34 | #define WM831X_CS1_OFF_RAMP_SHIFT 10 /* CS1_OFF_RAMP - [11:10] */ | |
35 | #define WM831X_CS1_OFF_RAMP_WIDTH 2 /* CS1_OFF_RAMP - [11:10] */ | |
36 | #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */ | |
37 | #define WM831X_CS1_ON_RAMP_SHIFT 8 /* CS1_ON_RAMP - [9:8] */ | |
38 | #define WM831X_CS1_ON_RAMP_WIDTH 2 /* CS1_ON_RAMP - [9:8] */ | |
39 | #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */ | |
40 | #define WM831X_CS1_ISEL_SHIFT 0 /* CS1_ISEL - [5:0] */ | |
41 | #define WM831X_CS1_ISEL_WIDTH 6 /* CS1_ISEL - [5:0] */ | |
42 | ||
43 | /* | |
44 | * R16463 (0x404F) - Current Sink 2 | |
45 | */ | |
46 | #define WM831X_CS2_ENA 0x8000 /* CS2_ENA */ | |
47 | #define WM831X_CS2_ENA_MASK 0x8000 /* CS2_ENA */ | |
48 | #define WM831X_CS2_ENA_SHIFT 15 /* CS2_ENA */ | |
49 | #define WM831X_CS2_ENA_WIDTH 1 /* CS2_ENA */ | |
50 | #define WM831X_CS2_DRIVE 0x4000 /* CS2_DRIVE */ | |
51 | #define WM831X_CS2_DRIVE_MASK 0x4000 /* CS2_DRIVE */ | |
52 | #define WM831X_CS2_DRIVE_SHIFT 14 /* CS2_DRIVE */ | |
53 | #define WM831X_CS2_DRIVE_WIDTH 1 /* CS2_DRIVE */ | |
54 | #define WM831X_CS2_SLPENA 0x1000 /* CS2_SLPENA */ | |
55 | #define WM831X_CS2_SLPENA_MASK 0x1000 /* CS2_SLPENA */ | |
56 | #define WM831X_CS2_SLPENA_SHIFT 12 /* CS2_SLPENA */ | |
57 | #define WM831X_CS2_SLPENA_WIDTH 1 /* CS2_SLPENA */ | |
58 | #define WM831X_CS2_OFF_RAMP_MASK 0x0C00 /* CS2_OFF_RAMP - [11:10] */ | |
59 | #define WM831X_CS2_OFF_RAMP_SHIFT 10 /* CS2_OFF_RAMP - [11:10] */ | |
60 | #define WM831X_CS2_OFF_RAMP_WIDTH 2 /* CS2_OFF_RAMP - [11:10] */ | |
61 | #define WM831X_CS2_ON_RAMP_MASK 0x0300 /* CS2_ON_RAMP - [9:8] */ | |
62 | #define WM831X_CS2_ON_RAMP_SHIFT 8 /* CS2_ON_RAMP - [9:8] */ | |
63 | #define WM831X_CS2_ON_RAMP_WIDTH 2 /* CS2_ON_RAMP - [9:8] */ | |
64 | #define WM831X_CS2_ISEL_MASK 0x003F /* CS2_ISEL - [5:0] */ | |
65 | #define WM831X_CS2_ISEL_SHIFT 0 /* CS2_ISEL - [5:0] */ | |
66 | #define WM831X_CS2_ISEL_WIDTH 6 /* CS2_ISEL - [5:0] */ | |
67 | ||
68 | /* | |
69 | * R16464 (0x4050) - DCDC Enable | |
70 | */ | |
71 | #define WM831X_EPE2_ENA 0x0080 /* EPE2_ENA */ | |
72 | #define WM831X_EPE2_ENA_MASK 0x0080 /* EPE2_ENA */ | |
73 | #define WM831X_EPE2_ENA_SHIFT 7 /* EPE2_ENA */ | |
74 | #define WM831X_EPE2_ENA_WIDTH 1 /* EPE2_ENA */ | |
75 | #define WM831X_EPE1_ENA 0x0040 /* EPE1_ENA */ | |
76 | #define WM831X_EPE1_ENA_MASK 0x0040 /* EPE1_ENA */ | |
77 | #define WM831X_EPE1_ENA_SHIFT 6 /* EPE1_ENA */ | |
78 | #define WM831X_EPE1_ENA_WIDTH 1 /* EPE1_ENA */ | |
79 | #define WM831X_DC4_ENA 0x0008 /* DC4_ENA */ | |
80 | #define WM831X_DC4_ENA_MASK 0x0008 /* DC4_ENA */ | |
81 | #define WM831X_DC4_ENA_SHIFT 3 /* DC4_ENA */ | |
82 | #define WM831X_DC4_ENA_WIDTH 1 /* DC4_ENA */ | |
83 | #define WM831X_DC3_ENA 0x0004 /* DC3_ENA */ | |
84 | #define WM831X_DC3_ENA_MASK 0x0004 /* DC3_ENA */ | |
85 | #define WM831X_DC3_ENA_SHIFT 2 /* DC3_ENA */ | |
86 | #define WM831X_DC3_ENA_WIDTH 1 /* DC3_ENA */ | |
87 | #define WM831X_DC2_ENA 0x0002 /* DC2_ENA */ | |
88 | #define WM831X_DC2_ENA_MASK 0x0002 /* DC2_ENA */ | |
89 | #define WM831X_DC2_ENA_SHIFT 1 /* DC2_ENA */ | |
90 | #define WM831X_DC2_ENA_WIDTH 1 /* DC2_ENA */ | |
91 | #define WM831X_DC1_ENA 0x0001 /* DC1_ENA */ | |
92 | #define WM831X_DC1_ENA_MASK 0x0001 /* DC1_ENA */ | |
93 | #define WM831X_DC1_ENA_SHIFT 0 /* DC1_ENA */ | |
94 | #define WM831X_DC1_ENA_WIDTH 1 /* DC1_ENA */ | |
95 | ||
96 | /* | |
97 | * R16465 (0x4051) - LDO Enable | |
98 | */ | |
99 | #define WM831X_LDO11_ENA 0x0400 /* LDO11_ENA */ | |
100 | #define WM831X_LDO11_ENA_MASK 0x0400 /* LDO11_ENA */ | |
101 | #define WM831X_LDO11_ENA_SHIFT 10 /* LDO11_ENA */ | |
102 | #define WM831X_LDO11_ENA_WIDTH 1 /* LDO11_ENA */ | |
103 | #define WM831X_LDO10_ENA 0x0200 /* LDO10_ENA */ | |
104 | #define WM831X_LDO10_ENA_MASK 0x0200 /* LDO10_ENA */ | |
105 | #define WM831X_LDO10_ENA_SHIFT 9 /* LDO10_ENA */ | |
106 | #define WM831X_LDO10_ENA_WIDTH 1 /* LDO10_ENA */ | |
107 | #define WM831X_LDO9_ENA 0x0100 /* LDO9_ENA */ | |
108 | #define WM831X_LDO9_ENA_MASK 0x0100 /* LDO9_ENA */ | |
109 | #define WM831X_LDO9_ENA_SHIFT 8 /* LDO9_ENA */ | |
110 | #define WM831X_LDO9_ENA_WIDTH 1 /* LDO9_ENA */ | |
111 | #define WM831X_LDO8_ENA 0x0080 /* LDO8_ENA */ | |
112 | #define WM831X_LDO8_ENA_MASK 0x0080 /* LDO8_ENA */ | |
113 | #define WM831X_LDO8_ENA_SHIFT 7 /* LDO8_ENA */ | |
114 | #define WM831X_LDO8_ENA_WIDTH 1 /* LDO8_ENA */ | |
115 | #define WM831X_LDO7_ENA 0x0040 /* LDO7_ENA */ | |
116 | #define WM831X_LDO7_ENA_MASK 0x0040 /* LDO7_ENA */ | |
117 | #define WM831X_LDO7_ENA_SHIFT 6 /* LDO7_ENA */ | |
118 | #define WM831X_LDO7_ENA_WIDTH 1 /* LDO7_ENA */ | |
119 | #define WM831X_LDO6_ENA 0x0020 /* LDO6_ENA */ | |
120 | #define WM831X_LDO6_ENA_MASK 0x0020 /* LDO6_ENA */ | |
121 | #define WM831X_LDO6_ENA_SHIFT 5 /* LDO6_ENA */ | |
122 | #define WM831X_LDO6_ENA_WIDTH 1 /* LDO6_ENA */ | |
123 | #define WM831X_LDO5_ENA 0x0010 /* LDO5_ENA */ | |
124 | #define WM831X_LDO5_ENA_MASK 0x0010 /* LDO5_ENA */ | |
125 | #define WM831X_LDO5_ENA_SHIFT 4 /* LDO5_ENA */ | |
126 | #define WM831X_LDO5_ENA_WIDTH 1 /* LDO5_ENA */ | |
127 | #define WM831X_LDO4_ENA 0x0008 /* LDO4_ENA */ | |
128 | #define WM831X_LDO4_ENA_MASK 0x0008 /* LDO4_ENA */ | |
129 | #define WM831X_LDO4_ENA_SHIFT 3 /* LDO4_ENA */ | |
130 | #define WM831X_LDO4_ENA_WIDTH 1 /* LDO4_ENA */ | |
131 | #define WM831X_LDO3_ENA 0x0004 /* LDO3_ENA */ | |
132 | #define WM831X_LDO3_ENA_MASK 0x0004 /* LDO3_ENA */ | |
133 | #define WM831X_LDO3_ENA_SHIFT 2 /* LDO3_ENA */ | |
134 | #define WM831X_LDO3_ENA_WIDTH 1 /* LDO3_ENA */ | |
135 | #define WM831X_LDO2_ENA 0x0002 /* LDO2_ENA */ | |
136 | #define WM831X_LDO2_ENA_MASK 0x0002 /* LDO2_ENA */ | |
137 | #define WM831X_LDO2_ENA_SHIFT 1 /* LDO2_ENA */ | |
138 | #define WM831X_LDO2_ENA_WIDTH 1 /* LDO2_ENA */ | |
139 | #define WM831X_LDO1_ENA 0x0001 /* LDO1_ENA */ | |
140 | #define WM831X_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */ | |
141 | #define WM831X_LDO1_ENA_SHIFT 0 /* LDO1_ENA */ | |
142 | #define WM831X_LDO1_ENA_WIDTH 1 /* LDO1_ENA */ | |
143 | ||
144 | /* | |
145 | * R16466 (0x4052) - DCDC Status | |
146 | */ | |
147 | #define WM831X_EPE2_STS 0x0080 /* EPE2_STS */ | |
148 | #define WM831X_EPE2_STS_MASK 0x0080 /* EPE2_STS */ | |
149 | #define WM831X_EPE2_STS_SHIFT 7 /* EPE2_STS */ | |
150 | #define WM831X_EPE2_STS_WIDTH 1 /* EPE2_STS */ | |
151 | #define WM831X_EPE1_STS 0x0040 /* EPE1_STS */ | |
152 | #define WM831X_EPE1_STS_MASK 0x0040 /* EPE1_STS */ | |
153 | #define WM831X_EPE1_STS_SHIFT 6 /* EPE1_STS */ | |
154 | #define WM831X_EPE1_STS_WIDTH 1 /* EPE1_STS */ | |
155 | #define WM831X_DC4_STS 0x0008 /* DC4_STS */ | |
156 | #define WM831X_DC4_STS_MASK 0x0008 /* DC4_STS */ | |
157 | #define WM831X_DC4_STS_SHIFT 3 /* DC4_STS */ | |
158 | #define WM831X_DC4_STS_WIDTH 1 /* DC4_STS */ | |
159 | #define WM831X_DC3_STS 0x0004 /* DC3_STS */ | |
160 | #define WM831X_DC3_STS_MASK 0x0004 /* DC3_STS */ | |
161 | #define WM831X_DC3_STS_SHIFT 2 /* DC3_STS */ | |
162 | #define WM831X_DC3_STS_WIDTH 1 /* DC3_STS */ | |
163 | #define WM831X_DC2_STS 0x0002 /* DC2_STS */ | |
164 | #define WM831X_DC2_STS_MASK 0x0002 /* DC2_STS */ | |
165 | #define WM831X_DC2_STS_SHIFT 1 /* DC2_STS */ | |
166 | #define WM831X_DC2_STS_WIDTH 1 /* DC2_STS */ | |
167 | #define WM831X_DC1_STS 0x0001 /* DC1_STS */ | |
168 | #define WM831X_DC1_STS_MASK 0x0001 /* DC1_STS */ | |
169 | #define WM831X_DC1_STS_SHIFT 0 /* DC1_STS */ | |
170 | #define WM831X_DC1_STS_WIDTH 1 /* DC1_STS */ | |
171 | ||
172 | /* | |
173 | * R16467 (0x4053) - LDO Status | |
174 | */ | |
175 | #define WM831X_LDO11_STS 0x0400 /* LDO11_STS */ | |
176 | #define WM831X_LDO11_STS_MASK 0x0400 /* LDO11_STS */ | |
177 | #define WM831X_LDO11_STS_SHIFT 10 /* LDO11_STS */ | |
178 | #define WM831X_LDO11_STS_WIDTH 1 /* LDO11_STS */ | |
179 | #define WM831X_LDO10_STS 0x0200 /* LDO10_STS */ | |
180 | #define WM831X_LDO10_STS_MASK 0x0200 /* LDO10_STS */ | |
181 | #define WM831X_LDO10_STS_SHIFT 9 /* LDO10_STS */ | |
182 | #define WM831X_LDO10_STS_WIDTH 1 /* LDO10_STS */ | |
183 | #define WM831X_LDO9_STS 0x0100 /* LDO9_STS */ | |
184 | #define WM831X_LDO9_STS_MASK 0x0100 /* LDO9_STS */ | |
185 | #define WM831X_LDO9_STS_SHIFT 8 /* LDO9_STS */ | |
186 | #define WM831X_LDO9_STS_WIDTH 1 /* LDO9_STS */ | |
187 | #define WM831X_LDO8_STS 0x0080 /* LDO8_STS */ | |
188 | #define WM831X_LDO8_STS_MASK 0x0080 /* LDO8_STS */ | |
189 | #define WM831X_LDO8_STS_SHIFT 7 /* LDO8_STS */ | |
190 | #define WM831X_LDO8_STS_WIDTH 1 /* LDO8_STS */ | |
191 | #define WM831X_LDO7_STS 0x0040 /* LDO7_STS */ | |
192 | #define WM831X_LDO7_STS_MASK 0x0040 /* LDO7_STS */ | |
193 | #define WM831X_LDO7_STS_SHIFT 6 /* LDO7_STS */ | |
194 | #define WM831X_LDO7_STS_WIDTH 1 /* LDO7_STS */ | |
195 | #define WM831X_LDO6_STS 0x0020 /* LDO6_STS */ | |
196 | #define WM831X_LDO6_STS_MASK 0x0020 /* LDO6_STS */ | |
197 | #define WM831X_LDO6_STS_SHIFT 5 /* LDO6_STS */ | |
198 | #define WM831X_LDO6_STS_WIDTH 1 /* LDO6_STS */ | |
199 | #define WM831X_LDO5_STS 0x0010 /* LDO5_STS */ | |
200 | #define WM831X_LDO5_STS_MASK 0x0010 /* LDO5_STS */ | |
201 | #define WM831X_LDO5_STS_SHIFT 4 /* LDO5_STS */ | |
202 | #define WM831X_LDO5_STS_WIDTH 1 /* LDO5_STS */ | |
203 | #define WM831X_LDO4_STS 0x0008 /* LDO4_STS */ | |
204 | #define WM831X_LDO4_STS_MASK 0x0008 /* LDO4_STS */ | |
205 | #define WM831X_LDO4_STS_SHIFT 3 /* LDO4_STS */ | |
206 | #define WM831X_LDO4_STS_WIDTH 1 /* LDO4_STS */ | |
207 | #define WM831X_LDO3_STS 0x0004 /* LDO3_STS */ | |
208 | #define WM831X_LDO3_STS_MASK 0x0004 /* LDO3_STS */ | |
209 | #define WM831X_LDO3_STS_SHIFT 2 /* LDO3_STS */ | |
210 | #define WM831X_LDO3_STS_WIDTH 1 /* LDO3_STS */ | |
211 | #define WM831X_LDO2_STS 0x0002 /* LDO2_STS */ | |
212 | #define WM831X_LDO2_STS_MASK 0x0002 /* LDO2_STS */ | |
213 | #define WM831X_LDO2_STS_SHIFT 1 /* LDO2_STS */ | |
214 | #define WM831X_LDO2_STS_WIDTH 1 /* LDO2_STS */ | |
215 | #define WM831X_LDO1_STS 0x0001 /* LDO1_STS */ | |
216 | #define WM831X_LDO1_STS_MASK 0x0001 /* LDO1_STS */ | |
217 | #define WM831X_LDO1_STS_SHIFT 0 /* LDO1_STS */ | |
218 | #define WM831X_LDO1_STS_WIDTH 1 /* LDO1_STS */ | |
219 | ||
220 | /* | |
221 | * R16468 (0x4054) - DCDC UV Status | |
222 | */ | |
223 | #define WM831X_DC2_OV_STS 0x2000 /* DC2_OV_STS */ | |
224 | #define WM831X_DC2_OV_STS_MASK 0x2000 /* DC2_OV_STS */ | |
225 | #define WM831X_DC2_OV_STS_SHIFT 13 /* DC2_OV_STS */ | |
226 | #define WM831X_DC2_OV_STS_WIDTH 1 /* DC2_OV_STS */ | |
227 | #define WM831X_DC1_OV_STS 0x1000 /* DC1_OV_STS */ | |
228 | #define WM831X_DC1_OV_STS_MASK 0x1000 /* DC1_OV_STS */ | |
229 | #define WM831X_DC1_OV_STS_SHIFT 12 /* DC1_OV_STS */ | |
230 | #define WM831X_DC1_OV_STS_WIDTH 1 /* DC1_OV_STS */ | |
231 | #define WM831X_DC2_HC_STS 0x0200 /* DC2_HC_STS */ | |
232 | #define WM831X_DC2_HC_STS_MASK 0x0200 /* DC2_HC_STS */ | |
233 | #define WM831X_DC2_HC_STS_SHIFT 9 /* DC2_HC_STS */ | |
234 | #define WM831X_DC2_HC_STS_WIDTH 1 /* DC2_HC_STS */ | |
235 | #define WM831X_DC1_HC_STS 0x0100 /* DC1_HC_STS */ | |
236 | #define WM831X_DC1_HC_STS_MASK 0x0100 /* DC1_HC_STS */ | |
237 | #define WM831X_DC1_HC_STS_SHIFT 8 /* DC1_HC_STS */ | |
238 | #define WM831X_DC1_HC_STS_WIDTH 1 /* DC1_HC_STS */ | |
239 | #define WM831X_DC4_UV_STS 0x0008 /* DC4_UV_STS */ | |
240 | #define WM831X_DC4_UV_STS_MASK 0x0008 /* DC4_UV_STS */ | |
241 | #define WM831X_DC4_UV_STS_SHIFT 3 /* DC4_UV_STS */ | |
242 | #define WM831X_DC4_UV_STS_WIDTH 1 /* DC4_UV_STS */ | |
243 | #define WM831X_DC3_UV_STS 0x0004 /* DC3_UV_STS */ | |
244 | #define WM831X_DC3_UV_STS_MASK 0x0004 /* DC3_UV_STS */ | |
245 | #define WM831X_DC3_UV_STS_SHIFT 2 /* DC3_UV_STS */ | |
246 | #define WM831X_DC3_UV_STS_WIDTH 1 /* DC3_UV_STS */ | |
247 | #define WM831X_DC2_UV_STS 0x0002 /* DC2_UV_STS */ | |
248 | #define WM831X_DC2_UV_STS_MASK 0x0002 /* DC2_UV_STS */ | |
249 | #define WM831X_DC2_UV_STS_SHIFT 1 /* DC2_UV_STS */ | |
250 | #define WM831X_DC2_UV_STS_WIDTH 1 /* DC2_UV_STS */ | |
251 | #define WM831X_DC1_UV_STS 0x0001 /* DC1_UV_STS */ | |
252 | #define WM831X_DC1_UV_STS_MASK 0x0001 /* DC1_UV_STS */ | |
253 | #define WM831X_DC1_UV_STS_SHIFT 0 /* DC1_UV_STS */ | |
254 | #define WM831X_DC1_UV_STS_WIDTH 1 /* DC1_UV_STS */ | |
255 | ||
256 | /* | |
257 | * R16469 (0x4055) - LDO UV Status | |
258 | */ | |
259 | #define WM831X_INTLDO_UV_STS 0x8000 /* INTLDO_UV_STS */ | |
260 | #define WM831X_INTLDO_UV_STS_MASK 0x8000 /* INTLDO_UV_STS */ | |
261 | #define WM831X_INTLDO_UV_STS_SHIFT 15 /* INTLDO_UV_STS */ | |
262 | #define WM831X_INTLDO_UV_STS_WIDTH 1 /* INTLDO_UV_STS */ | |
263 | #define WM831X_LDO10_UV_STS 0x0200 /* LDO10_UV_STS */ | |
264 | #define WM831X_LDO10_UV_STS_MASK 0x0200 /* LDO10_UV_STS */ | |
265 | #define WM831X_LDO10_UV_STS_SHIFT 9 /* LDO10_UV_STS */ | |
266 | #define WM831X_LDO10_UV_STS_WIDTH 1 /* LDO10_UV_STS */ | |
267 | #define WM831X_LDO9_UV_STS 0x0100 /* LDO9_UV_STS */ | |
268 | #define WM831X_LDO9_UV_STS_MASK 0x0100 /* LDO9_UV_STS */ | |
269 | #define WM831X_LDO9_UV_STS_SHIFT 8 /* LDO9_UV_STS */ | |
270 | #define WM831X_LDO9_UV_STS_WIDTH 1 /* LDO9_UV_STS */ | |
271 | #define WM831X_LDO8_UV_STS 0x0080 /* LDO8_UV_STS */ | |
272 | #define WM831X_LDO8_UV_STS_MASK 0x0080 /* LDO8_UV_STS */ | |
273 | #define WM831X_LDO8_UV_STS_SHIFT 7 /* LDO8_UV_STS */ | |
274 | #define WM831X_LDO8_UV_STS_WIDTH 1 /* LDO8_UV_STS */ | |
275 | #define WM831X_LDO7_UV_STS 0x0040 /* LDO7_UV_STS */ | |
276 | #define WM831X_LDO7_UV_STS_MASK 0x0040 /* LDO7_UV_STS */ | |
277 | #define WM831X_LDO7_UV_STS_SHIFT 6 /* LDO7_UV_STS */ | |
278 | #define WM831X_LDO7_UV_STS_WIDTH 1 /* LDO7_UV_STS */ | |
279 | #define WM831X_LDO6_UV_STS 0x0020 /* LDO6_UV_STS */ | |
280 | #define WM831X_LDO6_UV_STS_MASK 0x0020 /* LDO6_UV_STS */ | |
281 | #define WM831X_LDO6_UV_STS_SHIFT 5 /* LDO6_UV_STS */ | |
282 | #define WM831X_LDO6_UV_STS_WIDTH 1 /* LDO6_UV_STS */ | |
283 | #define WM831X_LDO5_UV_STS 0x0010 /* LDO5_UV_STS */ | |
284 | #define WM831X_LDO5_UV_STS_MASK 0x0010 /* LDO5_UV_STS */ | |
285 | #define WM831X_LDO5_UV_STS_SHIFT 4 /* LDO5_UV_STS */ | |
286 | #define WM831X_LDO5_UV_STS_WIDTH 1 /* LDO5_UV_STS */ | |
287 | #define WM831X_LDO4_UV_STS 0x0008 /* LDO4_UV_STS */ | |
288 | #define WM831X_LDO4_UV_STS_MASK 0x0008 /* LDO4_UV_STS */ | |
289 | #define WM831X_LDO4_UV_STS_SHIFT 3 /* LDO4_UV_STS */ | |
290 | #define WM831X_LDO4_UV_STS_WIDTH 1 /* LDO4_UV_STS */ | |
291 | #define WM831X_LDO3_UV_STS 0x0004 /* LDO3_UV_STS */ | |
292 | #define WM831X_LDO3_UV_STS_MASK 0x0004 /* LDO3_UV_STS */ | |
293 | #define WM831X_LDO3_UV_STS_SHIFT 2 /* LDO3_UV_STS */ | |
294 | #define WM831X_LDO3_UV_STS_WIDTH 1 /* LDO3_UV_STS */ | |
295 | #define WM831X_LDO2_UV_STS 0x0002 /* LDO2_UV_STS */ | |
296 | #define WM831X_LDO2_UV_STS_MASK 0x0002 /* LDO2_UV_STS */ | |
297 | #define WM831X_LDO2_UV_STS_SHIFT 1 /* LDO2_UV_STS */ | |
298 | #define WM831X_LDO2_UV_STS_WIDTH 1 /* LDO2_UV_STS */ | |
299 | #define WM831X_LDO1_UV_STS 0x0001 /* LDO1_UV_STS */ | |
300 | #define WM831X_LDO1_UV_STS_MASK 0x0001 /* LDO1_UV_STS */ | |
301 | #define WM831X_LDO1_UV_STS_SHIFT 0 /* LDO1_UV_STS */ | |
302 | #define WM831X_LDO1_UV_STS_WIDTH 1 /* LDO1_UV_STS */ | |
303 | ||
304 | /* | |
305 | * R16470 (0x4056) - DC1 Control 1 | |
306 | */ | |
307 | #define WM831X_DC1_RATE_MASK 0xC000 /* DC1_RATE - [15:14] */ | |
308 | #define WM831X_DC1_RATE_SHIFT 14 /* DC1_RATE - [15:14] */ | |
309 | #define WM831X_DC1_RATE_WIDTH 2 /* DC1_RATE - [15:14] */ | |
310 | #define WM831X_DC1_PHASE 0x1000 /* DC1_PHASE */ | |
311 | #define WM831X_DC1_PHASE_MASK 0x1000 /* DC1_PHASE */ | |
312 | #define WM831X_DC1_PHASE_SHIFT 12 /* DC1_PHASE */ | |
313 | #define WM831X_DC1_PHASE_WIDTH 1 /* DC1_PHASE */ | |
314 | #define WM831X_DC1_FREQ_MASK 0x0300 /* DC1_FREQ - [9:8] */ | |
315 | #define WM831X_DC1_FREQ_SHIFT 8 /* DC1_FREQ - [9:8] */ | |
316 | #define WM831X_DC1_FREQ_WIDTH 2 /* DC1_FREQ - [9:8] */ | |
317 | #define WM831X_DC1_FLT 0x0080 /* DC1_FLT */ | |
318 | #define WM831X_DC1_FLT_MASK 0x0080 /* DC1_FLT */ | |
319 | #define WM831X_DC1_FLT_SHIFT 7 /* DC1_FLT */ | |
320 | #define WM831X_DC1_FLT_WIDTH 1 /* DC1_FLT */ | |
321 | #define WM831X_DC1_SOFT_START_MASK 0x0030 /* DC1_SOFT_START - [5:4] */ | |
322 | #define WM831X_DC1_SOFT_START_SHIFT 4 /* DC1_SOFT_START - [5:4] */ | |
323 | #define WM831X_DC1_SOFT_START_WIDTH 2 /* DC1_SOFT_START - [5:4] */ | |
324 | #define WM831X_DC1_CAP_MASK 0x0003 /* DC1_CAP - [1:0] */ | |
325 | #define WM831X_DC1_CAP_SHIFT 0 /* DC1_CAP - [1:0] */ | |
326 | #define WM831X_DC1_CAP_WIDTH 2 /* DC1_CAP - [1:0] */ | |
327 | ||
328 | /* | |
329 | * R16471 (0x4057) - DC1 Control 2 | |
330 | */ | |
331 | #define WM831X_DC1_ERR_ACT_MASK 0xC000 /* DC1_ERR_ACT - [15:14] */ | |
332 | #define WM831X_DC1_ERR_ACT_SHIFT 14 /* DC1_ERR_ACT - [15:14] */ | |
333 | #define WM831X_DC1_ERR_ACT_WIDTH 2 /* DC1_ERR_ACT - [15:14] */ | |
334 | #define WM831X_DC1_HWC_SRC_MASK 0x1800 /* DC1_HWC_SRC - [12:11] */ | |
335 | #define WM831X_DC1_HWC_SRC_SHIFT 11 /* DC1_HWC_SRC - [12:11] */ | |
336 | #define WM831X_DC1_HWC_SRC_WIDTH 2 /* DC1_HWC_SRC - [12:11] */ | |
337 | #define WM831X_DC1_HWC_VSEL 0x0400 /* DC1_HWC_VSEL */ | |
338 | #define WM831X_DC1_HWC_VSEL_MASK 0x0400 /* DC1_HWC_VSEL */ | |
339 | #define WM831X_DC1_HWC_VSEL_SHIFT 10 /* DC1_HWC_VSEL */ | |
340 | #define WM831X_DC1_HWC_VSEL_WIDTH 1 /* DC1_HWC_VSEL */ | |
341 | #define WM831X_DC1_HWC_MODE_MASK 0x0300 /* DC1_HWC_MODE - [9:8] */ | |
342 | #define WM831X_DC1_HWC_MODE_SHIFT 8 /* DC1_HWC_MODE - [9:8] */ | |
343 | #define WM831X_DC1_HWC_MODE_WIDTH 2 /* DC1_HWC_MODE - [9:8] */ | |
344 | #define WM831X_DC1_HC_THR_MASK 0x0070 /* DC1_HC_THR - [6:4] */ | |
345 | #define WM831X_DC1_HC_THR_SHIFT 4 /* DC1_HC_THR - [6:4] */ | |
346 | #define WM831X_DC1_HC_THR_WIDTH 3 /* DC1_HC_THR - [6:4] */ | |
347 | #define WM831X_DC1_HC_IND_ENA 0x0001 /* DC1_HC_IND_ENA */ | |
348 | #define WM831X_DC1_HC_IND_ENA_MASK 0x0001 /* DC1_HC_IND_ENA */ | |
349 | #define WM831X_DC1_HC_IND_ENA_SHIFT 0 /* DC1_HC_IND_ENA */ | |
350 | #define WM831X_DC1_HC_IND_ENA_WIDTH 1 /* DC1_HC_IND_ENA */ | |
351 | ||
352 | /* | |
353 | * R16472 (0x4058) - DC1 ON Config | |
354 | */ | |
355 | #define WM831X_DC1_ON_SLOT_MASK 0xE000 /* DC1_ON_SLOT - [15:13] */ | |
356 | #define WM831X_DC1_ON_SLOT_SHIFT 13 /* DC1_ON_SLOT - [15:13] */ | |
357 | #define WM831X_DC1_ON_SLOT_WIDTH 3 /* DC1_ON_SLOT - [15:13] */ | |
358 | #define WM831X_DC1_ON_MODE_MASK 0x0300 /* DC1_ON_MODE - [9:8] */ | |
359 | #define WM831X_DC1_ON_MODE_SHIFT 8 /* DC1_ON_MODE - [9:8] */ | |
360 | #define WM831X_DC1_ON_MODE_WIDTH 2 /* DC1_ON_MODE - [9:8] */ | |
361 | #define WM831X_DC1_ON_VSEL_MASK 0x007F /* DC1_ON_VSEL - [6:0] */ | |
362 | #define WM831X_DC1_ON_VSEL_SHIFT 0 /* DC1_ON_VSEL - [6:0] */ | |
363 | #define WM831X_DC1_ON_VSEL_WIDTH 7 /* DC1_ON_VSEL - [6:0] */ | |
364 | ||
365 | /* | |
366 | * R16473 (0x4059) - DC1 SLEEP Control | |
367 | */ | |
368 | #define WM831X_DC1_SLP_SLOT_MASK 0xE000 /* DC1_SLP_SLOT - [15:13] */ | |
369 | #define WM831X_DC1_SLP_SLOT_SHIFT 13 /* DC1_SLP_SLOT - [15:13] */ | |
370 | #define WM831X_DC1_SLP_SLOT_WIDTH 3 /* DC1_SLP_SLOT - [15:13] */ | |
371 | #define WM831X_DC1_SLP_MODE_MASK 0x0300 /* DC1_SLP_MODE - [9:8] */ | |
372 | #define WM831X_DC1_SLP_MODE_SHIFT 8 /* DC1_SLP_MODE - [9:8] */ | |
373 | #define WM831X_DC1_SLP_MODE_WIDTH 2 /* DC1_SLP_MODE - [9:8] */ | |
374 | #define WM831X_DC1_SLP_VSEL_MASK 0x007F /* DC1_SLP_VSEL - [6:0] */ | |
375 | #define WM831X_DC1_SLP_VSEL_SHIFT 0 /* DC1_SLP_VSEL - [6:0] */ | |
376 | #define WM831X_DC1_SLP_VSEL_WIDTH 7 /* DC1_SLP_VSEL - [6:0] */ | |
377 | ||
378 | /* | |
379 | * R16474 (0x405A) - DC1 DVS Control | |
380 | */ | |
381 | #define WM831X_DC1_DVS_SRC_MASK 0x1800 /* DC1_DVS_SRC - [12:11] */ | |
382 | #define WM831X_DC1_DVS_SRC_SHIFT 11 /* DC1_DVS_SRC - [12:11] */ | |
383 | #define WM831X_DC1_DVS_SRC_WIDTH 2 /* DC1_DVS_SRC - [12:11] */ | |
384 | #define WM831X_DC1_DVS_VSEL_MASK 0x007F /* DC1_DVS_VSEL - [6:0] */ | |
385 | #define WM831X_DC1_DVS_VSEL_SHIFT 0 /* DC1_DVS_VSEL - [6:0] */ | |
386 | #define WM831X_DC1_DVS_VSEL_WIDTH 7 /* DC1_DVS_VSEL - [6:0] */ | |
387 | ||
388 | /* | |
389 | * R16475 (0x405B) - DC2 Control 1 | |
390 | */ | |
391 | #define WM831X_DC2_RATE_MASK 0xC000 /* DC2_RATE - [15:14] */ | |
392 | #define WM831X_DC2_RATE_SHIFT 14 /* DC2_RATE - [15:14] */ | |
393 | #define WM831X_DC2_RATE_WIDTH 2 /* DC2_RATE - [15:14] */ | |
394 | #define WM831X_DC2_PHASE 0x1000 /* DC2_PHASE */ | |
395 | #define WM831X_DC2_PHASE_MASK 0x1000 /* DC2_PHASE */ | |
396 | #define WM831X_DC2_PHASE_SHIFT 12 /* DC2_PHASE */ | |
397 | #define WM831X_DC2_PHASE_WIDTH 1 /* DC2_PHASE */ | |
398 | #define WM831X_DC2_FREQ_MASK 0x0300 /* DC2_FREQ - [9:8] */ | |
399 | #define WM831X_DC2_FREQ_SHIFT 8 /* DC2_FREQ - [9:8] */ | |
400 | #define WM831X_DC2_FREQ_WIDTH 2 /* DC2_FREQ - [9:8] */ | |
401 | #define WM831X_DC2_FLT 0x0080 /* DC2_FLT */ | |
402 | #define WM831X_DC2_FLT_MASK 0x0080 /* DC2_FLT */ | |
403 | #define WM831X_DC2_FLT_SHIFT 7 /* DC2_FLT */ | |
404 | #define WM831X_DC2_FLT_WIDTH 1 /* DC2_FLT */ | |
405 | #define WM831X_DC2_SOFT_START_MASK 0x0030 /* DC2_SOFT_START - [5:4] */ | |
406 | #define WM831X_DC2_SOFT_START_SHIFT 4 /* DC2_SOFT_START - [5:4] */ | |
407 | #define WM831X_DC2_SOFT_START_WIDTH 2 /* DC2_SOFT_START - [5:4] */ | |
408 | #define WM831X_DC2_CAP_MASK 0x0003 /* DC2_CAP - [1:0] */ | |
409 | #define WM831X_DC2_CAP_SHIFT 0 /* DC2_CAP - [1:0] */ | |
410 | #define WM831X_DC2_CAP_WIDTH 2 /* DC2_CAP - [1:0] */ | |
411 | ||
412 | /* | |
413 | * R16476 (0x405C) - DC2 Control 2 | |
414 | */ | |
415 | #define WM831X_DC2_ERR_ACT_MASK 0xC000 /* DC2_ERR_ACT - [15:14] */ | |
416 | #define WM831X_DC2_ERR_ACT_SHIFT 14 /* DC2_ERR_ACT - [15:14] */ | |
417 | #define WM831X_DC2_ERR_ACT_WIDTH 2 /* DC2_ERR_ACT - [15:14] */ | |
418 | #define WM831X_DC2_HWC_SRC_MASK 0x1800 /* DC2_HWC_SRC - [12:11] */ | |
419 | #define WM831X_DC2_HWC_SRC_SHIFT 11 /* DC2_HWC_SRC - [12:11] */ | |
420 | #define WM831X_DC2_HWC_SRC_WIDTH 2 /* DC2_HWC_SRC - [12:11] */ | |
421 | #define WM831X_DC2_HWC_VSEL 0x0400 /* DC2_HWC_VSEL */ | |
422 | #define WM831X_DC2_HWC_VSEL_MASK 0x0400 /* DC2_HWC_VSEL */ | |
423 | #define WM831X_DC2_HWC_VSEL_SHIFT 10 /* DC2_HWC_VSEL */ | |
424 | #define WM831X_DC2_HWC_VSEL_WIDTH 1 /* DC2_HWC_VSEL */ | |
425 | #define WM831X_DC2_HWC_MODE_MASK 0x0300 /* DC2_HWC_MODE - [9:8] */ | |
426 | #define WM831X_DC2_HWC_MODE_SHIFT 8 /* DC2_HWC_MODE - [9:8] */ | |
427 | #define WM831X_DC2_HWC_MODE_WIDTH 2 /* DC2_HWC_MODE - [9:8] */ | |
428 | #define WM831X_DC2_HC_THR_MASK 0x0070 /* DC2_HC_THR - [6:4] */ | |
429 | #define WM831X_DC2_HC_THR_SHIFT 4 /* DC2_HC_THR - [6:4] */ | |
430 | #define WM831X_DC2_HC_THR_WIDTH 3 /* DC2_HC_THR - [6:4] */ | |
431 | #define WM831X_DC2_HC_IND_ENA 0x0001 /* DC2_HC_IND_ENA */ | |
432 | #define WM831X_DC2_HC_IND_ENA_MASK 0x0001 /* DC2_HC_IND_ENA */ | |
433 | #define WM831X_DC2_HC_IND_ENA_SHIFT 0 /* DC2_HC_IND_ENA */ | |
434 | #define WM831X_DC2_HC_IND_ENA_WIDTH 1 /* DC2_HC_IND_ENA */ | |
435 | ||
436 | /* | |
437 | * R16477 (0x405D) - DC2 ON Config | |
438 | */ | |
439 | #define WM831X_DC2_ON_SLOT_MASK 0xE000 /* DC2_ON_SLOT - [15:13] */ | |
440 | #define WM831X_DC2_ON_SLOT_SHIFT 13 /* DC2_ON_SLOT - [15:13] */ | |
441 | #define WM831X_DC2_ON_SLOT_WIDTH 3 /* DC2_ON_SLOT - [15:13] */ | |
442 | #define WM831X_DC2_ON_MODE_MASK 0x0300 /* DC2_ON_MODE - [9:8] */ | |
443 | #define WM831X_DC2_ON_MODE_SHIFT 8 /* DC2_ON_MODE - [9:8] */ | |
444 | #define WM831X_DC2_ON_MODE_WIDTH 2 /* DC2_ON_MODE - [9:8] */ | |
445 | #define WM831X_DC2_ON_VSEL_MASK 0x007F /* DC2_ON_VSEL - [6:0] */ | |
446 | #define WM831X_DC2_ON_VSEL_SHIFT 0 /* DC2_ON_VSEL - [6:0] */ | |
447 | #define WM831X_DC2_ON_VSEL_WIDTH 7 /* DC2_ON_VSEL - [6:0] */ | |
448 | ||
449 | /* | |
450 | * R16478 (0x405E) - DC2 SLEEP Control | |
451 | */ | |
452 | #define WM831X_DC2_SLP_SLOT_MASK 0xE000 /* DC2_SLP_SLOT - [15:13] */ | |
453 | #define WM831X_DC2_SLP_SLOT_SHIFT 13 /* DC2_SLP_SLOT - [15:13] */ | |
454 | #define WM831X_DC2_SLP_SLOT_WIDTH 3 /* DC2_SLP_SLOT - [15:13] */ | |
455 | #define WM831X_DC2_SLP_MODE_MASK 0x0300 /* DC2_SLP_MODE - [9:8] */ | |
456 | #define WM831X_DC2_SLP_MODE_SHIFT 8 /* DC2_SLP_MODE - [9:8] */ | |
457 | #define WM831X_DC2_SLP_MODE_WIDTH 2 /* DC2_SLP_MODE - [9:8] */ | |
458 | #define WM831X_DC2_SLP_VSEL_MASK 0x007F /* DC2_SLP_VSEL - [6:0] */ | |
459 | #define WM831X_DC2_SLP_VSEL_SHIFT 0 /* DC2_SLP_VSEL - [6:0] */ | |
460 | #define WM831X_DC2_SLP_VSEL_WIDTH 7 /* DC2_SLP_VSEL - [6:0] */ | |
461 | ||
462 | /* | |
463 | * R16479 (0x405F) - DC2 DVS Control | |
464 | */ | |
465 | #define WM831X_DC2_DVS_SRC_MASK 0x1800 /* DC2_DVS_SRC - [12:11] */ | |
466 | #define WM831X_DC2_DVS_SRC_SHIFT 11 /* DC2_DVS_SRC - [12:11] */ | |
467 | #define WM831X_DC2_DVS_SRC_WIDTH 2 /* DC2_DVS_SRC - [12:11] */ | |
468 | #define WM831X_DC2_DVS_VSEL_MASK 0x007F /* DC2_DVS_VSEL - [6:0] */ | |
469 | #define WM831X_DC2_DVS_VSEL_SHIFT 0 /* DC2_DVS_VSEL - [6:0] */ | |
470 | #define WM831X_DC2_DVS_VSEL_WIDTH 7 /* DC2_DVS_VSEL - [6:0] */ | |
471 | ||
472 | /* | |
473 | * R16480 (0x4060) - DC3 Control 1 | |
474 | */ | |
475 | #define WM831X_DC3_PHASE 0x1000 /* DC3_PHASE */ | |
476 | #define WM831X_DC3_PHASE_MASK 0x1000 /* DC3_PHASE */ | |
477 | #define WM831X_DC3_PHASE_SHIFT 12 /* DC3_PHASE */ | |
478 | #define WM831X_DC3_PHASE_WIDTH 1 /* DC3_PHASE */ | |
479 | #define WM831X_DC3_FLT 0x0080 /* DC3_FLT */ | |
480 | #define WM831X_DC3_FLT_MASK 0x0080 /* DC3_FLT */ | |
481 | #define WM831X_DC3_FLT_SHIFT 7 /* DC3_FLT */ | |
482 | #define WM831X_DC3_FLT_WIDTH 1 /* DC3_FLT */ | |
483 | #define WM831X_DC3_SOFT_START_MASK 0x0030 /* DC3_SOFT_START - [5:4] */ | |
484 | #define WM831X_DC3_SOFT_START_SHIFT 4 /* DC3_SOFT_START - [5:4] */ | |
485 | #define WM831X_DC3_SOFT_START_WIDTH 2 /* DC3_SOFT_START - [5:4] */ | |
486 | #define WM831X_DC3_STNBY_LIM_MASK 0x000C /* DC3_STNBY_LIM - [3:2] */ | |
487 | #define WM831X_DC3_STNBY_LIM_SHIFT 2 /* DC3_STNBY_LIM - [3:2] */ | |
488 | #define WM831X_DC3_STNBY_LIM_WIDTH 2 /* DC3_STNBY_LIM - [3:2] */ | |
489 | #define WM831X_DC3_CAP_MASK 0x0003 /* DC3_CAP - [1:0] */ | |
490 | #define WM831X_DC3_CAP_SHIFT 0 /* DC3_CAP - [1:0] */ | |
491 | #define WM831X_DC3_CAP_WIDTH 2 /* DC3_CAP - [1:0] */ | |
492 | ||
493 | /* | |
494 | * R16481 (0x4061) - DC3 Control 2 | |
495 | */ | |
496 | #define WM831X_DC3_ERR_ACT_MASK 0xC000 /* DC3_ERR_ACT - [15:14] */ | |
497 | #define WM831X_DC3_ERR_ACT_SHIFT 14 /* DC3_ERR_ACT - [15:14] */ | |
498 | #define WM831X_DC3_ERR_ACT_WIDTH 2 /* DC3_ERR_ACT - [15:14] */ | |
499 | #define WM831X_DC3_HWC_SRC_MASK 0x1800 /* DC3_HWC_SRC - [12:11] */ | |
500 | #define WM831X_DC3_HWC_SRC_SHIFT 11 /* DC3_HWC_SRC - [12:11] */ | |
501 | #define WM831X_DC3_HWC_SRC_WIDTH 2 /* DC3_HWC_SRC - [12:11] */ | |
502 | #define WM831X_DC3_HWC_VSEL 0x0400 /* DC3_HWC_VSEL */ | |
503 | #define WM831X_DC3_HWC_VSEL_MASK 0x0400 /* DC3_HWC_VSEL */ | |
504 | #define WM831X_DC3_HWC_VSEL_SHIFT 10 /* DC3_HWC_VSEL */ | |
505 | #define WM831X_DC3_HWC_VSEL_WIDTH 1 /* DC3_HWC_VSEL */ | |
506 | #define WM831X_DC3_HWC_MODE_MASK 0x0300 /* DC3_HWC_MODE - [9:8] */ | |
507 | #define WM831X_DC3_HWC_MODE_SHIFT 8 /* DC3_HWC_MODE - [9:8] */ | |
508 | #define WM831X_DC3_HWC_MODE_WIDTH 2 /* DC3_HWC_MODE - [9:8] */ | |
509 | #define WM831X_DC3_OVP 0x0080 /* DC3_OVP */ | |
510 | #define WM831X_DC3_OVP_MASK 0x0080 /* DC3_OVP */ | |
511 | #define WM831X_DC3_OVP_SHIFT 7 /* DC3_OVP */ | |
512 | #define WM831X_DC3_OVP_WIDTH 1 /* DC3_OVP */ | |
513 | ||
514 | /* | |
515 | * R16482 (0x4062) - DC3 ON Config | |
516 | */ | |
517 | #define WM831X_DC3_ON_SLOT_MASK 0xE000 /* DC3_ON_SLOT - [15:13] */ | |
518 | #define WM831X_DC3_ON_SLOT_SHIFT 13 /* DC3_ON_SLOT - [15:13] */ | |
519 | #define WM831X_DC3_ON_SLOT_WIDTH 3 /* DC3_ON_SLOT - [15:13] */ | |
520 | #define WM831X_DC3_ON_MODE_MASK 0x0300 /* DC3_ON_MODE - [9:8] */ | |
521 | #define WM831X_DC3_ON_MODE_SHIFT 8 /* DC3_ON_MODE - [9:8] */ | |
522 | #define WM831X_DC3_ON_MODE_WIDTH 2 /* DC3_ON_MODE - [9:8] */ | |
523 | #define WM831X_DC3_ON_VSEL_MASK 0x007F /* DC3_ON_VSEL - [6:0] */ | |
524 | #define WM831X_DC3_ON_VSEL_SHIFT 0 /* DC3_ON_VSEL - [6:0] */ | |
525 | #define WM831X_DC3_ON_VSEL_WIDTH 7 /* DC3_ON_VSEL - [6:0] */ | |
526 | ||
527 | /* | |
528 | * R16483 (0x4063) - DC3 SLEEP Control | |
529 | */ | |
530 | #define WM831X_DC3_SLP_SLOT_MASK 0xE000 /* DC3_SLP_SLOT - [15:13] */ | |
531 | #define WM831X_DC3_SLP_SLOT_SHIFT 13 /* DC3_SLP_SLOT - [15:13] */ | |
532 | #define WM831X_DC3_SLP_SLOT_WIDTH 3 /* DC3_SLP_SLOT - [15:13] */ | |
533 | #define WM831X_DC3_SLP_MODE_MASK 0x0300 /* DC3_SLP_MODE - [9:8] */ | |
534 | #define WM831X_DC3_SLP_MODE_SHIFT 8 /* DC3_SLP_MODE - [9:8] */ | |
535 | #define WM831X_DC3_SLP_MODE_WIDTH 2 /* DC3_SLP_MODE - [9:8] */ | |
536 | #define WM831X_DC3_SLP_VSEL_MASK 0x007F /* DC3_SLP_VSEL - [6:0] */ | |
537 | #define WM831X_DC3_SLP_VSEL_SHIFT 0 /* DC3_SLP_VSEL - [6:0] */ | |
538 | #define WM831X_DC3_SLP_VSEL_WIDTH 7 /* DC3_SLP_VSEL - [6:0] */ | |
539 | ||
540 | /* | |
541 | * R16484 (0x4064) - DC4 Control | |
542 | */ | |
543 | #define WM831X_DC4_ERR_ACT_MASK 0xC000 /* DC4_ERR_ACT - [15:14] */ | |
544 | #define WM831X_DC4_ERR_ACT_SHIFT 14 /* DC4_ERR_ACT - [15:14] */ | |
545 | #define WM831X_DC4_ERR_ACT_WIDTH 2 /* DC4_ERR_ACT - [15:14] */ | |
546 | #define WM831X_DC4_HWC_SRC_MASK 0x1800 /* DC4_HWC_SRC - [12:11] */ | |
547 | #define WM831X_DC4_HWC_SRC_SHIFT 11 /* DC4_HWC_SRC - [12:11] */ | |
548 | #define WM831X_DC4_HWC_SRC_WIDTH 2 /* DC4_HWC_SRC - [12:11] */ | |
549 | #define WM831X_DC4_HWC_MODE 0x0100 /* DC4_HWC_MODE */ | |
550 | #define WM831X_DC4_HWC_MODE_MASK 0x0100 /* DC4_HWC_MODE */ | |
551 | #define WM831X_DC4_HWC_MODE_SHIFT 8 /* DC4_HWC_MODE */ | |
552 | #define WM831X_DC4_HWC_MODE_WIDTH 1 /* DC4_HWC_MODE */ | |
553 | #define WM831X_DC4_RANGE_MASK 0x000C /* DC4_RANGE - [3:2] */ | |
554 | #define WM831X_DC4_RANGE_SHIFT 2 /* DC4_RANGE - [3:2] */ | |
555 | #define WM831X_DC4_RANGE_WIDTH 2 /* DC4_RANGE - [3:2] */ | |
556 | #define WM831X_DC4_FBSRC 0x0001 /* DC4_FBSRC */ | |
557 | #define WM831X_DC4_FBSRC_MASK 0x0001 /* DC4_FBSRC */ | |
558 | #define WM831X_DC4_FBSRC_SHIFT 0 /* DC4_FBSRC */ | |
559 | #define WM831X_DC4_FBSRC_WIDTH 1 /* DC4_FBSRC */ | |
560 | ||
561 | /* | |
562 | * R16485 (0x4065) - DC4 SLEEP Control | |
563 | */ | |
564 | #define WM831X_DC4_SLPENA 0x0100 /* DC4_SLPENA */ | |
565 | #define WM831X_DC4_SLPENA_MASK 0x0100 /* DC4_SLPENA */ | |
566 | #define WM831X_DC4_SLPENA_SHIFT 8 /* DC4_SLPENA */ | |
567 | #define WM831X_DC4_SLPENA_WIDTH 1 /* DC4_SLPENA */ | |
568 | ||
d1c6b4fe MB |
569 | /* |
570 | * R16488 (0x4068) - LDO1 Control | |
571 | */ | |
572 | #define WM831X_LDO1_ERR_ACT_MASK 0xC000 /* LDO1_ERR_ACT - [15:14] */ | |
573 | #define WM831X_LDO1_ERR_ACT_SHIFT 14 /* LDO1_ERR_ACT - [15:14] */ | |
574 | #define WM831X_LDO1_ERR_ACT_WIDTH 2 /* LDO1_ERR_ACT - [15:14] */ | |
575 | #define WM831X_LDO1_HWC_SRC_MASK 0x1800 /* LDO1_HWC_SRC - [12:11] */ | |
576 | #define WM831X_LDO1_HWC_SRC_SHIFT 11 /* LDO1_HWC_SRC - [12:11] */ | |
577 | #define WM831X_LDO1_HWC_SRC_WIDTH 2 /* LDO1_HWC_SRC - [12:11] */ | |
578 | #define WM831X_LDO1_HWC_VSEL 0x0400 /* LDO1_HWC_VSEL */ | |
579 | #define WM831X_LDO1_HWC_VSEL_MASK 0x0400 /* LDO1_HWC_VSEL */ | |
580 | #define WM831X_LDO1_HWC_VSEL_SHIFT 10 /* LDO1_HWC_VSEL */ | |
581 | #define WM831X_LDO1_HWC_VSEL_WIDTH 1 /* LDO1_HWC_VSEL */ | |
582 | #define WM831X_LDO1_HWC_MODE_MASK 0x0300 /* LDO1_HWC_MODE - [9:8] */ | |
583 | #define WM831X_LDO1_HWC_MODE_SHIFT 8 /* LDO1_HWC_MODE - [9:8] */ | |
584 | #define WM831X_LDO1_HWC_MODE_WIDTH 2 /* LDO1_HWC_MODE - [9:8] */ | |
585 | #define WM831X_LDO1_FLT 0x0080 /* LDO1_FLT */ | |
586 | #define WM831X_LDO1_FLT_MASK 0x0080 /* LDO1_FLT */ | |
587 | #define WM831X_LDO1_FLT_SHIFT 7 /* LDO1_FLT */ | |
588 | #define WM831X_LDO1_FLT_WIDTH 1 /* LDO1_FLT */ | |
589 | #define WM831X_LDO1_SWI 0x0040 /* LDO1_SWI */ | |
590 | #define WM831X_LDO1_SWI_MASK 0x0040 /* LDO1_SWI */ | |
591 | #define WM831X_LDO1_SWI_SHIFT 6 /* LDO1_SWI */ | |
592 | #define WM831X_LDO1_SWI_WIDTH 1 /* LDO1_SWI */ | |
593 | #define WM831X_LDO1_LP_MODE 0x0001 /* LDO1_LP_MODE */ | |
594 | #define WM831X_LDO1_LP_MODE_MASK 0x0001 /* LDO1_LP_MODE */ | |
595 | #define WM831X_LDO1_LP_MODE_SHIFT 0 /* LDO1_LP_MODE */ | |
596 | #define WM831X_LDO1_LP_MODE_WIDTH 1 /* LDO1_LP_MODE */ | |
597 | ||
598 | /* | |
599 | * R16489 (0x4069) - LDO1 ON Control | |
600 | */ | |
601 | #define WM831X_LDO1_ON_SLOT_MASK 0xE000 /* LDO1_ON_SLOT - [15:13] */ | |
602 | #define WM831X_LDO1_ON_SLOT_SHIFT 13 /* LDO1_ON_SLOT - [15:13] */ | |
603 | #define WM831X_LDO1_ON_SLOT_WIDTH 3 /* LDO1_ON_SLOT - [15:13] */ | |
604 | #define WM831X_LDO1_ON_MODE 0x0100 /* LDO1_ON_MODE */ | |
605 | #define WM831X_LDO1_ON_MODE_MASK 0x0100 /* LDO1_ON_MODE */ | |
606 | #define WM831X_LDO1_ON_MODE_SHIFT 8 /* LDO1_ON_MODE */ | |
607 | #define WM831X_LDO1_ON_MODE_WIDTH 1 /* LDO1_ON_MODE */ | |
608 | #define WM831X_LDO1_ON_VSEL_MASK 0x001F /* LDO1_ON_VSEL - [4:0] */ | |
609 | #define WM831X_LDO1_ON_VSEL_SHIFT 0 /* LDO1_ON_VSEL - [4:0] */ | |
610 | #define WM831X_LDO1_ON_VSEL_WIDTH 5 /* LDO1_ON_VSEL - [4:0] */ | |
611 | ||
612 | /* | |
613 | * R16490 (0x406A) - LDO1 SLEEP Control | |
614 | */ | |
615 | #define WM831X_LDO1_SLP_SLOT_MASK 0xE000 /* LDO1_SLP_SLOT - [15:13] */ | |
616 | #define WM831X_LDO1_SLP_SLOT_SHIFT 13 /* LDO1_SLP_SLOT - [15:13] */ | |
617 | #define WM831X_LDO1_SLP_SLOT_WIDTH 3 /* LDO1_SLP_SLOT - [15:13] */ | |
618 | #define WM831X_LDO1_SLP_MODE 0x0100 /* LDO1_SLP_MODE */ | |
619 | #define WM831X_LDO1_SLP_MODE_MASK 0x0100 /* LDO1_SLP_MODE */ | |
620 | #define WM831X_LDO1_SLP_MODE_SHIFT 8 /* LDO1_SLP_MODE */ | |
621 | #define WM831X_LDO1_SLP_MODE_WIDTH 1 /* LDO1_SLP_MODE */ | |
622 | #define WM831X_LDO1_SLP_VSEL_MASK 0x001F /* LDO1_SLP_VSEL - [4:0] */ | |
623 | #define WM831X_LDO1_SLP_VSEL_SHIFT 0 /* LDO1_SLP_VSEL - [4:0] */ | |
624 | #define WM831X_LDO1_SLP_VSEL_WIDTH 5 /* LDO1_SLP_VSEL - [4:0] */ | |
625 | ||
626 | /* | |
627 | * R16491 (0x406B) - LDO2 Control | |
628 | */ | |
629 | #define WM831X_LDO2_ERR_ACT_MASK 0xC000 /* LDO2_ERR_ACT - [15:14] */ | |
630 | #define WM831X_LDO2_ERR_ACT_SHIFT 14 /* LDO2_ERR_ACT - [15:14] */ | |
631 | #define WM831X_LDO2_ERR_ACT_WIDTH 2 /* LDO2_ERR_ACT - [15:14] */ | |
632 | #define WM831X_LDO2_HWC_SRC_MASK 0x1800 /* LDO2_HWC_SRC - [12:11] */ | |
633 | #define WM831X_LDO2_HWC_SRC_SHIFT 11 /* LDO2_HWC_SRC - [12:11] */ | |
634 | #define WM831X_LDO2_HWC_SRC_WIDTH 2 /* LDO2_HWC_SRC - [12:11] */ | |
635 | #define WM831X_LDO2_HWC_VSEL 0x0400 /* LDO2_HWC_VSEL */ | |
636 | #define WM831X_LDO2_HWC_VSEL_MASK 0x0400 /* LDO2_HWC_VSEL */ | |
637 | #define WM831X_LDO2_HWC_VSEL_SHIFT 10 /* LDO2_HWC_VSEL */ | |
638 | #define WM831X_LDO2_HWC_VSEL_WIDTH 1 /* LDO2_HWC_VSEL */ | |
639 | #define WM831X_LDO2_HWC_MODE_MASK 0x0300 /* LDO2_HWC_MODE - [9:8] */ | |
640 | #define WM831X_LDO2_HWC_MODE_SHIFT 8 /* LDO2_HWC_MODE - [9:8] */ | |
641 | #define WM831X_LDO2_HWC_MODE_WIDTH 2 /* LDO2_HWC_MODE - [9:8] */ | |
642 | #define WM831X_LDO2_FLT 0x0080 /* LDO2_FLT */ | |
643 | #define WM831X_LDO2_FLT_MASK 0x0080 /* LDO2_FLT */ | |
644 | #define WM831X_LDO2_FLT_SHIFT 7 /* LDO2_FLT */ | |
645 | #define WM831X_LDO2_FLT_WIDTH 1 /* LDO2_FLT */ | |
646 | #define WM831X_LDO2_SWI 0x0040 /* LDO2_SWI */ | |
647 | #define WM831X_LDO2_SWI_MASK 0x0040 /* LDO2_SWI */ | |
648 | #define WM831X_LDO2_SWI_SHIFT 6 /* LDO2_SWI */ | |
649 | #define WM831X_LDO2_SWI_WIDTH 1 /* LDO2_SWI */ | |
650 | #define WM831X_LDO2_LP_MODE 0x0001 /* LDO2_LP_MODE */ | |
651 | #define WM831X_LDO2_LP_MODE_MASK 0x0001 /* LDO2_LP_MODE */ | |
652 | #define WM831X_LDO2_LP_MODE_SHIFT 0 /* LDO2_LP_MODE */ | |
653 | #define WM831X_LDO2_LP_MODE_WIDTH 1 /* LDO2_LP_MODE */ | |
654 | ||
655 | /* | |
656 | * R16492 (0x406C) - LDO2 ON Control | |
657 | */ | |
658 | #define WM831X_LDO2_ON_SLOT_MASK 0xE000 /* LDO2_ON_SLOT - [15:13] */ | |
659 | #define WM831X_LDO2_ON_SLOT_SHIFT 13 /* LDO2_ON_SLOT - [15:13] */ | |
660 | #define WM831X_LDO2_ON_SLOT_WIDTH 3 /* LDO2_ON_SLOT - [15:13] */ | |
661 | #define WM831X_LDO2_ON_MODE 0x0100 /* LDO2_ON_MODE */ | |
662 | #define WM831X_LDO2_ON_MODE_MASK 0x0100 /* LDO2_ON_MODE */ | |
663 | #define WM831X_LDO2_ON_MODE_SHIFT 8 /* LDO2_ON_MODE */ | |
664 | #define WM831X_LDO2_ON_MODE_WIDTH 1 /* LDO2_ON_MODE */ | |
665 | #define WM831X_LDO2_ON_VSEL_MASK 0x001F /* LDO2_ON_VSEL - [4:0] */ | |
666 | #define WM831X_LDO2_ON_VSEL_SHIFT 0 /* LDO2_ON_VSEL - [4:0] */ | |
667 | #define WM831X_LDO2_ON_VSEL_WIDTH 5 /* LDO2_ON_VSEL - [4:0] */ | |
668 | ||
669 | /* | |
670 | * R16493 (0x406D) - LDO2 SLEEP Control | |
671 | */ | |
672 | #define WM831X_LDO2_SLP_SLOT_MASK 0xE000 /* LDO2_SLP_SLOT - [15:13] */ | |
673 | #define WM831X_LDO2_SLP_SLOT_SHIFT 13 /* LDO2_SLP_SLOT - [15:13] */ | |
674 | #define WM831X_LDO2_SLP_SLOT_WIDTH 3 /* LDO2_SLP_SLOT - [15:13] */ | |
675 | #define WM831X_LDO2_SLP_MODE 0x0100 /* LDO2_SLP_MODE */ | |
676 | #define WM831X_LDO2_SLP_MODE_MASK 0x0100 /* LDO2_SLP_MODE */ | |
677 | #define WM831X_LDO2_SLP_MODE_SHIFT 8 /* LDO2_SLP_MODE */ | |
678 | #define WM831X_LDO2_SLP_MODE_WIDTH 1 /* LDO2_SLP_MODE */ | |
679 | #define WM831X_LDO2_SLP_VSEL_MASK 0x001F /* LDO2_SLP_VSEL - [4:0] */ | |
680 | #define WM831X_LDO2_SLP_VSEL_SHIFT 0 /* LDO2_SLP_VSEL - [4:0] */ | |
681 | #define WM831X_LDO2_SLP_VSEL_WIDTH 5 /* LDO2_SLP_VSEL - [4:0] */ | |
682 | ||
683 | /* | |
684 | * R16494 (0x406E) - LDO3 Control | |
685 | */ | |
686 | #define WM831X_LDO3_ERR_ACT_MASK 0xC000 /* LDO3_ERR_ACT - [15:14] */ | |
687 | #define WM831X_LDO3_ERR_ACT_SHIFT 14 /* LDO3_ERR_ACT - [15:14] */ | |
688 | #define WM831X_LDO3_ERR_ACT_WIDTH 2 /* LDO3_ERR_ACT - [15:14] */ | |
689 | #define WM831X_LDO3_HWC_SRC_MASK 0x1800 /* LDO3_HWC_SRC - [12:11] */ | |
690 | #define WM831X_LDO3_HWC_SRC_SHIFT 11 /* LDO3_HWC_SRC - [12:11] */ | |
691 | #define WM831X_LDO3_HWC_SRC_WIDTH 2 /* LDO3_HWC_SRC - [12:11] */ | |
692 | #define WM831X_LDO3_HWC_VSEL 0x0400 /* LDO3_HWC_VSEL */ | |
693 | #define WM831X_LDO3_HWC_VSEL_MASK 0x0400 /* LDO3_HWC_VSEL */ | |
694 | #define WM831X_LDO3_HWC_VSEL_SHIFT 10 /* LDO3_HWC_VSEL */ | |
695 | #define WM831X_LDO3_HWC_VSEL_WIDTH 1 /* LDO3_HWC_VSEL */ | |
696 | #define WM831X_LDO3_HWC_MODE_MASK 0x0300 /* LDO3_HWC_MODE - [9:8] */ | |
697 | #define WM831X_LDO3_HWC_MODE_SHIFT 8 /* LDO3_HWC_MODE - [9:8] */ | |
698 | #define WM831X_LDO3_HWC_MODE_WIDTH 2 /* LDO3_HWC_MODE - [9:8] */ | |
699 | #define WM831X_LDO3_FLT 0x0080 /* LDO3_FLT */ | |
700 | #define WM831X_LDO3_FLT_MASK 0x0080 /* LDO3_FLT */ | |
701 | #define WM831X_LDO3_FLT_SHIFT 7 /* LDO3_FLT */ | |
702 | #define WM831X_LDO3_FLT_WIDTH 1 /* LDO3_FLT */ | |
703 | #define WM831X_LDO3_SWI 0x0040 /* LDO3_SWI */ | |
704 | #define WM831X_LDO3_SWI_MASK 0x0040 /* LDO3_SWI */ | |
705 | #define WM831X_LDO3_SWI_SHIFT 6 /* LDO3_SWI */ | |
706 | #define WM831X_LDO3_SWI_WIDTH 1 /* LDO3_SWI */ | |
707 | #define WM831X_LDO3_LP_MODE 0x0001 /* LDO3_LP_MODE */ | |
708 | #define WM831X_LDO3_LP_MODE_MASK 0x0001 /* LDO3_LP_MODE */ | |
709 | #define WM831X_LDO3_LP_MODE_SHIFT 0 /* LDO3_LP_MODE */ | |
710 | #define WM831X_LDO3_LP_MODE_WIDTH 1 /* LDO3_LP_MODE */ | |
711 | ||
712 | /* | |
713 | * R16495 (0x406F) - LDO3 ON Control | |
714 | */ | |
715 | #define WM831X_LDO3_ON_SLOT_MASK 0xE000 /* LDO3_ON_SLOT - [15:13] */ | |
716 | #define WM831X_LDO3_ON_SLOT_SHIFT 13 /* LDO3_ON_SLOT - [15:13] */ | |
717 | #define WM831X_LDO3_ON_SLOT_WIDTH 3 /* LDO3_ON_SLOT - [15:13] */ | |
718 | #define WM831X_LDO3_ON_MODE 0x0100 /* LDO3_ON_MODE */ | |
719 | #define WM831X_LDO3_ON_MODE_MASK 0x0100 /* LDO3_ON_MODE */ | |
720 | #define WM831X_LDO3_ON_MODE_SHIFT 8 /* LDO3_ON_MODE */ | |
721 | #define WM831X_LDO3_ON_MODE_WIDTH 1 /* LDO3_ON_MODE */ | |
722 | #define WM831X_LDO3_ON_VSEL_MASK 0x001F /* LDO3_ON_VSEL - [4:0] */ | |
723 | #define WM831X_LDO3_ON_VSEL_SHIFT 0 /* LDO3_ON_VSEL - [4:0] */ | |
724 | #define WM831X_LDO3_ON_VSEL_WIDTH 5 /* LDO3_ON_VSEL - [4:0] */ | |
725 | ||
726 | /* | |
727 | * R16496 (0x4070) - LDO3 SLEEP Control | |
728 | */ | |
729 | #define WM831X_LDO3_SLP_SLOT_MASK 0xE000 /* LDO3_SLP_SLOT - [15:13] */ | |
730 | #define WM831X_LDO3_SLP_SLOT_SHIFT 13 /* LDO3_SLP_SLOT - [15:13] */ | |
731 | #define WM831X_LDO3_SLP_SLOT_WIDTH 3 /* LDO3_SLP_SLOT - [15:13] */ | |
732 | #define WM831X_LDO3_SLP_MODE 0x0100 /* LDO3_SLP_MODE */ | |
733 | #define WM831X_LDO3_SLP_MODE_MASK 0x0100 /* LDO3_SLP_MODE */ | |
734 | #define WM831X_LDO3_SLP_MODE_SHIFT 8 /* LDO3_SLP_MODE */ | |
735 | #define WM831X_LDO3_SLP_MODE_WIDTH 1 /* LDO3_SLP_MODE */ | |
736 | #define WM831X_LDO3_SLP_VSEL_MASK 0x001F /* LDO3_SLP_VSEL - [4:0] */ | |
737 | #define WM831X_LDO3_SLP_VSEL_SHIFT 0 /* LDO3_SLP_VSEL - [4:0] */ | |
738 | #define WM831X_LDO3_SLP_VSEL_WIDTH 5 /* LDO3_SLP_VSEL - [4:0] */ | |
739 | ||
740 | /* | |
741 | * R16497 (0x4071) - LDO4 Control | |
742 | */ | |
743 | #define WM831X_LDO4_ERR_ACT_MASK 0xC000 /* LDO4_ERR_ACT - [15:14] */ | |
744 | #define WM831X_LDO4_ERR_ACT_SHIFT 14 /* LDO4_ERR_ACT - [15:14] */ | |
745 | #define WM831X_LDO4_ERR_ACT_WIDTH 2 /* LDO4_ERR_ACT - [15:14] */ | |
746 | #define WM831X_LDO4_HWC_SRC_MASK 0x1800 /* LDO4_HWC_SRC - [12:11] */ | |
747 | #define WM831X_LDO4_HWC_SRC_SHIFT 11 /* LDO4_HWC_SRC - [12:11] */ | |
748 | #define WM831X_LDO4_HWC_SRC_WIDTH 2 /* LDO4_HWC_SRC - [12:11] */ | |
749 | #define WM831X_LDO4_HWC_VSEL 0x0400 /* LDO4_HWC_VSEL */ | |
750 | #define WM831X_LDO4_HWC_VSEL_MASK 0x0400 /* LDO4_HWC_VSEL */ | |
751 | #define WM831X_LDO4_HWC_VSEL_SHIFT 10 /* LDO4_HWC_VSEL */ | |
752 | #define WM831X_LDO4_HWC_VSEL_WIDTH 1 /* LDO4_HWC_VSEL */ | |
753 | #define WM831X_LDO4_HWC_MODE_MASK 0x0300 /* LDO4_HWC_MODE - [9:8] */ | |
754 | #define WM831X_LDO4_HWC_MODE_SHIFT 8 /* LDO4_HWC_MODE - [9:8] */ | |
755 | #define WM831X_LDO4_HWC_MODE_WIDTH 2 /* LDO4_HWC_MODE - [9:8] */ | |
756 | #define WM831X_LDO4_FLT 0x0080 /* LDO4_FLT */ | |
757 | #define WM831X_LDO4_FLT_MASK 0x0080 /* LDO4_FLT */ | |
758 | #define WM831X_LDO4_FLT_SHIFT 7 /* LDO4_FLT */ | |
759 | #define WM831X_LDO4_FLT_WIDTH 1 /* LDO4_FLT */ | |
760 | #define WM831X_LDO4_SWI 0x0040 /* LDO4_SWI */ | |
761 | #define WM831X_LDO4_SWI_MASK 0x0040 /* LDO4_SWI */ | |
762 | #define WM831X_LDO4_SWI_SHIFT 6 /* LDO4_SWI */ | |
763 | #define WM831X_LDO4_SWI_WIDTH 1 /* LDO4_SWI */ | |
764 | #define WM831X_LDO4_LP_MODE 0x0001 /* LDO4_LP_MODE */ | |
765 | #define WM831X_LDO4_LP_MODE_MASK 0x0001 /* LDO4_LP_MODE */ | |
766 | #define WM831X_LDO4_LP_MODE_SHIFT 0 /* LDO4_LP_MODE */ | |
767 | #define WM831X_LDO4_LP_MODE_WIDTH 1 /* LDO4_LP_MODE */ | |
768 | ||
769 | /* | |
770 | * R16498 (0x4072) - LDO4 ON Control | |
771 | */ | |
772 | #define WM831X_LDO4_ON_SLOT_MASK 0xE000 /* LDO4_ON_SLOT - [15:13] */ | |
773 | #define WM831X_LDO4_ON_SLOT_SHIFT 13 /* LDO4_ON_SLOT - [15:13] */ | |
774 | #define WM831X_LDO4_ON_SLOT_WIDTH 3 /* LDO4_ON_SLOT - [15:13] */ | |
775 | #define WM831X_LDO4_ON_MODE 0x0100 /* LDO4_ON_MODE */ | |
776 | #define WM831X_LDO4_ON_MODE_MASK 0x0100 /* LDO4_ON_MODE */ | |
777 | #define WM831X_LDO4_ON_MODE_SHIFT 8 /* LDO4_ON_MODE */ | |
778 | #define WM831X_LDO4_ON_MODE_WIDTH 1 /* LDO4_ON_MODE */ | |
779 | #define WM831X_LDO4_ON_VSEL_MASK 0x001F /* LDO4_ON_VSEL - [4:0] */ | |
780 | #define WM831X_LDO4_ON_VSEL_SHIFT 0 /* LDO4_ON_VSEL - [4:0] */ | |
781 | #define WM831X_LDO4_ON_VSEL_WIDTH 5 /* LDO4_ON_VSEL - [4:0] */ | |
782 | ||
783 | /* | |
784 | * R16499 (0x4073) - LDO4 SLEEP Control | |
785 | */ | |
786 | #define WM831X_LDO4_SLP_SLOT_MASK 0xE000 /* LDO4_SLP_SLOT - [15:13] */ | |
787 | #define WM831X_LDO4_SLP_SLOT_SHIFT 13 /* LDO4_SLP_SLOT - [15:13] */ | |
788 | #define WM831X_LDO4_SLP_SLOT_WIDTH 3 /* LDO4_SLP_SLOT - [15:13] */ | |
789 | #define WM831X_LDO4_SLP_MODE 0x0100 /* LDO4_SLP_MODE */ | |
790 | #define WM831X_LDO4_SLP_MODE_MASK 0x0100 /* LDO4_SLP_MODE */ | |
791 | #define WM831X_LDO4_SLP_MODE_SHIFT 8 /* LDO4_SLP_MODE */ | |
792 | #define WM831X_LDO4_SLP_MODE_WIDTH 1 /* LDO4_SLP_MODE */ | |
793 | #define WM831X_LDO4_SLP_VSEL_MASK 0x001F /* LDO4_SLP_VSEL - [4:0] */ | |
794 | #define WM831X_LDO4_SLP_VSEL_SHIFT 0 /* LDO4_SLP_VSEL - [4:0] */ | |
795 | #define WM831X_LDO4_SLP_VSEL_WIDTH 5 /* LDO4_SLP_VSEL - [4:0] */ | |
796 | ||
797 | /* | |
798 | * R16500 (0x4074) - LDO5 Control | |
799 | */ | |
800 | #define WM831X_LDO5_ERR_ACT_MASK 0xC000 /* LDO5_ERR_ACT - [15:14] */ | |
801 | #define WM831X_LDO5_ERR_ACT_SHIFT 14 /* LDO5_ERR_ACT - [15:14] */ | |
802 | #define WM831X_LDO5_ERR_ACT_WIDTH 2 /* LDO5_ERR_ACT - [15:14] */ | |
803 | #define WM831X_LDO5_HWC_SRC_MASK 0x1800 /* LDO5_HWC_SRC - [12:11] */ | |
804 | #define WM831X_LDO5_HWC_SRC_SHIFT 11 /* LDO5_HWC_SRC - [12:11] */ | |
805 | #define WM831X_LDO5_HWC_SRC_WIDTH 2 /* LDO5_HWC_SRC - [12:11] */ | |
806 | #define WM831X_LDO5_HWC_VSEL 0x0400 /* LDO5_HWC_VSEL */ | |
807 | #define WM831X_LDO5_HWC_VSEL_MASK 0x0400 /* LDO5_HWC_VSEL */ | |
808 | #define WM831X_LDO5_HWC_VSEL_SHIFT 10 /* LDO5_HWC_VSEL */ | |
809 | #define WM831X_LDO5_HWC_VSEL_WIDTH 1 /* LDO5_HWC_VSEL */ | |
810 | #define WM831X_LDO5_HWC_MODE_MASK 0x0300 /* LDO5_HWC_MODE - [9:8] */ | |
811 | #define WM831X_LDO5_HWC_MODE_SHIFT 8 /* LDO5_HWC_MODE - [9:8] */ | |
812 | #define WM831X_LDO5_HWC_MODE_WIDTH 2 /* LDO5_HWC_MODE - [9:8] */ | |
813 | #define WM831X_LDO5_FLT 0x0080 /* LDO5_FLT */ | |
814 | #define WM831X_LDO5_FLT_MASK 0x0080 /* LDO5_FLT */ | |
815 | #define WM831X_LDO5_FLT_SHIFT 7 /* LDO5_FLT */ | |
816 | #define WM831X_LDO5_FLT_WIDTH 1 /* LDO5_FLT */ | |
817 | #define WM831X_LDO5_SWI 0x0040 /* LDO5_SWI */ | |
818 | #define WM831X_LDO5_SWI_MASK 0x0040 /* LDO5_SWI */ | |
819 | #define WM831X_LDO5_SWI_SHIFT 6 /* LDO5_SWI */ | |
820 | #define WM831X_LDO5_SWI_WIDTH 1 /* LDO5_SWI */ | |
821 | #define WM831X_LDO5_LP_MODE 0x0001 /* LDO5_LP_MODE */ | |
822 | #define WM831X_LDO5_LP_MODE_MASK 0x0001 /* LDO5_LP_MODE */ | |
823 | #define WM831X_LDO5_LP_MODE_SHIFT 0 /* LDO5_LP_MODE */ | |
824 | #define WM831X_LDO5_LP_MODE_WIDTH 1 /* LDO5_LP_MODE */ | |
825 | ||
826 | /* | |
827 | * R16501 (0x4075) - LDO5 ON Control | |
828 | */ | |
829 | #define WM831X_LDO5_ON_SLOT_MASK 0xE000 /* LDO5_ON_SLOT - [15:13] */ | |
830 | #define WM831X_LDO5_ON_SLOT_SHIFT 13 /* LDO5_ON_SLOT - [15:13] */ | |
831 | #define WM831X_LDO5_ON_SLOT_WIDTH 3 /* LDO5_ON_SLOT - [15:13] */ | |
832 | #define WM831X_LDO5_ON_MODE 0x0100 /* LDO5_ON_MODE */ | |
833 | #define WM831X_LDO5_ON_MODE_MASK 0x0100 /* LDO5_ON_MODE */ | |
834 | #define WM831X_LDO5_ON_MODE_SHIFT 8 /* LDO5_ON_MODE */ | |
835 | #define WM831X_LDO5_ON_MODE_WIDTH 1 /* LDO5_ON_MODE */ | |
836 | #define WM831X_LDO5_ON_VSEL_MASK 0x001F /* LDO5_ON_VSEL - [4:0] */ | |
837 | #define WM831X_LDO5_ON_VSEL_SHIFT 0 /* LDO5_ON_VSEL - [4:0] */ | |
838 | #define WM831X_LDO5_ON_VSEL_WIDTH 5 /* LDO5_ON_VSEL - [4:0] */ | |
839 | ||
840 | /* | |
841 | * R16502 (0x4076) - LDO5 SLEEP Control | |
842 | */ | |
843 | #define WM831X_LDO5_SLP_SLOT_MASK 0xE000 /* LDO5_SLP_SLOT - [15:13] */ | |
844 | #define WM831X_LDO5_SLP_SLOT_SHIFT 13 /* LDO5_SLP_SLOT - [15:13] */ | |
845 | #define WM831X_LDO5_SLP_SLOT_WIDTH 3 /* LDO5_SLP_SLOT - [15:13] */ | |
846 | #define WM831X_LDO5_SLP_MODE 0x0100 /* LDO5_SLP_MODE */ | |
847 | #define WM831X_LDO5_SLP_MODE_MASK 0x0100 /* LDO5_SLP_MODE */ | |
848 | #define WM831X_LDO5_SLP_MODE_SHIFT 8 /* LDO5_SLP_MODE */ | |
849 | #define WM831X_LDO5_SLP_MODE_WIDTH 1 /* LDO5_SLP_MODE */ | |
850 | #define WM831X_LDO5_SLP_VSEL_MASK 0x001F /* LDO5_SLP_VSEL - [4:0] */ | |
851 | #define WM831X_LDO5_SLP_VSEL_SHIFT 0 /* LDO5_SLP_VSEL - [4:0] */ | |
852 | #define WM831X_LDO5_SLP_VSEL_WIDTH 5 /* LDO5_SLP_VSEL - [4:0] */ | |
853 | ||
854 | /* | |
855 | * R16503 (0x4077) - LDO6 Control | |
856 | */ | |
857 | #define WM831X_LDO6_ERR_ACT_MASK 0xC000 /* LDO6_ERR_ACT - [15:14] */ | |
858 | #define WM831X_LDO6_ERR_ACT_SHIFT 14 /* LDO6_ERR_ACT - [15:14] */ | |
859 | #define WM831X_LDO6_ERR_ACT_WIDTH 2 /* LDO6_ERR_ACT - [15:14] */ | |
860 | #define WM831X_LDO6_HWC_SRC_MASK 0x1800 /* LDO6_HWC_SRC - [12:11] */ | |
861 | #define WM831X_LDO6_HWC_SRC_SHIFT 11 /* LDO6_HWC_SRC - [12:11] */ | |
862 | #define WM831X_LDO6_HWC_SRC_WIDTH 2 /* LDO6_HWC_SRC - [12:11] */ | |
863 | #define WM831X_LDO6_HWC_VSEL 0x0400 /* LDO6_HWC_VSEL */ | |
864 | #define WM831X_LDO6_HWC_VSEL_MASK 0x0400 /* LDO6_HWC_VSEL */ | |
865 | #define WM831X_LDO6_HWC_VSEL_SHIFT 10 /* LDO6_HWC_VSEL */ | |
866 | #define WM831X_LDO6_HWC_VSEL_WIDTH 1 /* LDO6_HWC_VSEL */ | |
867 | #define WM831X_LDO6_HWC_MODE_MASK 0x0300 /* LDO6_HWC_MODE - [9:8] */ | |
868 | #define WM831X_LDO6_HWC_MODE_SHIFT 8 /* LDO6_HWC_MODE - [9:8] */ | |
869 | #define WM831X_LDO6_HWC_MODE_WIDTH 2 /* LDO6_HWC_MODE - [9:8] */ | |
870 | #define WM831X_LDO6_FLT 0x0080 /* LDO6_FLT */ | |
871 | #define WM831X_LDO6_FLT_MASK 0x0080 /* LDO6_FLT */ | |
872 | #define WM831X_LDO6_FLT_SHIFT 7 /* LDO6_FLT */ | |
873 | #define WM831X_LDO6_FLT_WIDTH 1 /* LDO6_FLT */ | |
874 | #define WM831X_LDO6_SWI 0x0040 /* LDO6_SWI */ | |
875 | #define WM831X_LDO6_SWI_MASK 0x0040 /* LDO6_SWI */ | |
876 | #define WM831X_LDO6_SWI_SHIFT 6 /* LDO6_SWI */ | |
877 | #define WM831X_LDO6_SWI_WIDTH 1 /* LDO6_SWI */ | |
878 | #define WM831X_LDO6_LP_MODE 0x0001 /* LDO6_LP_MODE */ | |
879 | #define WM831X_LDO6_LP_MODE_MASK 0x0001 /* LDO6_LP_MODE */ | |
880 | #define WM831X_LDO6_LP_MODE_SHIFT 0 /* LDO6_LP_MODE */ | |
881 | #define WM831X_LDO6_LP_MODE_WIDTH 1 /* LDO6_LP_MODE */ | |
882 | ||
883 | /* | |
884 | * R16504 (0x4078) - LDO6 ON Control | |
885 | */ | |
886 | #define WM831X_LDO6_ON_SLOT_MASK 0xE000 /* LDO6_ON_SLOT - [15:13] */ | |
887 | #define WM831X_LDO6_ON_SLOT_SHIFT 13 /* LDO6_ON_SLOT - [15:13] */ | |
888 | #define WM831X_LDO6_ON_SLOT_WIDTH 3 /* LDO6_ON_SLOT - [15:13] */ | |
889 | #define WM831X_LDO6_ON_MODE 0x0100 /* LDO6_ON_MODE */ | |
890 | #define WM831X_LDO6_ON_MODE_MASK 0x0100 /* LDO6_ON_MODE */ | |
891 | #define WM831X_LDO6_ON_MODE_SHIFT 8 /* LDO6_ON_MODE */ | |
892 | #define WM831X_LDO6_ON_MODE_WIDTH 1 /* LDO6_ON_MODE */ | |
893 | #define WM831X_LDO6_ON_VSEL_MASK 0x001F /* LDO6_ON_VSEL - [4:0] */ | |
894 | #define WM831X_LDO6_ON_VSEL_SHIFT 0 /* LDO6_ON_VSEL - [4:0] */ | |
895 | #define WM831X_LDO6_ON_VSEL_WIDTH 5 /* LDO6_ON_VSEL - [4:0] */ | |
896 | ||
897 | /* | |
898 | * R16505 (0x4079) - LDO6 SLEEP Control | |
899 | */ | |
900 | #define WM831X_LDO6_SLP_SLOT_MASK 0xE000 /* LDO6_SLP_SLOT - [15:13] */ | |
901 | #define WM831X_LDO6_SLP_SLOT_SHIFT 13 /* LDO6_SLP_SLOT - [15:13] */ | |
902 | #define WM831X_LDO6_SLP_SLOT_WIDTH 3 /* LDO6_SLP_SLOT - [15:13] */ | |
903 | #define WM831X_LDO6_SLP_MODE 0x0100 /* LDO6_SLP_MODE */ | |
904 | #define WM831X_LDO6_SLP_MODE_MASK 0x0100 /* LDO6_SLP_MODE */ | |
905 | #define WM831X_LDO6_SLP_MODE_SHIFT 8 /* LDO6_SLP_MODE */ | |
906 | #define WM831X_LDO6_SLP_MODE_WIDTH 1 /* LDO6_SLP_MODE */ | |
907 | #define WM831X_LDO6_SLP_VSEL_MASK 0x001F /* LDO6_SLP_VSEL - [4:0] */ | |
908 | #define WM831X_LDO6_SLP_VSEL_SHIFT 0 /* LDO6_SLP_VSEL - [4:0] */ | |
909 | #define WM831X_LDO6_SLP_VSEL_WIDTH 5 /* LDO6_SLP_VSEL - [4:0] */ | |
910 | ||
911 | /* | |
912 | * R16506 (0x407A) - LDO7 Control | |
913 | */ | |
914 | #define WM831X_LDO7_ERR_ACT_MASK 0xC000 /* LDO7_ERR_ACT - [15:14] */ | |
915 | #define WM831X_LDO7_ERR_ACT_SHIFT 14 /* LDO7_ERR_ACT - [15:14] */ | |
916 | #define WM831X_LDO7_ERR_ACT_WIDTH 2 /* LDO7_ERR_ACT - [15:14] */ | |
917 | #define WM831X_LDO7_HWC_SRC_MASK 0x1800 /* LDO7_HWC_SRC - [12:11] */ | |
918 | #define WM831X_LDO7_HWC_SRC_SHIFT 11 /* LDO7_HWC_SRC - [12:11] */ | |
919 | #define WM831X_LDO7_HWC_SRC_WIDTH 2 /* LDO7_HWC_SRC - [12:11] */ | |
920 | #define WM831X_LDO7_HWC_VSEL 0x0400 /* LDO7_HWC_VSEL */ | |
921 | #define WM831X_LDO7_HWC_VSEL_MASK 0x0400 /* LDO7_HWC_VSEL */ | |
922 | #define WM831X_LDO7_HWC_VSEL_SHIFT 10 /* LDO7_HWC_VSEL */ | |
923 | #define WM831X_LDO7_HWC_VSEL_WIDTH 1 /* LDO7_HWC_VSEL */ | |
924 | #define WM831X_LDO7_HWC_MODE_MASK 0x0300 /* LDO7_HWC_MODE - [9:8] */ | |
925 | #define WM831X_LDO7_HWC_MODE_SHIFT 8 /* LDO7_HWC_MODE - [9:8] */ | |
926 | #define WM831X_LDO7_HWC_MODE_WIDTH 2 /* LDO7_HWC_MODE - [9:8] */ | |
927 | #define WM831X_LDO7_FLT 0x0080 /* LDO7_FLT */ | |
928 | #define WM831X_LDO7_FLT_MASK 0x0080 /* LDO7_FLT */ | |
929 | #define WM831X_LDO7_FLT_SHIFT 7 /* LDO7_FLT */ | |
930 | #define WM831X_LDO7_FLT_WIDTH 1 /* LDO7_FLT */ | |
931 | #define WM831X_LDO7_SWI 0x0040 /* LDO7_SWI */ | |
932 | #define WM831X_LDO7_SWI_MASK 0x0040 /* LDO7_SWI */ | |
933 | #define WM831X_LDO7_SWI_SHIFT 6 /* LDO7_SWI */ | |
934 | #define WM831X_LDO7_SWI_WIDTH 1 /* LDO7_SWI */ | |
935 | ||
936 | /* | |
937 | * R16507 (0x407B) - LDO7 ON Control | |
938 | */ | |
939 | #define WM831X_LDO7_ON_SLOT_MASK 0xE000 /* LDO7_ON_SLOT - [15:13] */ | |
940 | #define WM831X_LDO7_ON_SLOT_SHIFT 13 /* LDO7_ON_SLOT - [15:13] */ | |
941 | #define WM831X_LDO7_ON_SLOT_WIDTH 3 /* LDO7_ON_SLOT - [15:13] */ | |
942 | #define WM831X_LDO7_ON_MODE 0x0100 /* LDO7_ON_MODE */ | |
943 | #define WM831X_LDO7_ON_MODE_MASK 0x0100 /* LDO7_ON_MODE */ | |
944 | #define WM831X_LDO7_ON_MODE_SHIFT 8 /* LDO7_ON_MODE */ | |
945 | #define WM831X_LDO7_ON_MODE_WIDTH 1 /* LDO7_ON_MODE */ | |
946 | #define WM831X_LDO7_ON_VSEL_MASK 0x001F /* LDO7_ON_VSEL - [4:0] */ | |
947 | #define WM831X_LDO7_ON_VSEL_SHIFT 0 /* LDO7_ON_VSEL - [4:0] */ | |
948 | #define WM831X_LDO7_ON_VSEL_WIDTH 5 /* LDO7_ON_VSEL - [4:0] */ | |
949 | ||
950 | /* | |
951 | * R16508 (0x407C) - LDO7 SLEEP Control | |
952 | */ | |
953 | #define WM831X_LDO7_SLP_SLOT_MASK 0xE000 /* LDO7_SLP_SLOT - [15:13] */ | |
954 | #define WM831X_LDO7_SLP_SLOT_SHIFT 13 /* LDO7_SLP_SLOT - [15:13] */ | |
955 | #define WM831X_LDO7_SLP_SLOT_WIDTH 3 /* LDO7_SLP_SLOT - [15:13] */ | |
956 | #define WM831X_LDO7_SLP_MODE 0x0100 /* LDO7_SLP_MODE */ | |
957 | #define WM831X_LDO7_SLP_MODE_MASK 0x0100 /* LDO7_SLP_MODE */ | |
958 | #define WM831X_LDO7_SLP_MODE_SHIFT 8 /* LDO7_SLP_MODE */ | |
959 | #define WM831X_LDO7_SLP_MODE_WIDTH 1 /* LDO7_SLP_MODE */ | |
960 | #define WM831X_LDO7_SLP_VSEL_MASK 0x001F /* LDO7_SLP_VSEL - [4:0] */ | |
961 | #define WM831X_LDO7_SLP_VSEL_SHIFT 0 /* LDO7_SLP_VSEL - [4:0] */ | |
962 | #define WM831X_LDO7_SLP_VSEL_WIDTH 5 /* LDO7_SLP_VSEL - [4:0] */ | |
963 | ||
964 | /* | |
965 | * R16509 (0x407D) - LDO8 Control | |
966 | */ | |
967 | #define WM831X_LDO8_ERR_ACT_MASK 0xC000 /* LDO8_ERR_ACT - [15:14] */ | |
968 | #define WM831X_LDO8_ERR_ACT_SHIFT 14 /* LDO8_ERR_ACT - [15:14] */ | |
969 | #define WM831X_LDO8_ERR_ACT_WIDTH 2 /* LDO8_ERR_ACT - [15:14] */ | |
970 | #define WM831X_LDO8_HWC_SRC_MASK 0x1800 /* LDO8_HWC_SRC - [12:11] */ | |
971 | #define WM831X_LDO8_HWC_SRC_SHIFT 11 /* LDO8_HWC_SRC - [12:11] */ | |
972 | #define WM831X_LDO8_HWC_SRC_WIDTH 2 /* LDO8_HWC_SRC - [12:11] */ | |
973 | #define WM831X_LDO8_HWC_VSEL 0x0400 /* LDO8_HWC_VSEL */ | |
974 | #define WM831X_LDO8_HWC_VSEL_MASK 0x0400 /* LDO8_HWC_VSEL */ | |
975 | #define WM831X_LDO8_HWC_VSEL_SHIFT 10 /* LDO8_HWC_VSEL */ | |
976 | #define WM831X_LDO8_HWC_VSEL_WIDTH 1 /* LDO8_HWC_VSEL */ | |
977 | #define WM831X_LDO8_HWC_MODE_MASK 0x0300 /* LDO8_HWC_MODE - [9:8] */ | |
978 | #define WM831X_LDO8_HWC_MODE_SHIFT 8 /* LDO8_HWC_MODE - [9:8] */ | |
979 | #define WM831X_LDO8_HWC_MODE_WIDTH 2 /* LDO8_HWC_MODE - [9:8] */ | |
980 | #define WM831X_LDO8_FLT 0x0080 /* LDO8_FLT */ | |
981 | #define WM831X_LDO8_FLT_MASK 0x0080 /* LDO8_FLT */ | |
982 | #define WM831X_LDO8_FLT_SHIFT 7 /* LDO8_FLT */ | |
983 | #define WM831X_LDO8_FLT_WIDTH 1 /* LDO8_FLT */ | |
984 | #define WM831X_LDO8_SWI 0x0040 /* LDO8_SWI */ | |
985 | #define WM831X_LDO8_SWI_MASK 0x0040 /* LDO8_SWI */ | |
986 | #define WM831X_LDO8_SWI_SHIFT 6 /* LDO8_SWI */ | |
987 | #define WM831X_LDO8_SWI_WIDTH 1 /* LDO8_SWI */ | |
988 | ||
989 | /* | |
990 | * R16510 (0x407E) - LDO8 ON Control | |
991 | */ | |
992 | #define WM831X_LDO8_ON_SLOT_MASK 0xE000 /* LDO8_ON_SLOT - [15:13] */ | |
993 | #define WM831X_LDO8_ON_SLOT_SHIFT 13 /* LDO8_ON_SLOT - [15:13] */ | |
994 | #define WM831X_LDO8_ON_SLOT_WIDTH 3 /* LDO8_ON_SLOT - [15:13] */ | |
995 | #define WM831X_LDO8_ON_MODE 0x0100 /* LDO8_ON_MODE */ | |
996 | #define WM831X_LDO8_ON_MODE_MASK 0x0100 /* LDO8_ON_MODE */ | |
997 | #define WM831X_LDO8_ON_MODE_SHIFT 8 /* LDO8_ON_MODE */ | |
998 | #define WM831X_LDO8_ON_MODE_WIDTH 1 /* LDO8_ON_MODE */ | |
999 | #define WM831X_LDO8_ON_VSEL_MASK 0x001F /* LDO8_ON_VSEL - [4:0] */ | |
1000 | #define WM831X_LDO8_ON_VSEL_SHIFT 0 /* LDO8_ON_VSEL - [4:0] */ | |
1001 | #define WM831X_LDO8_ON_VSEL_WIDTH 5 /* LDO8_ON_VSEL - [4:0] */ | |
1002 | ||
1003 | /* | |
1004 | * R16511 (0x407F) - LDO8 SLEEP Control | |
1005 | */ | |
1006 | #define WM831X_LDO8_SLP_SLOT_MASK 0xE000 /* LDO8_SLP_SLOT - [15:13] */ | |
1007 | #define WM831X_LDO8_SLP_SLOT_SHIFT 13 /* LDO8_SLP_SLOT - [15:13] */ | |
1008 | #define WM831X_LDO8_SLP_SLOT_WIDTH 3 /* LDO8_SLP_SLOT - [15:13] */ | |
1009 | #define WM831X_LDO8_SLP_MODE 0x0100 /* LDO8_SLP_MODE */ | |
1010 | #define WM831X_LDO8_SLP_MODE_MASK 0x0100 /* LDO8_SLP_MODE */ | |
1011 | #define WM831X_LDO8_SLP_MODE_SHIFT 8 /* LDO8_SLP_MODE */ | |
1012 | #define WM831X_LDO8_SLP_MODE_WIDTH 1 /* LDO8_SLP_MODE */ | |
1013 | #define WM831X_LDO8_SLP_VSEL_MASK 0x001F /* LDO8_SLP_VSEL - [4:0] */ | |
1014 | #define WM831X_LDO8_SLP_VSEL_SHIFT 0 /* LDO8_SLP_VSEL - [4:0] */ | |
1015 | #define WM831X_LDO8_SLP_VSEL_WIDTH 5 /* LDO8_SLP_VSEL - [4:0] */ | |
1016 | ||
1017 | /* | |
1018 | * R16512 (0x4080) - LDO9 Control | |
1019 | */ | |
1020 | #define WM831X_LDO9_ERR_ACT_MASK 0xC000 /* LDO9_ERR_ACT - [15:14] */ | |
1021 | #define WM831X_LDO9_ERR_ACT_SHIFT 14 /* LDO9_ERR_ACT - [15:14] */ | |
1022 | #define WM831X_LDO9_ERR_ACT_WIDTH 2 /* LDO9_ERR_ACT - [15:14] */ | |
1023 | #define WM831X_LDO9_HWC_SRC_MASK 0x1800 /* LDO9_HWC_SRC - [12:11] */ | |
1024 | #define WM831X_LDO9_HWC_SRC_SHIFT 11 /* LDO9_HWC_SRC - [12:11] */ | |
1025 | #define WM831X_LDO9_HWC_SRC_WIDTH 2 /* LDO9_HWC_SRC - [12:11] */ | |
1026 | #define WM831X_LDO9_HWC_VSEL 0x0400 /* LDO9_HWC_VSEL */ | |
1027 | #define WM831X_LDO9_HWC_VSEL_MASK 0x0400 /* LDO9_HWC_VSEL */ | |
1028 | #define WM831X_LDO9_HWC_VSEL_SHIFT 10 /* LDO9_HWC_VSEL */ | |
1029 | #define WM831X_LDO9_HWC_VSEL_WIDTH 1 /* LDO9_HWC_VSEL */ | |
1030 | #define WM831X_LDO9_HWC_MODE_MASK 0x0300 /* LDO9_HWC_MODE - [9:8] */ | |
1031 | #define WM831X_LDO9_HWC_MODE_SHIFT 8 /* LDO9_HWC_MODE - [9:8] */ | |
1032 | #define WM831X_LDO9_HWC_MODE_WIDTH 2 /* LDO9_HWC_MODE - [9:8] */ | |
1033 | #define WM831X_LDO9_FLT 0x0080 /* LDO9_FLT */ | |
1034 | #define WM831X_LDO9_FLT_MASK 0x0080 /* LDO9_FLT */ | |
1035 | #define WM831X_LDO9_FLT_SHIFT 7 /* LDO9_FLT */ | |
1036 | #define WM831X_LDO9_FLT_WIDTH 1 /* LDO9_FLT */ | |
1037 | #define WM831X_LDO9_SWI 0x0040 /* LDO9_SWI */ | |
1038 | #define WM831X_LDO9_SWI_MASK 0x0040 /* LDO9_SWI */ | |
1039 | #define WM831X_LDO9_SWI_SHIFT 6 /* LDO9_SWI */ | |
1040 | #define WM831X_LDO9_SWI_WIDTH 1 /* LDO9_SWI */ | |
1041 | ||
1042 | /* | |
1043 | * R16513 (0x4081) - LDO9 ON Control | |
1044 | */ | |
1045 | #define WM831X_LDO9_ON_SLOT_MASK 0xE000 /* LDO9_ON_SLOT - [15:13] */ | |
1046 | #define WM831X_LDO9_ON_SLOT_SHIFT 13 /* LDO9_ON_SLOT - [15:13] */ | |
1047 | #define WM831X_LDO9_ON_SLOT_WIDTH 3 /* LDO9_ON_SLOT - [15:13] */ | |
1048 | #define WM831X_LDO9_ON_MODE 0x0100 /* LDO9_ON_MODE */ | |
1049 | #define WM831X_LDO9_ON_MODE_MASK 0x0100 /* LDO9_ON_MODE */ | |
1050 | #define WM831X_LDO9_ON_MODE_SHIFT 8 /* LDO9_ON_MODE */ | |
1051 | #define WM831X_LDO9_ON_MODE_WIDTH 1 /* LDO9_ON_MODE */ | |
1052 | #define WM831X_LDO9_ON_VSEL_MASK 0x001F /* LDO9_ON_VSEL - [4:0] */ | |
1053 | #define WM831X_LDO9_ON_VSEL_SHIFT 0 /* LDO9_ON_VSEL - [4:0] */ | |
1054 | #define WM831X_LDO9_ON_VSEL_WIDTH 5 /* LDO9_ON_VSEL - [4:0] */ | |
1055 | ||
1056 | /* | |
1057 | * R16514 (0x4082) - LDO9 SLEEP Control | |
1058 | */ | |
1059 | #define WM831X_LDO9_SLP_SLOT_MASK 0xE000 /* LDO9_SLP_SLOT - [15:13] */ | |
1060 | #define WM831X_LDO9_SLP_SLOT_SHIFT 13 /* LDO9_SLP_SLOT - [15:13] */ | |
1061 | #define WM831X_LDO9_SLP_SLOT_WIDTH 3 /* LDO9_SLP_SLOT - [15:13] */ | |
1062 | #define WM831X_LDO9_SLP_MODE 0x0100 /* LDO9_SLP_MODE */ | |
1063 | #define WM831X_LDO9_SLP_MODE_MASK 0x0100 /* LDO9_SLP_MODE */ | |
1064 | #define WM831X_LDO9_SLP_MODE_SHIFT 8 /* LDO9_SLP_MODE */ | |
1065 | #define WM831X_LDO9_SLP_MODE_WIDTH 1 /* LDO9_SLP_MODE */ | |
1066 | #define WM831X_LDO9_SLP_VSEL_MASK 0x001F /* LDO9_SLP_VSEL - [4:0] */ | |
1067 | #define WM831X_LDO9_SLP_VSEL_SHIFT 0 /* LDO9_SLP_VSEL - [4:0] */ | |
1068 | #define WM831X_LDO9_SLP_VSEL_WIDTH 5 /* LDO9_SLP_VSEL - [4:0] */ | |
1069 | ||
1070 | /* | |
1071 | * R16515 (0x4083) - LDO10 Control | |
1072 | */ | |
1073 | #define WM831X_LDO10_ERR_ACT_MASK 0xC000 /* LDO10_ERR_ACT - [15:14] */ | |
1074 | #define WM831X_LDO10_ERR_ACT_SHIFT 14 /* LDO10_ERR_ACT - [15:14] */ | |
1075 | #define WM831X_LDO10_ERR_ACT_WIDTH 2 /* LDO10_ERR_ACT - [15:14] */ | |
1076 | #define WM831X_LDO10_HWC_SRC_MASK 0x1800 /* LDO10_HWC_SRC - [12:11] */ | |
1077 | #define WM831X_LDO10_HWC_SRC_SHIFT 11 /* LDO10_HWC_SRC - [12:11] */ | |
1078 | #define WM831X_LDO10_HWC_SRC_WIDTH 2 /* LDO10_HWC_SRC - [12:11] */ | |
1079 | #define WM831X_LDO10_HWC_VSEL 0x0400 /* LDO10_HWC_VSEL */ | |
1080 | #define WM831X_LDO10_HWC_VSEL_MASK 0x0400 /* LDO10_HWC_VSEL */ | |
1081 | #define WM831X_LDO10_HWC_VSEL_SHIFT 10 /* LDO10_HWC_VSEL */ | |
1082 | #define WM831X_LDO10_HWC_VSEL_WIDTH 1 /* LDO10_HWC_VSEL */ | |
1083 | #define WM831X_LDO10_HWC_MODE_MASK 0x0300 /* LDO10_HWC_MODE - [9:8] */ | |
1084 | #define WM831X_LDO10_HWC_MODE_SHIFT 8 /* LDO10_HWC_MODE - [9:8] */ | |
1085 | #define WM831X_LDO10_HWC_MODE_WIDTH 2 /* LDO10_HWC_MODE - [9:8] */ | |
1086 | #define WM831X_LDO10_FLT 0x0080 /* LDO10_FLT */ | |
1087 | #define WM831X_LDO10_FLT_MASK 0x0080 /* LDO10_FLT */ | |
1088 | #define WM831X_LDO10_FLT_SHIFT 7 /* LDO10_FLT */ | |
1089 | #define WM831X_LDO10_FLT_WIDTH 1 /* LDO10_FLT */ | |
1090 | #define WM831X_LDO10_SWI 0x0040 /* LDO10_SWI */ | |
1091 | #define WM831X_LDO10_SWI_MASK 0x0040 /* LDO10_SWI */ | |
1092 | #define WM831X_LDO10_SWI_SHIFT 6 /* LDO10_SWI */ | |
1093 | #define WM831X_LDO10_SWI_WIDTH 1 /* LDO10_SWI */ | |
1094 | ||
1095 | /* | |
1096 | * R16516 (0x4084) - LDO10 ON Control | |
1097 | */ | |
1098 | #define WM831X_LDO10_ON_SLOT_MASK 0xE000 /* LDO10_ON_SLOT - [15:13] */ | |
1099 | #define WM831X_LDO10_ON_SLOT_SHIFT 13 /* LDO10_ON_SLOT - [15:13] */ | |
1100 | #define WM831X_LDO10_ON_SLOT_WIDTH 3 /* LDO10_ON_SLOT - [15:13] */ | |
1101 | #define WM831X_LDO10_ON_MODE 0x0100 /* LDO10_ON_MODE */ | |
1102 | #define WM831X_LDO10_ON_MODE_MASK 0x0100 /* LDO10_ON_MODE */ | |
1103 | #define WM831X_LDO10_ON_MODE_SHIFT 8 /* LDO10_ON_MODE */ | |
1104 | #define WM831X_LDO10_ON_MODE_WIDTH 1 /* LDO10_ON_MODE */ | |
1105 | #define WM831X_LDO10_ON_VSEL_MASK 0x001F /* LDO10_ON_VSEL - [4:0] */ | |
1106 | #define WM831X_LDO10_ON_VSEL_SHIFT 0 /* LDO10_ON_VSEL - [4:0] */ | |
1107 | #define WM831X_LDO10_ON_VSEL_WIDTH 5 /* LDO10_ON_VSEL - [4:0] */ | |
1108 | ||
1109 | /* | |
1110 | * R16517 (0x4085) - LDO10 SLEEP Control | |
1111 | */ | |
1112 | #define WM831X_LDO10_SLP_SLOT_MASK 0xE000 /* LDO10_SLP_SLOT - [15:13] */ | |
1113 | #define WM831X_LDO10_SLP_SLOT_SHIFT 13 /* LDO10_SLP_SLOT - [15:13] */ | |
1114 | #define WM831X_LDO10_SLP_SLOT_WIDTH 3 /* LDO10_SLP_SLOT - [15:13] */ | |
1115 | #define WM831X_LDO10_SLP_MODE 0x0100 /* LDO10_SLP_MODE */ | |
1116 | #define WM831X_LDO10_SLP_MODE_MASK 0x0100 /* LDO10_SLP_MODE */ | |
1117 | #define WM831X_LDO10_SLP_MODE_SHIFT 8 /* LDO10_SLP_MODE */ | |
1118 | #define WM831X_LDO10_SLP_MODE_WIDTH 1 /* LDO10_SLP_MODE */ | |
1119 | #define WM831X_LDO10_SLP_VSEL_MASK 0x001F /* LDO10_SLP_VSEL - [4:0] */ | |
1120 | #define WM831X_LDO10_SLP_VSEL_SHIFT 0 /* LDO10_SLP_VSEL - [4:0] */ | |
1121 | #define WM831X_LDO10_SLP_VSEL_WIDTH 5 /* LDO10_SLP_VSEL - [4:0] */ | |
1122 | ||
1123 | /* | |
1124 | * R16519 (0x4087) - LDO11 ON Control | |
1125 | */ | |
1126 | #define WM831X_LDO11_ON_SLOT_MASK 0xE000 /* LDO11_ON_SLOT - [15:13] */ | |
1127 | #define WM831X_LDO11_ON_SLOT_SHIFT 13 /* LDO11_ON_SLOT - [15:13] */ | |
1128 | #define WM831X_LDO11_ON_SLOT_WIDTH 3 /* LDO11_ON_SLOT - [15:13] */ | |
1129 | #define WM831X_LDO11_OFFENA 0x1000 /* LDO11_OFFENA */ | |
1130 | #define WM831X_LDO11_OFFENA_MASK 0x1000 /* LDO11_OFFENA */ | |
1131 | #define WM831X_LDO11_OFFENA_SHIFT 12 /* LDO11_OFFENA */ | |
1132 | #define WM831X_LDO11_OFFENA_WIDTH 1 /* LDO11_OFFENA */ | |
1133 | #define WM831X_LDO11_VSEL_SRC 0x0080 /* LDO11_VSEL_SRC */ | |
1134 | #define WM831X_LDO11_VSEL_SRC_MASK 0x0080 /* LDO11_VSEL_SRC */ | |
1135 | #define WM831X_LDO11_VSEL_SRC_SHIFT 7 /* LDO11_VSEL_SRC */ | |
1136 | #define WM831X_LDO11_VSEL_SRC_WIDTH 1 /* LDO11_VSEL_SRC */ | |
1137 | #define WM831X_LDO11_ON_VSEL_MASK 0x000F /* LDO11_ON_VSEL - [3:0] */ | |
1138 | #define WM831X_LDO11_ON_VSEL_SHIFT 0 /* LDO11_ON_VSEL - [3:0] */ | |
1139 | #define WM831X_LDO11_ON_VSEL_WIDTH 4 /* LDO11_ON_VSEL - [3:0] */ | |
1140 | ||
1141 | /* | |
1142 | * R16520 (0x4088) - LDO11 SLEEP Control | |
1143 | */ | |
1144 | #define WM831X_LDO11_SLP_SLOT_MASK 0xE000 /* LDO11_SLP_SLOT - [15:13] */ | |
1145 | #define WM831X_LDO11_SLP_SLOT_SHIFT 13 /* LDO11_SLP_SLOT - [15:13] */ | |
1146 | #define WM831X_LDO11_SLP_SLOT_WIDTH 3 /* LDO11_SLP_SLOT - [15:13] */ | |
1147 | #define WM831X_LDO11_SLP_VSEL_MASK 0x000F /* LDO11_SLP_VSEL - [3:0] */ | |
1148 | #define WM831X_LDO11_SLP_VSEL_SHIFT 0 /* LDO11_SLP_VSEL - [3:0] */ | |
1149 | #define WM831X_LDO11_SLP_VSEL_WIDTH 4 /* LDO11_SLP_VSEL - [3:0] */ | |
1150 | ||
e4ee831f MB |
1151 | /* |
1152 | * R16526 (0x408E) - Power Good Source 1 | |
1153 | */ | |
1154 | #define WM831X_DC4_OK 0x0008 /* DC4_OK */ | |
1155 | #define WM831X_DC4_OK_MASK 0x0008 /* DC4_OK */ | |
1156 | #define WM831X_DC4_OK_SHIFT 3 /* DC4_OK */ | |
1157 | #define WM831X_DC4_OK_WIDTH 1 /* DC4_OK */ | |
1158 | #define WM831X_DC3_OK 0x0004 /* DC3_OK */ | |
1159 | #define WM831X_DC3_OK_MASK 0x0004 /* DC3_OK */ | |
1160 | #define WM831X_DC3_OK_SHIFT 2 /* DC3_OK */ | |
1161 | #define WM831X_DC3_OK_WIDTH 1 /* DC3_OK */ | |
1162 | #define WM831X_DC2_OK 0x0002 /* DC2_OK */ | |
1163 | #define WM831X_DC2_OK_MASK 0x0002 /* DC2_OK */ | |
1164 | #define WM831X_DC2_OK_SHIFT 1 /* DC2_OK */ | |
1165 | #define WM831X_DC2_OK_WIDTH 1 /* DC2_OK */ | |
1166 | #define WM831X_DC1_OK 0x0001 /* DC1_OK */ | |
1167 | #define WM831X_DC1_OK_MASK 0x0001 /* DC1_OK */ | |
1168 | #define WM831X_DC1_OK_SHIFT 0 /* DC1_OK */ | |
1169 | #define WM831X_DC1_OK_WIDTH 1 /* DC1_OK */ | |
1170 | ||
d1c6b4fe MB |
1171 | /* |
1172 | * R16527 (0x408F) - Power Good Source 2 | |
1173 | */ | |
1174 | #define WM831X_LDO10_OK 0x0200 /* LDO10_OK */ | |
1175 | #define WM831X_LDO10_OK_MASK 0x0200 /* LDO10_OK */ | |
1176 | #define WM831X_LDO10_OK_SHIFT 9 /* LDO10_OK */ | |
1177 | #define WM831X_LDO10_OK_WIDTH 1 /* LDO10_OK */ | |
1178 | #define WM831X_LDO9_OK 0x0100 /* LDO9_OK */ | |
1179 | #define WM831X_LDO9_OK_MASK 0x0100 /* LDO9_OK */ | |
1180 | #define WM831X_LDO9_OK_SHIFT 8 /* LDO9_OK */ | |
1181 | #define WM831X_LDO9_OK_WIDTH 1 /* LDO9_OK */ | |
1182 | #define WM831X_LDO8_OK 0x0080 /* LDO8_OK */ | |
1183 | #define WM831X_LDO8_OK_MASK 0x0080 /* LDO8_OK */ | |
1184 | #define WM831X_LDO8_OK_SHIFT 7 /* LDO8_OK */ | |
1185 | #define WM831X_LDO8_OK_WIDTH 1 /* LDO8_OK */ | |
1186 | #define WM831X_LDO7_OK 0x0040 /* LDO7_OK */ | |
1187 | #define WM831X_LDO7_OK_MASK 0x0040 /* LDO7_OK */ | |
1188 | #define WM831X_LDO7_OK_SHIFT 6 /* LDO7_OK */ | |
1189 | #define WM831X_LDO7_OK_WIDTH 1 /* LDO7_OK */ | |
1190 | #define WM831X_LDO6_OK 0x0020 /* LDO6_OK */ | |
1191 | #define WM831X_LDO6_OK_MASK 0x0020 /* LDO6_OK */ | |
1192 | #define WM831X_LDO6_OK_SHIFT 5 /* LDO6_OK */ | |
1193 | #define WM831X_LDO6_OK_WIDTH 1 /* LDO6_OK */ | |
1194 | #define WM831X_LDO5_OK 0x0010 /* LDO5_OK */ | |
1195 | #define WM831X_LDO5_OK_MASK 0x0010 /* LDO5_OK */ | |
1196 | #define WM831X_LDO5_OK_SHIFT 4 /* LDO5_OK */ | |
1197 | #define WM831X_LDO5_OK_WIDTH 1 /* LDO5_OK */ | |
1198 | #define WM831X_LDO4_OK 0x0008 /* LDO4_OK */ | |
1199 | #define WM831X_LDO4_OK_MASK 0x0008 /* LDO4_OK */ | |
1200 | #define WM831X_LDO4_OK_SHIFT 3 /* LDO4_OK */ | |
1201 | #define WM831X_LDO4_OK_WIDTH 1 /* LDO4_OK */ | |
1202 | #define WM831X_LDO3_OK 0x0004 /* LDO3_OK */ | |
1203 | #define WM831X_LDO3_OK_MASK 0x0004 /* LDO3_OK */ | |
1204 | #define WM831X_LDO3_OK_SHIFT 2 /* LDO3_OK */ | |
1205 | #define WM831X_LDO3_OK_WIDTH 1 /* LDO3_OK */ | |
1206 | #define WM831X_LDO2_OK 0x0002 /* LDO2_OK */ | |
1207 | #define WM831X_LDO2_OK_MASK 0x0002 /* LDO2_OK */ | |
1208 | #define WM831X_LDO2_OK_SHIFT 1 /* LDO2_OK */ | |
1209 | #define WM831X_LDO2_OK_WIDTH 1 /* LDO2_OK */ | |
1210 | #define WM831X_LDO1_OK 0x0001 /* LDO1_OK */ | |
1211 | #define WM831X_LDO1_OK_MASK 0x0001 /* LDO1_OK */ | |
1212 | #define WM831X_LDO1_OK_SHIFT 0 /* LDO1_OK */ | |
1213 | #define WM831X_LDO1_OK_WIDTH 1 /* LDO1_OK */ | |
1214 | ||
7716977b MB |
1215 | #define WM831X_ISINK_MAX_ISEL 55 |
1216 | extern int wm831x_isinkv_values[WM831X_ISINK_MAX_ISEL + 1]; | |
698659d5 MB |
1217 | |
1218 | #endif |