Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/shli/md
[linux-2.6-block.git] / include / linux / mfd / tmio.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
f024ff10
DB
2#ifndef MFD_TMIO_H
3#define MFD_TMIO_H
4
c8be24c2 5#include <linux/device.h>
b53cde35 6#include <linux/fb.h>
64e8867b 7#include <linux/io.h>
c8be24c2 8#include <linux/jiffies.h>
bbf0208d 9#include <linux/mmc/card.h>
64e8867b 10#include <linux/platform_device.h>
7311bef0 11#include <linux/pm_runtime.h>
b53cde35 12
d3a2f718
IM
13#define tmio_ioread8(addr) readb(addr)
14#define tmio_ioread16(addr) readw(addr)
15#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
16#define tmio_ioread32(addr) \
f2218db8 17 (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
d3a2f718
IM
18
19#define tmio_iowrite8(val, addr) writeb((val), (addr))
20#define tmio_iowrite16(val, addr) writew((val), (addr))
21#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
22#define tmio_iowrite32(val, addr) \
23 do { \
f2218db8
SH
24 writew((val), (addr)); \
25 writew((val) >> 16, (addr) + 2); \
d3a2f718
IM
26 } while (0)
27
64e8867b
IM
28#define sd_config_write8(base, shift, reg, val) \
29 tmio_iowrite8((val), (base) + ((reg) << (shift)))
30#define sd_config_write16(base, shift, reg, val) \
31 tmio_iowrite16((val), (base) + ((reg) << (shift)))
32#define sd_config_write32(base, shift, reg, val) \
33 do { \
34 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
35 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
36 } while (0)
37
ac8fb3e8 38/* tmio MMC platform flags */
f2218db8 39#define TMIO_MMC_WRPROTECT_DISABLE BIT(0)
f1334fb3
YG
40/*
41 * Some controllers can support a 2-byte block size when the bus width
42 * is configured in 4-bit mode.
43 */
f2218db8 44#define TMIO_MMC_BLKSZ_2BYTES BIT(1)
845ecd20
AH
45/*
46 * Some controllers can support SDIO IRQ signalling.
47 */
f2218db8 48#define TMIO_MMC_SDIO_IRQ BIT(2)
04e24b80 49
d63c2bf4 50/* Some features are only available or tested on R-Car Gen2 or later */
f2218db8 51#define TMIO_MMC_MIN_RCAR2 BIT(3)
04e24b80 52
973ed3af
SH
53/*
54 * Some controllers require waiting for the SD bus to become
55 * idle before writing to some registers.
56 */
f2218db8 57#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
c8be24c2
GL
58/*
59 * A GPIO is used for card hotplug detection. We need an extra flag for this,
60 * because 0 is a valid GPIO number too, and requiring users to specify
61 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
62 */
f2218db8 63#define TMIO_MMC_USE_GPIO_CD BIT(5)
ac8fb3e8 64
5d60e500
KM
65/*
66 * Some controllers doesn't have over 0x100 register.
67 * it is used to checking accessibility of
68 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
69 */
f2218db8 70#define TMIO_MMC_HAVE_HIGH_REG BIT(6)
5d60e500 71
b8d11962
SU
72/*
73 * Some controllers have CMD12 automatically
74 * issue/non-issue register
75 */
f2218db8 76#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
b8d11962 77
20dd0373 78/* Controller has some SDIO status bits which must be 1 */
f2218db8 79#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
6b98757e 80
8185e51f
CB
81/*
82 * Some controllers have a 32-bit wide data port register
83 */
f2218db8 84#define TMIO_MMC_32BIT_DATA_PORT BIT(9)
8185e51f 85
da29fe2b
SU
86/*
87 * Some controllers allows to set SDx actual clock
88 */
f2218db8 89#define TMIO_MMC_CLK_ACTUAL BIT(10)
da29fe2b 90
5124b592
WS
91/* Some controllers have a CBSY bit */
92#define TMIO_MMC_HAVE_CBSY BIT(11)
93
64e8867b
IM
94int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
95int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
96void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
97void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
98
03a0675b
GL
99struct dma_chan;
100
f0e46cc4
PZ
101/*
102 * data for the MMC controller
103 */
104struct tmio_mmc_data {
f33c9d65
KM
105 void *chan_priv_tx;
106 void *chan_priv_rx;
707f0b2f 107 unsigned int hclk;
b741d440 108 unsigned long capabilities;
02cb3221 109 unsigned long capabilities2;
ac8fb3e8 110 unsigned long flags;
a2b14dc9 111 u32 ocr_mask; /* available voltages */
c8be24c2 112 unsigned int cd_gpio;
e471df0b 113 int alignment_shift;
8b4c8f32 114 dma_addr_t dma_rx_offset;
603aa14d
YS
115 unsigned int max_blk_count;
116 unsigned short max_segs;
9d731e75 117 void (*set_pwr)(struct platform_device *host, int state);
64e8867b 118 void (*set_clk_div)(struct platform_device *host, int state);
f0e46cc4
PZ
119};
120
f024ff10
DB
121/*
122 * data for the NAND controller
123 */
124struct tmio_nand_data {
125 struct nand_bbt_descr *badblock_pattern;
126 struct mtd_partition *partition;
127 unsigned int num_partitions;
827dba9d 128 const char *const *part_parsers;
f024ff10
DB
129};
130
b53cde35
DB
131#define FBIO_TMIO_ACC_WRITE 0x7C639300
132#define FBIO_TMIO_ACC_SYNC 0x7C639301
133
134struct tmio_fb_data {
135 int (*lcd_set_power)(struct platform_device *fb_dev,
f2218db8 136 bool on);
b53cde35 137 int (*lcd_mode)(struct platform_device *fb_dev,
f2218db8 138 const struct fb_videomode *mode);
b53cde35
DB
139 int num_modes;
140 struct fb_videomode *modes;
141
142 /* in mm: size of screen */
143 int height;
144 int width;
145};
146
f024ff10 147#endif