[linux-2.6-block.git] / include / linux / mfd / ti_am335x_tscadc.h

#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
#define __LINUX_TI_AM335X_TSCADC_MFD_H

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/mfd/core.h>

#define REG_RAWIRQSTATUS	0x024
#define REG_IRQSTATUS		0x028
#define REG_IRQENABLE		0x02C
#define REG_IRQCLR		0x030
#define REG_IRQWAKEUP		0x034
#define REG_DMAENABLE_SET	0x038
#define REG_DMAENABLE_CLEAR	0x03c
#define REG_CTRL		0x040
#define REG_ADCFSM		0x044
#define REG_CLKDIV		0x04C
#define REG_SE			0x054
#define REG_IDLECONFIG		0x058
#define REG_CHARGECONFIG	0x05C
#define REG_CHARGEDELAY		0x060
#define REG_STEPCONFIG(n)	(0x64 + ((n) * 8))
#define REG_STEPDELAY(n)	(0x68 + ((n) * 8))
#define REG_FIFO0CNT		0xE4
#define REG_FIFO0THR		0xE8
#define REG_FIFO1CNT		0xF0
#define REG_FIFO1THR		0xF4
#define REG_DMA1REQ		0xF8
#define REG_FIFO0		0x100
#define REG_FIFO1		0x200

/*	Register Bitfields	*/
/* IRQ wakeup enable */
#define IRQWKUP_ENB		BIT(0)

/* Step Enable */
#define STEPENB_MASK		(0x1FFFF << 0)
#define STEPENB(val)		((val) << 0)
#define ENB(val)			(1 << (val))
#define STPENB_STEPENB		STEPENB(0x1FFFF)
#define STPENB_STEPENB_TC	STEPENB(0x1FFF)

/* IRQ enable */
#define IRQENB_HW_PEN		BIT(0)
#define IRQENB_EOS		BIT(1)
#define IRQENB_FIFO0THRES	BIT(2)
#define IRQENB_FIFO0OVRRUN	BIT(3)
#define IRQENB_FIFO0UNDRFLW	BIT(4)
#define IRQENB_FIFO1THRES	BIT(5)
#define IRQENB_FIFO1OVRRUN	BIT(6)
#define IRQENB_FIFO1UNDRFLW	BIT(7)
#define IRQENB_PENUP		BIT(9)

/* Step Configuration */
#define STEPCONFIG_MODE_MASK	(3 << 0)
#define STEPCONFIG_MODE(val)	((val) << 0)
#define STEPCONFIG_MODE_SWCNT	STEPCONFIG_MODE(1)
#define STEPCONFIG_MODE_HWSYNC	STEPCONFIG_MODE(2)
#define STEPCONFIG_AVG_MASK	(7 << 2)
#define STEPCONFIG_AVG(val)	((val) << 2)
#define STEPCONFIG_AVG_16	STEPCONFIG_AVG(4)
#define STEPCONFIG_XPP		BIT(5)
#define STEPCONFIG_XNN		BIT(6)
#define STEPCONFIG_YPP		BIT(7)
#define STEPCONFIG_YNN		BIT(8)
#define STEPCONFIG_XNP		BIT(9)
#define STEPCONFIG_YPN		BIT(10)
#define STEPCONFIG_RFP(val)	((val) << 12)
#define STEPCONFIG_RFP_VREFP	(0x3 << 12)
#define STEPCONFIG_INM_MASK	(0xF << 15)
#define STEPCONFIG_INM(val)	((val) << 15)
#define STEPCONFIG_INM_ADCREFM	STEPCONFIG_INM(8)
#define STEPCONFIG_INP_MASK	(0xF << 19)
#define STEPCONFIG_INP(val)	((val) << 19)
#define STEPCONFIG_INP_AN4	STEPCONFIG_INP(4)
#define STEPCONFIG_INP_ADCREFM	STEPCONFIG_INP(8)
#define STEPCONFIG_FIFO1	BIT(26)
#define STEPCONFIG_RFM(val)	((val) << 23)
#define STEPCONFIG_RFM_VREFN	(0x3 << 23)

/* Delay register */
#define STEPDELAY_OPEN_MASK	(0x3FFFF << 0)
#define STEPDELAY_OPEN(val)	((val) << 0)
#define STEPCONFIG_OPENDLY	STEPDELAY_OPEN(0x098)
#define STEPDELAY_SAMPLE_MASK	(0xFF << 24)
#define STEPDELAY_SAMPLE(val)	((val) << 24)
#define STEPCONFIG_SAMPLEDLY	STEPDELAY_SAMPLE(0)

/* Charge Config */
#define STEPCHARGE_RFP_MASK	(7 << 12)
#define STEPCHARGE_RFP(val)	((val) << 12)
#define STEPCHARGE_RFP_XPUL	STEPCHARGE_RFP(1)
#define STEPCHARGE_INM_MASK	(0xF << 15)
#define STEPCHARGE_INM(val)	((val) << 15)
#define STEPCHARGE_INM_AN1	STEPCHARGE_INM(1)
#define STEPCHARGE_INP_MASK	(0xF << 19)
#define STEPCHARGE_INP(val)	((val) << 19)
#define STEPCHARGE_RFM_MASK	(3 << 23)
#define STEPCHARGE_RFM(val)	((val) << 23)
#define STEPCHARGE_RFM_XNUR	STEPCHARGE_RFM(1)

/* Charge delay */
#define CHARGEDLY_OPEN_MASK	(0x3FFFF << 0)
#define CHARGEDLY_OPEN(val)	((val) << 0)
#define CHARGEDLY_OPENDLY	CHARGEDLY_OPEN(0x400)

/* Control register */
#define CNTRLREG_TSCSSENB	BIT(0)
#define CNTRLREG_STEPID		BIT(1)
#define CNTRLREG_STEPCONFIGWRT	BIT(2)
#define CNTRLREG_POWERDOWN	BIT(4)
#define CNTRLREG_AFE_CTRL_MASK	(3 << 5)
#define CNTRLREG_AFE_CTRL(val)	((val) << 5)
#define CNTRLREG_4WIRE		CNTRLREG_AFE_CTRL(1)
#define CNTRLREG_5WIRE		CNTRLREG_AFE_CTRL(2)
#define CNTRLREG_8WIRE		CNTRLREG_AFE_CTRL(3)
#define CNTRLREG_TSCENB		BIT(7)

/* FIFO READ Register */
#define FIFOREAD_DATA_MASK (0xfff << 0)
#define FIFOREAD_CHNLID_MASK (0xf << 16)

/* DMA ENABLE/CLEAR Register */
#define DMA_FIFO0		BIT(0)
#define DMA_FIFO1		BIT(1)

/* Sequencer Status */
#define SEQ_STATUS BIT(5)
#define CHARGE_STEP		0x11

#define ADC_CLK			3000000
#define TOTAL_STEPS		16
#define TOTAL_CHANNELS		8
#define FIFO1_THRESHOLD		19

/*
 * time in us for processing a single channel, calculated as follows:
 *
 * max num cycles = open delay + (sample delay + conv time) * averaging
 *
 * max num cycles: 262143 + (255 + 13) * 16 = 266431
 *
 * clock frequency: 26MHz / 8 = 3.25MHz
 * clock period: 1 / 3.25MHz = 308ns
 *
 * max processing time: 266431 * 308ns = 83ms(approx)
 */
#define IDLE_TIMEOUT 83 /* milliseconds */

#define TSCADC_CELLS		2

struct ti_tscadc_dev {
	struct device *dev;
	struct regmap *regmap;
	void __iomem *tscadc_base;
	phys_addr_t tscadc_phys_base;
	int irq;
	int used_cells;	/* 1-2 */
	int tsc_wires;
	int tsc_cell;	/* -1 if not used */
	int adc_cell;	/* -1 if not used */
	struct mfd_cell cells[TSCADC_CELLS];
	u32 reg_se_cache;
	bool adc_waiting;
	bool adc_in_use;
	wait_queue_head_t reg_se_wait;
	spinlock_t reg_lock;
	unsigned int clk_div;

	/* tsc device */
	struct titsc *tsc;

	/* adc device */
	struct adc_device *adc;
};

static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
{
	struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;

	return *tscadc_dev;
}

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);

#endif
Commit	Line	Data
01636eb9 PR	1	#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
	2	#define __LINUX_TI_AM335X_TSCADC_MFD_H
	3
	4	/*
	5	* TI Touch Screen / ADC MFD driver
	6	*
4f4ed454	7	* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
01636eb9 PR	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation version 2.
	12	*
	13	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	14	* kind, whether express or implied; without even the implied warranty
	15	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/mfd/core.h>
	20
	21	#define REG_RAWIRQSTATUS 0x024
	22	#define REG_IRQSTATUS 0x028
	23	#define REG_IRQENABLE 0x02C
	24	#define REG_IRQCLR 0x030
	25	#define REG_IRQWAKEUP 0x034
f438b9da M	26	#define REG_DMAENABLE_SET 0x038
f438b9da M	27	#define REG_DMAENABLE_CLEAR 0x03c
01636eb9 PR	28	#define REG_CTRL 0x040
	29	#define REG_ADCFSM 0x044
	30	#define REG_CLKDIV 0x04C
	31	#define REG_SE 0x054
	32	#define REG_IDLECONFIG 0x058
	33	#define REG_CHARGECONFIG 0x05C
	34	#define REG_CHARGEDELAY 0x060
8c896308 SAS	35	#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
8c896308 SAS	36	#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
01636eb9 PR	37	#define REG_FIFO0CNT 0xE4
	38	#define REG_FIFO0THR 0xE8
	39	#define REG_FIFO1CNT 0xF0
	40	#define REG_FIFO1THR 0xF4
f438b9da	41	#define REG_DMA1REQ 0xF8
01636eb9 PR	42	#define REG_FIFO0 0x100
	43	#define REG_FIFO1 0x200
	44
	45	/* Register Bitfields */
	46	/* IRQ wakeup enable */
	47	#define IRQWKUP_ENB BIT(0)
	48
	49	/* Step Enable */
	50	#define STEPENB_MASK (0x1FFFF << 0)
	51	#define STEPENB(val) ((val) << 0)
ca9a5638 ZL	52	#define ENB(val) (1 << (val))
	53	#define STPENB_STEPENB STEPENB(0x1FFFF)
	54	#define STPENB_STEPENB_TC STEPENB(0x1FFF)
01636eb9 PR	55
	56	/* IRQ enable */
	57	#define IRQENB_HW_PEN BIT(0)
344d635b	58	#define IRQENB_EOS BIT(1)
01636eb9	59	#define IRQENB_FIFO0THRES BIT(2)
ca9a5638 ZL	60	#define IRQENB_FIFO0OVRRUN BIT(3)
ca9a5638 ZL	61	#define IRQENB_FIFO0UNDRFLW BIT(4)
01636eb9	62	#define IRQENB_FIFO1THRES BIT(5)
ca9a5638 ZL	63	#define IRQENB_FIFO1OVRRUN BIT(6)
ca9a5638 ZL	64	#define IRQENB_FIFO1UNDRFLW BIT(7)
01636eb9 PR	65	#define IRQENB_PENUP BIT(9)
	66
	67	/* Step Configuration */
	68	#define STEPCONFIG_MODE_MASK (3 << 0)
	69	#define STEPCONFIG_MODE(val) ((val) << 0)
ca9a5638	70	#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
01636eb9 PR	71	#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
	72	#define STEPCONFIG_AVG_MASK (7 << 2)
	73	#define STEPCONFIG_AVG(val) ((val) << 2)
	74	#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
	75	#define STEPCONFIG_XPP BIT(5)
	76	#define STEPCONFIG_XNN BIT(6)
	77	#define STEPCONFIG_YPP BIT(7)
	78	#define STEPCONFIG_YNN BIT(8)
	79	#define STEPCONFIG_XNP BIT(9)
	80	#define STEPCONFIG_YPN BIT(10)
4b3ab937 V	81	#define STEPCONFIG_RFP(val) ((val) << 12)
4b3ab937 V	82	#define STEPCONFIG_RFP_VREFP (0x3 << 12)
01636eb9 PR	83	#define STEPCONFIG_INM_MASK (0xF << 15)
	84	#define STEPCONFIG_INM(val) ((val) << 15)
	85	#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
	86	#define STEPCONFIG_INP_MASK (0xF << 19)
	87	#define STEPCONFIG_INP(val) ((val) << 19)
01636eb9 PR	88	#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
	89	#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
	90	#define STEPCONFIG_FIFO1 BIT(26)
4b3ab937 V	91	#define STEPCONFIG_RFM(val) ((val) << 23)
4b3ab937 V	92	#define STEPCONFIG_RFM_VREFN (0x3 << 23)
01636eb9 PR	93
	94	/* Delay register */
	95	#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
	96	#define STEPDELAY_OPEN(val) ((val) << 0)
	97	#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
	98	#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
	99	#define STEPDELAY_SAMPLE(val) ((val) << 24)
	100	#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
	101
	102	/* Charge Config */
	103	#define STEPCHARGE_RFP_MASK (7 << 12)
	104	#define STEPCHARGE_RFP(val) ((val) << 12)
	105	#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
	106	#define STEPCHARGE_INM_MASK (0xF << 15)
	107	#define STEPCHARGE_INM(val) ((val) << 15)
	108	#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
	109	#define STEPCHARGE_INP_MASK (0xF << 19)
	110	#define STEPCHARGE_INP(val) ((val) << 19)
01636eb9 PR	111	#define STEPCHARGE_RFM_MASK (3 << 23)
	112	#define STEPCHARGE_RFM(val) ((val) << 23)
	113	#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
	114
	115	/* Charge delay */
	116	#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
	117	#define CHARGEDLY_OPEN(val) ((val) << 0)
344d635b	118	#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
01636eb9 PR	119
	120	/* Control register */
	121	#define CNTRLREG_TSCSSENB BIT(0)
	122	#define CNTRLREG_STEPID BIT(1)
	123	#define CNTRLREG_STEPCONFIGWRT BIT(2)
	124	#define CNTRLREG_POWERDOWN BIT(4)
	125	#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
	126	#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
	127	#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
	128	#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
	129	#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
	130	#define CNTRLREG_TSCENB BIT(7)
	131
b1451e54 PR	132	/* FIFO READ Register */
	133	#define FIFOREAD_DATA_MASK (0xfff << 0)
	134	#define FIFOREAD_CHNLID_MASK (0xf << 16)
	135
f438b9da M	136	/* DMA ENABLE/CLEAR Register */
	137	#define DMA_FIFO0 BIT(0)
	138	#define DMA_FIFO1 BIT(1)
	139
b1451e54 PR	140	/* Sequencer Status */
b1451e54 PR	141	#define SEQ_STATUS BIT(5)
b10848e6	142	#define CHARGE_STEP 0x11
b1451e54	143
01636eb9	144	#define ADC_CLK 3000000
5e53a69b PR	145	#define TOTAL_STEPS 16
5e53a69b PR	146	#define TOTAL_CHANNELS 8
ca9a5638	147	#define FIFO1_THRESHOLD 19
01636eb9	148
b1451e54	149	/*
1a54b7da MK	150	* time in us for processing a single channel, calculated as follows:
1a54b7da MK	151	*
7175cce1	152	* max num cycles = open delay + (sample delay + conv time) * averaging
1a54b7da	153	*
7175cce1	154	* max num cycles: 262143 + (255 + 13) * 16 = 266431
1a54b7da MK	155	*
	156	* clock frequency: 26MHz / 8 = 3.25MHz
	157	* clock period: 1 / 3.25MHz = 308ns
	158	*
7175cce1	159	* max processing time: 266431 * 308ns = 83ms(approx)
1a54b7da	160	*/
7175cce1	161	#define IDLE_TIMEOUT 83 /* milliseconds */
b1451e54	162
5e53a69b	163	#define TSCADC_CELLS 2
2b99bafa	164
01636eb9 PR	165	struct ti_tscadc_dev {
01636eb9 PR	166	struct device *dev;
0d3a7cce	167	struct regmap *regmap;
01636eb9	168	void __iomem *tscadc_base;
c9329d86	169	phys_addr_t tscadc_phys_base;
01636eb9	170	int irq;
24d5c82f	171	int used_cells; /* 1-2 */
f0933a60	172	int tsc_wires;
24d5c82f PA	173	int tsc_cell; /* -1 if not used */
24d5c82f PA	174	int adc_cell; /* -1 if not used */
01636eb9	175	struct mfd_cell cells[TSCADC_CELLS];
abeccee4	176	u32 reg_se_cache;
7ca6740c SAS	177	bool adc_waiting;
	178	bool adc_in_use;
	179	wait_queue_head_t reg_se_wait;
abeccee4	180	spinlock_t reg_lock;
e90f8754	181	unsigned int clk_div;
2b99bafa PR	182
	183	/* tsc device */
	184	struct titsc *tsc;
5e53a69b PR	185
	186	/* adc device */
	187	struct adc_device *adc;
01636eb9 PR	188	};
01636eb9 PR	189
a9bce1b0 SAS	190	static inline struct ti_tscadc_dev ti_tscadc_dev_get(struct platform_device p)
	191	{
	192	struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
	193
	194	return *tscadc_dev;
	195	}
	196
7e170c6e SAS	197	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
7e170c6e SAS	198	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
abeccee4	199	void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
7ca6740c	200	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
abeccee4	201
01636eb9	202	#endif