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d5aa11bf MK |
1 | /* |
2 | * TI LMU (Lighting Management Unit) Device Register Map | |
3 | * | |
4 | * Copyright 2017 Texas Instruments | |
5 | * | |
6 | * Author: Milo Kim <milo.kim@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __MFD_TI_LMU_REGISTER_H__ | |
14 | #define __MFD_TI_LMU_REGISTER_H__ | |
15 | ||
16 | #include <linux/bitops.h> | |
17 | ||
18 | /* LM3532 */ | |
19 | #define LM3532_REG_OUTPUT_CFG 0x10 | |
20 | #define LM3532_ILED1_CFG_MASK 0x03 | |
21 | #define LM3532_ILED2_CFG_MASK 0x0C | |
22 | #define LM3532_ILED3_CFG_MASK 0x30 | |
23 | #define LM3532_ILED1_CFG_SHIFT 0 | |
24 | #define LM3532_ILED2_CFG_SHIFT 2 | |
25 | #define LM3532_ILED3_CFG_SHIFT 4 | |
26 | ||
27 | #define LM3532_REG_RAMPUP 0x12 | |
28 | #define LM3532_REG_RAMPDN LM3532_REG_RAMPUP | |
29 | #define LM3532_RAMPUP_MASK 0x07 | |
30 | #define LM3532_RAMPUP_SHIFT 0 | |
31 | #define LM3532_RAMPDN_MASK 0x38 | |
32 | #define LM3532_RAMPDN_SHIFT 3 | |
33 | ||
34 | #define LM3532_REG_ENABLE 0x1D | |
35 | ||
36 | #define LM3532_REG_PWM_A_CFG 0x13 | |
37 | #define LM3532_PWM_A_MASK 0x05 /* zone 0 */ | |
38 | #define LM3532_PWM_ZONE_0 BIT(2) | |
39 | ||
40 | #define LM3532_REG_PWM_B_CFG 0x14 | |
41 | #define LM3532_PWM_B_MASK 0x09 /* zone 1 */ | |
42 | #define LM3532_PWM_ZONE_1 BIT(3) | |
43 | ||
44 | #define LM3532_REG_PWM_C_CFG 0x15 | |
45 | #define LM3532_PWM_C_MASK 0x11 /* zone 2 */ | |
46 | #define LM3532_PWM_ZONE_2 BIT(4) | |
47 | ||
48 | #define LM3532_REG_ZONE_CFG_A 0x16 | |
49 | #define LM3532_REG_ZONE_CFG_B 0x18 | |
50 | #define LM3532_REG_ZONE_CFG_C 0x1A | |
51 | #define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4)) | |
52 | #define LM3532_ZONE_0 0 | |
53 | #define LM3532_ZONE_1 BIT(2) | |
54 | #define LM3532_ZONE_2 BIT(3) | |
55 | ||
56 | #define LM3532_REG_BRT_A 0x70 /* zone 0 */ | |
57 | #define LM3532_REG_BRT_B 0x76 /* zone 1 */ | |
58 | #define LM3532_REG_BRT_C 0x7C /* zone 2 */ | |
59 | ||
60 | #define LM3532_MAX_REG 0x7E | |
61 | ||
62 | /* LM3631 */ | |
63 | #define LM3631_REG_DEVCTRL 0x00 | |
64 | #define LM3631_LCD_EN_MASK BIT(1) | |
65 | #define LM3631_BL_EN_MASK BIT(0) | |
66 | ||
67 | #define LM3631_REG_BRT_LSB 0x01 | |
68 | #define LM3631_REG_BRT_MSB 0x02 | |
69 | ||
70 | #define LM3631_REG_BL_CFG 0x06 | |
71 | #define LM3631_BL_CHANNEL_MASK BIT(3) | |
72 | #define LM3631_BL_DUAL_CHANNEL 0 | |
73 | #define LM3631_BL_SINGLE_CHANNEL BIT(3) | |
74 | #define LM3631_MAP_MASK BIT(5) | |
75 | #define LM3631_EXPONENTIAL_MAP 0 | |
76 | ||
77 | #define LM3631_REG_BRT_MODE 0x08 | |
78 | #define LM3631_MODE_MASK (BIT(1) | BIT(2) | BIT(3)) | |
79 | #define LM3631_DEFAULT_MODE (BIT(1) | BIT(3)) | |
80 | ||
81 | #define LM3631_REG_SLOPE 0x09 | |
82 | #define LM3631_SLOPE_MASK 0xF0 | |
83 | #define LM3631_SLOPE_SHIFT 4 | |
84 | ||
85 | #define LM3631_REG_LDO_CTRL1 0x0A | |
86 | #define LM3631_EN_OREF_MASK BIT(0) | |
87 | #define LM3631_EN_VNEG_MASK BIT(1) | |
88 | #define LM3631_EN_VPOS_MASK BIT(2) | |
89 | ||
90 | #define LM3631_REG_LDO_CTRL2 0x0B | |
91 | #define LM3631_EN_CONT_MASK BIT(0) | |
92 | ||
93 | #define LM3631_REG_VOUT_CONT 0x0C | |
94 | #define LM3631_VOUT_CONT_MASK (BIT(6) | BIT(7)) | |
95 | ||
96 | #define LM3631_REG_VOUT_BOOST 0x0C | |
97 | #define LM3631_REG_VOUT_POS 0x0D | |
98 | #define LM3631_REG_VOUT_NEG 0x0E | |
99 | #define LM3631_REG_VOUT_OREF 0x0F | |
100 | #define LM3631_VOUT_MASK 0x3F | |
101 | ||
102 | #define LM3631_REG_ENTIME_VCONT 0x0B | |
103 | #define LM3631_ENTIME_CONT_MASK 0x70 | |
104 | ||
105 | #define LM3631_REG_ENTIME_VOREF 0x0F | |
106 | #define LM3631_REG_ENTIME_VPOS 0x10 | |
107 | #define LM3631_REG_ENTIME_VNEG 0x11 | |
108 | #define LM3631_ENTIME_MASK 0xF0 | |
109 | #define LM3631_ENTIME_SHIFT 4 | |
110 | ||
111 | #define LM3631_MAX_REG 0x16 | |
112 | ||
113 | /* LM3632 */ | |
114 | #define LM3632_REG_CONFIG1 0x02 | |
115 | #define LM3632_OVP_MASK (BIT(5) | BIT(6) | BIT(7)) | |
116 | #define LM3632_OVP_25V BIT(6) | |
117 | ||
118 | #define LM3632_REG_CONFIG2 0x03 | |
119 | #define LM3632_SWFREQ_MASK BIT(7) | |
120 | #define LM3632_SWFREQ_1MHZ BIT(7) | |
121 | ||
122 | #define LM3632_REG_BRT_LSB 0x04 | |
123 | #define LM3632_REG_BRT_MSB 0x05 | |
124 | ||
125 | #define LM3632_REG_IO_CTRL 0x09 | |
126 | #define LM3632_PWM_MASK BIT(6) | |
127 | #define LM3632_I2C_MODE 0 | |
128 | #define LM3632_PWM_MODE BIT(6) | |
129 | ||
130 | #define LM3632_REG_ENABLE 0x0A | |
131 | #define LM3632_BL_EN_MASK BIT(0) | |
132 | #define LM3632_BL_CHANNEL_MASK (BIT(3) | BIT(4)) | |
133 | #define LM3632_BL_SINGLE_CHANNEL BIT(4) | |
134 | #define LM3632_BL_DUAL_CHANNEL BIT(3) | |
135 | ||
136 | #define LM3632_REG_BIAS_CONFIG 0x0C | |
137 | #define LM3632_EXT_EN_MASK BIT(0) | |
138 | #define LM3632_EN_VNEG_MASK BIT(1) | |
139 | #define LM3632_EN_VPOS_MASK BIT(2) | |
140 | ||
141 | #define LM3632_REG_VOUT_BOOST 0x0D | |
142 | #define LM3632_REG_VOUT_POS 0x0E | |
143 | #define LM3632_REG_VOUT_NEG 0x0F | |
144 | #define LM3632_VOUT_MASK 0x3F | |
145 | ||
146 | #define LM3632_MAX_REG 0x10 | |
147 | ||
148 | /* LM3633 */ | |
149 | #define LM3633_REG_HVLED_OUTPUT_CFG 0x10 | |
150 | #define LM3633_HVLED1_CFG_MASK BIT(0) | |
151 | #define LM3633_HVLED2_CFG_MASK BIT(1) | |
152 | #define LM3633_HVLED3_CFG_MASK BIT(2) | |
153 | #define LM3633_HVLED1_CFG_SHIFT 0 | |
154 | #define LM3633_HVLED2_CFG_SHIFT 1 | |
155 | #define LM3633_HVLED3_CFG_SHIFT 2 | |
156 | ||
157 | #define LM3633_REG_BANK_SEL 0x11 | |
158 | ||
159 | #define LM3633_REG_BL0_RAMP 0x12 | |
160 | #define LM3633_REG_BL1_RAMP 0x13 | |
161 | #define LM3633_BL_RAMPUP_MASK 0xF0 | |
162 | #define LM3633_BL_RAMPUP_SHIFT 4 | |
163 | #define LM3633_BL_RAMPDN_MASK 0x0F | |
164 | #define LM3633_BL_RAMPDN_SHIFT 0 | |
165 | ||
166 | #define LM3633_REG_BL_RAMP_CONF 0x1B | |
167 | #define LM3633_BL_RAMP_MASK 0x0F | |
168 | #define LM3633_BL_RAMP_EACH 0x05 | |
169 | ||
170 | #define LM3633_REG_PTN0_RAMP 0x1C | |
171 | #define LM3633_REG_PTN1_RAMP 0x1D | |
172 | #define LM3633_PTN_RAMPUP_MASK 0x70 | |
173 | #define LM3633_PTN_RAMPUP_SHIFT 4 | |
174 | #define LM3633_PTN_RAMPDN_MASK 0x07 | |
175 | #define LM3633_PTN_RAMPDN_SHIFT 0 | |
176 | ||
177 | #define LM3633_REG_LED_MAPPING_MODE 0x1F | |
178 | #define LM3633_LED_EXPONENTIAL BIT(1) | |
179 | ||
180 | #define LM3633_REG_IMAX_HVLED_A 0x20 | |
181 | #define LM3633_REG_IMAX_HVLED_B 0x21 | |
182 | #define LM3633_REG_IMAX_LVLED_BASE 0x22 | |
183 | ||
184 | #define LM3633_REG_BL_FEEDBACK_ENABLE 0x28 | |
185 | ||
186 | #define LM3633_REG_ENABLE 0x2B | |
187 | #define LM3633_LED_BANK_OFFSET 2 | |
188 | ||
189 | #define LM3633_REG_PATTERN 0x2C | |
190 | ||
191 | #define LM3633_REG_BOOST_CFG 0x2D | |
192 | #define LM3633_OVP_MASK (BIT(1) | BIT(2)) | |
193 | #define LM3633_OVP_40V 0x6 | |
194 | ||
195 | #define LM3633_REG_PWM_CFG 0x2F | |
196 | #define LM3633_PWM_A_MASK BIT(0) | |
197 | #define LM3633_PWM_B_MASK BIT(1) | |
198 | ||
199 | #define LM3633_REG_BRT_HVLED_A_LSB 0x40 | |
200 | #define LM3633_REG_BRT_HVLED_A_MSB 0x41 | |
201 | #define LM3633_REG_BRT_HVLED_B_LSB 0x42 | |
202 | #define LM3633_REG_BRT_HVLED_B_MSB 0x43 | |
203 | ||
204 | #define LM3633_REG_BRT_LVLED_BASE 0x44 | |
205 | ||
206 | #define LM3633_REG_PTN_DELAY 0x50 | |
207 | ||
208 | #define LM3633_REG_PTN_LOWTIME 0x51 | |
209 | ||
210 | #define LM3633_REG_PTN_HIGHTIME 0x52 | |
211 | ||
212 | #define LM3633_REG_PTN_LOWBRT 0x53 | |
213 | ||
214 | #define LM3633_REG_PTN_HIGHBRT LM3633_REG_BRT_LVLED_BASE | |
215 | ||
216 | #define LM3633_REG_BL_OPEN_FAULT_STATUS 0xB0 | |
217 | ||
218 | #define LM3633_REG_BL_SHORT_FAULT_STATUS 0xB2 | |
219 | ||
220 | #define LM3633_REG_MONITOR_ENABLE 0xB4 | |
221 | ||
222 | #define LM3633_MAX_REG 0xB4 | |
223 | ||
224 | /* LM3695 */ | |
225 | #define LM3695_REG_GP 0x10 | |
226 | #define LM3695_BL_CHANNEL_MASK BIT(3) | |
227 | #define LM3695_BL_DUAL_CHANNEL 0 | |
228 | #define LM3695_BL_SINGLE_CHANNEL BIT(3) | |
229 | #define LM3695_BRT_RW_MASK BIT(2) | |
230 | #define LM3695_BL_EN_MASK BIT(0) | |
231 | ||
232 | #define LM3695_REG_BRT_LSB 0x13 | |
233 | #define LM3695_REG_BRT_MSB 0x14 | |
234 | ||
235 | #define LM3695_MAX_REG 0x14 | |
236 | ||
237 | /* LM3697 */ | |
238 | #define LM3697_REG_HVLED_OUTPUT_CFG 0x10 | |
239 | #define LM3697_HVLED1_CFG_MASK BIT(0) | |
240 | #define LM3697_HVLED2_CFG_MASK BIT(1) | |
241 | #define LM3697_HVLED3_CFG_MASK BIT(2) | |
242 | #define LM3697_HVLED1_CFG_SHIFT 0 | |
243 | #define LM3697_HVLED2_CFG_SHIFT 1 | |
244 | #define LM3697_HVLED3_CFG_SHIFT 2 | |
245 | ||
246 | #define LM3697_REG_BL0_RAMP 0x11 | |
247 | #define LM3697_REG_BL1_RAMP 0x12 | |
248 | #define LM3697_RAMPUP_MASK 0xF0 | |
249 | #define LM3697_RAMPUP_SHIFT 4 | |
250 | #define LM3697_RAMPDN_MASK 0x0F | |
251 | #define LM3697_RAMPDN_SHIFT 0 | |
252 | ||
253 | #define LM3697_REG_RAMP_CONF 0x14 | |
254 | #define LM3697_RAMP_MASK 0x0F | |
255 | #define LM3697_RAMP_EACH 0x05 | |
256 | ||
257 | #define LM3697_REG_PWM_CFG 0x1C | |
258 | #define LM3697_PWM_A_MASK BIT(0) | |
259 | #define LM3697_PWM_B_MASK BIT(1) | |
260 | ||
261 | #define LM3697_REG_IMAX_A 0x17 | |
262 | #define LM3697_REG_IMAX_B 0x18 | |
263 | ||
264 | #define LM3697_REG_FEEDBACK_ENABLE 0x19 | |
265 | ||
266 | #define LM3697_REG_BRT_A_LSB 0x20 | |
267 | #define LM3697_REG_BRT_A_MSB 0x21 | |
268 | #define LM3697_REG_BRT_B_LSB 0x22 | |
269 | #define LM3697_REG_BRT_B_MSB 0x23 | |
270 | ||
271 | #define LM3697_REG_ENABLE 0x24 | |
272 | ||
273 | #define LM3697_REG_OPEN_FAULT_STATUS 0xB0 | |
274 | ||
275 | #define LM3697_REG_SHORT_FAULT_STATUS 0xB2 | |
276 | ||
277 | #define LM3697_REG_MONITOR_ENABLE 0xB4 | |
278 | ||
279 | #define LM3697_MAX_REG 0xB4 | |
280 | #endif |