projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 0b271258 BS |
1 | /* |
| 2 | * MFD core driver for Richtek RT5033 | |
| 3 | * | |
| 4 | * Copyright (C) 2014 Samsung Electronics, Co., Ltd. | |
| 5 | * Author: Beomho Seo <beomho.seo@samsung.com> | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or modify | |
| 8 | * it under the terms of the GNU General Public License version 2 as | |
| 9 | * published bythe Free Software Foundation. | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __RT5033_PRIVATE_H__ | |
| 13 | #define __RT5033_PRIVATE_H__ | |
| 14 | ||
| 15 | enum rt5033_reg { | |
| 16 | RT5033_REG_CHG_STAT = 0x00, | |
| 17 | RT5033_REG_CHG_CTRL1 = 0x01, | |
| 18 | RT5033_REG_CHG_CTRL2 = 0x02, | |
| 19 | RT5033_REG_DEVICE_ID = 0x03, | |
| 20 | RT5033_REG_CHG_CTRL3 = 0x04, | |
| 21 | RT5033_REG_CHG_CTRL4 = 0x05, | |
| 22 | RT5033_REG_CHG_CTRL5 = 0x06, | |
| 23 | RT5033_REG_RT_CTRL0 = 0x07, | |
| 24 | RT5033_REG_CHG_RESET = 0x08, | |
| 25 | /* Reserved 0x09~0x18 */ | |
| 26 | RT5033_REG_RT_CTRL1 = 0x19, | |
| 27 | /* Reserved 0x1A~0x20 */ | |
| 28 | RT5033_REG_FLED_FUNCTION1 = 0x21, | |
| 29 | RT5033_REG_FLED_FUNCTION2 = 0x22, | |
| 30 | RT5033_REG_FLED_STROBE_CTRL1 = 0x23, | |
| 31 | RT5033_REG_FLED_STROBE_CTRL2 = 0x24, | |
| 32 | RT5033_REG_FLED_CTRL1 = 0x25, | |
| 33 | RT5033_REG_FLED_CTRL2 = 0x26, | |
| 34 | RT5033_REG_FLED_CTRL3 = 0x27, | |
| 35 | RT5033_REG_FLED_CTRL4 = 0x28, | |
| 36 | RT5033_REG_FLED_CTRL5 = 0x29, | |
| 37 | /* Reserved 0x2A~0x40 */ | |
| 38 | RT5033_REG_CTRL = 0x41, | |
| 39 | RT5033_REG_BUCK_CTRL = 0x42, | |
| 40 | RT5033_REG_LDO_CTRL = 0x43, | |
| 41 | /* Reserved 0x44~0x46 */ | |
| 42 | RT5033_REG_MANUAL_RESET_CTRL = 0x47, | |
| 43 | /* Reserved 0x48~0x5F */ | |
| 44 | RT5033_REG_CHG_IRQ1 = 0x60, | |
| 45 | RT5033_REG_CHG_IRQ2 = 0x61, | |
| 46 | RT5033_REG_CHG_IRQ3 = 0x62, | |
| 47 | RT5033_REG_CHG_IRQ1_CTRL = 0x63, | |
| 48 | RT5033_REG_CHG_IRQ2_CTRL = 0x64, | |
| 49 | RT5033_REG_CHG_IRQ3_CTRL = 0x65, | |
| 50 | RT5033_REG_LED_IRQ_STAT = 0x66, | |
| 51 | RT5033_REG_LED_IRQ_CTRL = 0x67, | |
| 52 | RT5033_REG_PMIC_IRQ_STAT = 0x68, | |
| 53 | RT5033_REG_PMIC_IRQ_CTRL = 0x69, | |
| 54 | RT5033_REG_SHDN_CTRL = 0x6A, | |
| 55 | RT5033_REG_OFF_EVENT = 0x6B, | |
| 56 | ||
| 57 | RT5033_REG_END, | |
| 58 | }; | |
| 59 | ||
| 60 | /* RT5033 Charger state register */ | |
| 61 | #define RT5033_CHG_STAT_MASK 0x20 | |
| 62 | #define RT5033_CHG_STAT_DISCHARGING 0x00 | |
| 63 | #define RT5033_CHG_STAT_FULL 0x10 | |
| 64 | #define RT5033_CHG_STAT_CHARGING 0x20 | |
| 65 | #define RT5033_CHG_STAT_NOT_CHARGING 0x30 | |
| 66 | #define RT5033_CHG_STAT_TYPE_MASK 0x60 | |
| 67 | #define RT5033_CHG_STAT_TYPE_PRE 0x20 | |
| 68 | #define RT5033_CHG_STAT_TYPE_FAST 0x60 | |
| 69 | ||
| 70 | /* RT5033 CHGCTRL1 register */ | |
| 71 | #define RT5033_CHGCTRL1_IAICR_MASK 0xe0 | |
| 72 | #define RT5033_CHGCTRL1_MODE_MASK 0x01 | |
| 73 | ||
| 74 | /* RT5033 CHGCTRL2 register */ | |
| 75 | #define RT5033_CHGCTRL2_CV_MASK 0xfc | |
| 76 | ||
| 77 | /* RT5033 CHGCTRL3 register */ | |
| 78 | #define RT5033_CHGCTRL3_CFO_EN_MASK 0x40 | |
| 79 | #define RT5033_CHGCTRL3_TIMER_MASK 0x38 | |
| 80 | #define RT5033_CHGCTRL3_TIMER_EN_MASK 0x01 | |
| 81 | ||
| 82 | /* RT5033 CHGCTRL4 register */ | |
| 83 | #define RT5033_CHGCTRL4_EOC_MASK 0x07 | |
| 84 | #define RT5033_CHGCTRL4_IPREC_MASK 0x18 | |
| 85 | ||
| 86 | /* RT5033 CHGCTRL5 register */ | |
| 87 | #define RT5033_CHGCTRL5_VPREC_MASK 0x0f | |
| 88 | #define RT5033_CHGCTRL5_ICHG_MASK 0xf0 | |
| 89 | #define RT5033_CHGCTRL5_ICHG_SHIFT 0x04 | |
| 90 | #define RT5033_CHG_MAX_CURRENT 0x0d | |
| 91 | ||
| 92 | /* RT5033 RT CTRL1 register */ | |
| 93 | #define RT5033_RT_CTRL1_UUG_MASK 0x02 | |
| 94 | #define RT5033_RT_HZ_MASK 0x01 | |
| 95 | ||
| 96 | /* RT5033 control register */ | |
| 97 | #define RT5033_CTRL_FCCM_BUCK_MASK 0x00 | |
| 98 | #define RT5033_CTRL_BUCKOMS_MASK 0x01 | |
| 99 | #define RT5033_CTRL_LDOOMS_MASK 0x02 | |
| 100 | #define RT5033_CTRL_SLDOOMS_MASK 0x03 | |
| 101 | #define RT5033_CTRL_EN_BUCK_MASK 0x04 | |
| 102 | #define RT5033_CTRL_EN_LDO_MASK 0x05 | |
| 103 | #define RT5033_CTRL_EN_SAFE_LDO_MASK 0x06 | |
| 104 | #define RT5033_CTRL_LDO_SLEEP_MASK 0x07 | |
| 105 | ||
| 106 | /* RT5033 BUCK control register */ | |
| 107 | #define RT5033_BUCK_CTRL_MASK 0x1f | |
| 108 | ||
| 109 | /* RT5033 LDO control register */ | |
| 110 | #define RT5033_LDO_CTRL_MASK 0x1f | |
| 111 | ||
| 112 | /* RT5033 charger property - model, manufacturer */ | |
| 113 | ||
| 114 | #define RT5033_CHARGER_MODEL "RT5033WSC Charger" | |
| 115 | #define RT5033_MANUFACTURER "Richtek Technology Corporation" | |
| 116 | ||
| 117 | /* | |
| 118 | * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register), | |
| 119 | * AICR mode limits the input current for example, | |
| 120 | * the AIRC 100 mode limits the input current to 100 mA. | |
| 121 | */ | |
| 122 | #define RT5033_AICR_100_MODE 0x20 | |
| 123 | #define RT5033_AICR_500_MODE 0x40 | |
| 124 | #define RT5033_AICR_700_MODE 0x60 | |
| 125 | #define RT5033_AICR_900_MODE 0x80 | |
| 126 | #define RT5033_AICR_1500_MODE 0xc0 | |
| 127 | #define RT5033_AICR_2000_MODE 0xe0 | |
| 128 | #define RT5033_AICR_MODE_MASK 0xe0 | |
| 129 | ||
| 130 | /* RT5033 use internal timer need to set time */ | |
| 131 | #define RT5033_FAST_CHARGE_TIMER4 0x00 | |
| 132 | #define RT5033_FAST_CHARGE_TIMER6 0x01 | |
| 133 | #define RT5033_FAST_CHARGE_TIMER8 0x02 | |
| 134 | #define RT5033_FAST_CHARGE_TIMER9 0x03 | |
| 135 | #define RT5033_FAST_CHARGE_TIMER12 0x04 | |
| 136 | #define RT5033_FAST_CHARGE_TIMER14 0x05 | |
| 137 | #define RT5033_FAST_CHARGE_TIMER16 0x06 | |
| 138 | ||
| 139 | #define RT5033_INT_TIMER_ENABLE 0x01 | |
| 140 | ||
| 141 | /* RT5033 charger termination enable mask */ | |
| 142 | #define RT5033_TE_ENABLE_MASK 0x08 | |
| 143 | ||
| 144 | /* | |
| 145 | * RT5033 charger opa mode. RT50300 have two opa mode charger mode | |
| 146 | * and boost mode for OTG | |
| 147 | */ | |
| 148 | ||
| 149 | #define RT5033_CHARGER_MODE 0x00 | |
| 150 | #define RT5033_BOOST_MODE 0x01 | |
| 151 | ||
| 152 | /* RT5033 charger termination enable */ | |
| 153 | #define RT5033_TE_ENABLE 0x08 | |
| 154 | ||
| 155 | /* RT5033 charger CFO enable */ | |
| 156 | #define RT5033_CFO_ENABLE 0x40 | |
| 157 | ||
| 158 | /* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */ | |
| 159 | #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN 3650000U | |
| 160 | #define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM 25000U | |
| 161 | #define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX 4400000U | |
| 162 | ||
| 163 | /* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */ | |
| 164 | #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN 350000U | |
| 165 | #define RT5033_CHARGER_PRE_CURRENT_STEP_NUM 100000U | |
| 166 | #define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX 650000U | |
| 167 | ||
| 168 | /* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */ | |
| 169 | #define RT5033_CHARGER_FAST_CURRENT_MIN 700000U | |
| 170 | #define RT5033_CHARGER_FAST_CURRENT_STEP_NUM 100000U | |
| 171 | #define RT5033_CHARGER_FAST_CURRENT_MAX 2000000U | |
| 172 | ||
| 173 | /* | |
| 174 | * RT5033 charger const-charge end of charger current ( | |
| 175 | * as in CHGCTRL4 register), uA | |
| 176 | */ | |
| 177 | #define RT5033_CHARGER_EOC_MIN 150000U | |
| 178 | #define RT5033_CHARGER_EOC_REF 300000U | |
| 179 | #define RT5033_CHARGER_EOC_STEP_NUM1 50000U | |
| 180 | #define RT5033_CHARGER_EOC_STEP_NUM2 100000U | |
| 181 | #define RT5033_CHARGER_EOC_MAX 600000U | |
| 182 | ||
| 183 | /* | |
| 184 | * RT5033 charger pre-charge threshold volt limits | |
| 185 | * (as in CHGCTRL5 register), uV | |
| 186 | */ | |
| 187 | ||
| 188 | #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN 2300000U | |
| 189 | #define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM 100000U | |
| 190 | #define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX 3800000U | |
| 191 | ||
| 192 | /* | |
| 193 | * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger | |
| 194 | * circuit. | |
| 195 | */ | |
| 196 | #define RT5033_CHARGER_UUG_ENABLE 0x02 | |
| 197 | ||
| 198 | /* RT5033 charger High impedance mode */ | |
| 199 | #define RT5033_CHARGER_HZ_DISABLE 0x00 | |
| 200 | #define RT5033_CHARGER_HZ_ENABLE 0x01 | |
| 201 | ||
| 202 | /* RT5033 regulator BUCK output voltage uV */ | |
| 203 | #define RT5033_REGULATOR_BUCK_VOLTAGE_MIN 1000000U | |
| 204 | #define RT5033_REGULATOR_BUCK_VOLTAGE_MAX 3000000U | |
| 205 | #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP 100000U | |
| 206 | #define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM 32 | |
| 207 | ||
| 208 | /* RT5033 regulator LDO output voltage uV */ | |
| 209 | #define RT5033_REGULATOR_LDO_VOLTAGE_MIN 1200000U | |
| 210 | #define RT5033_REGULATOR_LDO_VOLTAGE_MAX 3000000U | |
| 211 | #define RT5033_REGULATOR_LDO_VOLTAGE_STEP 100000U | |
| 212 | #define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM 32 | |
| 213 | ||
| 214 | /* RT5033 regulator SAFE LDO output voltage uV */ | |
| 215 | #define RT5033_REGULATOR_SAFE_LDO_VOLTAGE 4900000U | |
| 216 | ||
| 217 | enum rt5033_fuel_reg { | |
| 218 | RT5033_FUEL_REG_OCV_H = 0x00, | |
| 219 | RT5033_FUEL_REG_OCV_L = 0x01, | |
| 220 | RT5033_FUEL_REG_VBAT_H = 0x02, | |
| 221 | RT5033_FUEL_REG_VBAT_L = 0x03, | |
| 222 | RT5033_FUEL_REG_SOC_H = 0x04, | |
| 223 | RT5033_FUEL_REG_SOC_L = 0x05, | |
| 224 | RT5033_FUEL_REG_CTRL_H = 0x06, | |
| 225 | RT5033_FUEL_REG_CTRL_L = 0x07, | |
| 226 | RT5033_FUEL_REG_CRATE = 0x08, | |
| 227 | RT5033_FUEL_REG_DEVICE_ID = 0x09, | |
| 228 | RT5033_FUEL_REG_AVG_VOLT_H = 0x0A, | |
| 229 | RT5033_FUEL_REG_AVG_VOLT_L = 0x0B, | |
| 230 | RT5033_FUEL_REG_CONFIG_H = 0x0C, | |
| 231 | RT5033_FUEL_REG_CONFIG_L = 0x0D, | |
| 232 | /* Reserved 0x0E~0x0F */ | |
| 233 | RT5033_FUEL_REG_IRQ_CTRL = 0x10, | |
| 234 | RT5033_FUEL_REG_IRQ_FLAG = 0x11, | |
| 235 | RT5033_FUEL_VMIN = 0x12, | |
| 236 | RT5033_FUEL_SMIN = 0x13, | |
| 237 | /* Reserved 0x14~0x1F */ | |
| 238 | RT5033_FUEL_VGCOMP1 = 0x20, | |
| 239 | RT5033_FUEL_VGCOMP2 = 0x21, | |
| 240 | RT5033_FUEL_VGCOMP3 = 0x22, | |
| 241 | RT5033_FUEL_VGCOMP4 = 0x23, | |
| 242 | /* Reserved 0x24~0xFD */ | |
| 243 | RT5033_FUEL_MFA_H = 0xFE, | |
| 244 | RT5033_FUEL_MFA_L = 0xFF, | |
| 245 | ||
| 246 | RT5033_FUEL_REG_END, | |
| 247 | }; | |
| 248 | ||
| 249 | /* RT5033 fuel gauge battery present property */ | |
| 250 | #define RT5033_FUEL_BAT_PRESENT 0x02 | |
| 251 | ||
| 252 | /* RT5033 PMIC interrupts */ | |
| 253 | #define RT5033_PMIC_IRQ_BUCKOCP 2 | |
| 254 | #define RT5033_PMIC_IRQ_BUCKLV 3 | |
| 255 | #define RT5033_PMIC_IRQ_SAFELDOLV 4 | |
| 256 | #define RT5033_PMIC_IRQ_LDOLV 5 | |
| 257 | #define RT5033_PMIC_IRQ_OT 6 | |
| 258 | #define RT5033_PMIC_IRQ_VDDA_UV 7 | |
| 259 | ||
| 260 | #endif /* __RT5033_PRIVATE_H__ */ |