[linux-2.6-block.git] / include / linux / mfd / rohm-bd70528.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (C) 2018 ROHM Semiconductors */

#ifndef __LINUX_MFD_BD70528_H__
#define __LINUX_MFD_BD70528_H__

#include <linux/bits.h>
#include <linux/device.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/mfd/rohm-shared.h>
#include <linux/regmap.h>

enum {
	BD70528_BUCK1,
	BD70528_BUCK2,
	BD70528_BUCK3,
	BD70528_LDO1,
	BD70528_LDO2,
	BD70528_LDO3,
	BD70528_LED1,
	BD70528_LED2,
};

struct bd70528_data {
	struct rohm_regmap_dev chip;
	struct mutex rtc_timer_lock;
};

#define BD70528_BUCK_VOLTS 0x10
#define BD70528_LDO_VOLTS 0x20

#define BD70528_REG_BUCK1_EN	0x0F
#define BD70528_REG_BUCK1_VOLT	0x15
#define BD70528_REG_BUCK2_EN	0x10
#define BD70528_REG_BUCK2_VOLT	0x16
#define BD70528_REG_BUCK3_EN	0x11
#define BD70528_REG_BUCK3_VOLT	0x17
#define BD70528_REG_LDO1_EN	0x1b
#define BD70528_REG_LDO1_VOLT	0x1e
#define BD70528_REG_LDO2_EN	0x1c
#define BD70528_REG_LDO2_VOLT	0x1f
#define BD70528_REG_LDO3_EN	0x1d
#define BD70528_REG_LDO3_VOLT	0x20
#define BD70528_REG_LED_CTRL	0x2b
#define BD70528_REG_LED_VOLT	0x29
#define BD70528_REG_LED_EN	0x2a

/* main irq registers */
#define BD70528_REG_INT_MAIN	0x7E
#define BD70528_REG_INT_MAIN_MASK 0x74

/* 'sub irq' registers */
#define BD70528_REG_INT_SHDN	0x7F
#define BD70528_REG_INT_PWR_FLT	0x80
#define BD70528_REG_INT_VR_FLT	0x81
#define BD70528_REG_INT_MISC	0x82
#define BD70528_REG_INT_BAT1	0x83
#define BD70528_REG_INT_BAT2	0x84
#define BD70528_REG_INT_RTC	0x85
#define BD70528_REG_INT_GPIO	0x86
#define BD70528_REG_INT_OP_FAIL	0x87

#define BD70528_REG_INT_SHDN_MASK	0x75
#define BD70528_REG_INT_PWR_FLT_MASK	0x76
#define BD70528_REG_INT_VR_FLT_MASK	0x77
#define BD70528_REG_INT_MISC_MASK	0x78
#define BD70528_REG_INT_BAT1_MASK	0x79
#define BD70528_REG_INT_BAT2_MASK	0x7a
#define BD70528_REG_INT_RTC_MASK	0x7b
#define BD70528_REG_INT_GPIO_MASK	0x7c
#define BD70528_REG_INT_OP_FAIL_MASK	0x7d

/* Reset related 'magic' registers */
#define BD70528_REG_SHIPMODE	0x03
#define BD70528_REG_HWRESET	0x04
#define BD70528_REG_WARMRESET	0x05
#define BD70528_REG_STANDBY	0x06

/* GPIO registers */
#define BD70528_REG_GPIO_STATE	0x8F

#define BD70528_REG_GPIO1_IN	0x4d
#define BD70528_REG_GPIO2_IN	0x4f
#define BD70528_REG_GPIO3_IN	0x51
#define BD70528_REG_GPIO4_IN	0x53
#define BD70528_REG_GPIO1_OUT	0x4e
#define BD70528_REG_GPIO2_OUT	0x50
#define BD70528_REG_GPIO3_OUT	0x52
#define BD70528_REG_GPIO4_OUT	0x54

/* RTC */

#define BD70528_REG_RTC_COUNT_H		0x2d
#define BD70528_REG_RTC_COUNT_L		0x2e
#define BD70528_REG_RTC_SEC		0x2f
#define BD70528_REG_RTC_MINUTE		0x30
#define BD70528_REG_RTC_HOUR		0x31
#define BD70528_REG_RTC_WEEK		0x32
#define BD70528_REG_RTC_DAY		0x33
#define BD70528_REG_RTC_MONTH		0x34
#define BD70528_REG_RTC_YEAR		0x35

#define BD70528_REG_RTC_ALM_SEC		0x36
#define BD70528_REG_RTC_ALM_START	BD70528_REG_RTC_ALM_SEC
#define BD70528_REG_RTC_ALM_MINUTE	0x37
#define BD70528_REG_RTC_ALM_HOUR	0x38
#define BD70528_REG_RTC_ALM_WEEK	0x39
#define BD70528_REG_RTC_ALM_DAY		0x3a
#define BD70528_REG_RTC_ALM_MONTH	0x3b
#define BD70528_REG_RTC_ALM_YEAR	0x3c
#define BD70528_REG_RTC_ALM_MASK	0x3d
#define BD70528_REG_RTC_ALM_REPEAT	0x3e
#define BD70528_REG_RTC_START		BD70528_REG_RTC_SEC

#define BD70528_REG_RTC_WAKE_SEC	0x43
#define BD70528_REG_RTC_WAKE_START	BD70528_REG_RTC_WAKE_SEC
#define BD70528_REG_RTC_WAKE_MIN	0x44
#define BD70528_REG_RTC_WAKE_HOUR	0x45
#define BD70528_REG_RTC_WAKE_CTRL	0x46

#define BD70528_REG_ELAPSED_TIMER_EN	0x42
#define BD70528_REG_WAKE_EN		0x46

/* WDT registers */
#define BD70528_REG_WDT_CTRL		0x4A
#define BD70528_REG_WDT_HOUR		0x49
#define BD70528_REG_WDT_MINUTE		0x48
#define BD70528_REG_WDT_SEC		0x47

/* Charger / Battery */
#define BD70528_REG_CHG_CURR_STAT	0x59
#define BD70528_REG_CHG_BAT_STAT	0x57
#define BD70528_REG_CHG_BAT_TEMP	0x58
#define BD70528_REG_CHG_IN_STAT		0x56
#define BD70528_REG_CHG_DCIN_ILIM	0x5d
#define BD70528_REG_CHG_CHG_CURR_WARM	0x61
#define BD70528_REG_CHG_CHG_CURR_COLD	0x62

/* Masks for main IRQ register bits */
enum {
	BD70528_INT_SHDN,
#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
	BD70528_INT_PWR_FLT,
#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
	BD70528_INT_VR_FLT,
#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
	BD70528_INT_MISC,
#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
	BD70528_INT_BAT1,
#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
	BD70528_INT_RTC,
#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
	BD70528_INT_GPIO,
#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
	BD70528_INT_OP_FAIL,
#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
};

/* IRQs */
enum {
	/* Shutdown register IRQs */
	BD70528_INT_LONGPUSH,
	BD70528_INT_WDT,
	BD70528_INT_HWRESET,
	BD70528_INT_RSTB_FAULT,
	BD70528_INT_VBAT_UVLO,
	BD70528_INT_TSD,
	BD70528_INT_RSTIN,
	/* Power failure register IRQs */
	BD70528_INT_BUCK1_FAULT,
	BD70528_INT_BUCK2_FAULT,
	BD70528_INT_BUCK3_FAULT,
	BD70528_INT_LDO1_FAULT,
	BD70528_INT_LDO2_FAULT,
	BD70528_INT_LDO3_FAULT,
	BD70528_INT_LED1_FAULT,
	BD70528_INT_LED2_FAULT,
	/* VR FAULT register IRQs */
	BD70528_INT_BUCK1_OCP,
	BD70528_INT_BUCK2_OCP,
	BD70528_INT_BUCK3_OCP,
	BD70528_INT_LED1_OCP,
	BD70528_INT_LED2_OCP,
	BD70528_INT_BUCK1_FULLON,
	BD70528_INT_BUCK2_FULLON,
	/* PMU register interrupts */
	BD70528_INT_SHORTPUSH,
	BD70528_INT_AUTO_WAKEUP,
	BD70528_INT_STATE_CHANGE,
	/* Charger 1 register IRQs */
	BD70528_INT_BAT_OV_RES,
	BD70528_INT_BAT_OV_DET,
	BD70528_INT_DBAT_DET,
	BD70528_INT_BATTSD_COLD_RES,
	BD70528_INT_BATTSD_COLD_DET,
	BD70528_INT_BATTSD_HOT_RES,
	BD70528_INT_BATTSD_HOT_DET,
	BD70528_INT_CHG_TSD,
	/* Charger 2 register IRQs */
	BD70528_INT_BAT_RMV,
	BD70528_INT_BAT_DET,
	BD70528_INT_DCIN2_OV_RES,
	BD70528_INT_DCIN2_OV_DET,
	BD70528_INT_DCIN2_RMV,
	BD70528_INT_DCIN2_DET,
	BD70528_INT_DCIN1_RMV,
	BD70528_INT_DCIN1_DET,
	/* RTC register IRQs */
	BD70528_INT_RTC_ALARM,
	BD70528_INT_ELPS_TIM,
	/* GPIO register IRQs */
	BD70528_INT_GPIO0,
	BD70528_INT_GPIO1,
	BD70528_INT_GPIO2,
	BD70528_INT_GPIO3,
	/* Invalid operation register IRQs */
	BD70528_INT_BUCK1_DVS_OPFAIL,
	BD70528_INT_BUCK2_DVS_OPFAIL,
	BD70528_INT_BUCK3_DVS_OPFAIL,
	BD70528_INT_LED1_VOLT_OPFAIL,
	BD70528_INT_LED2_VOLT_OPFAIL,
};

/* Masks */
#define BD70528_INT_LONGPUSH_MASK 0x1
#define BD70528_INT_WDT_MASK 0x2
#define BD70528_INT_HWRESET_MASK 0x4
#define BD70528_INT_RSTB_FAULT_MASK 0x8
#define BD70528_INT_VBAT_UVLO_MASK 0x10
#define BD70528_INT_TSD_MASK 0x20
#define BD70528_INT_RSTIN_MASK 0x40

#define BD70528_INT_BUCK1_FAULT_MASK 0x1
#define BD70528_INT_BUCK2_FAULT_MASK 0x2
#define BD70528_INT_BUCK3_FAULT_MASK 0x4
#define BD70528_INT_LDO1_FAULT_MASK 0x8
#define BD70528_INT_LDO2_FAULT_MASK 0x10
#define BD70528_INT_LDO3_FAULT_MASK 0x20
#define BD70528_INT_LED1_FAULT_MASK 0x40
#define BD70528_INT_LED2_FAULT_MASK 0x80

#define BD70528_INT_BUCK1_OCP_MASK 0x1
#define BD70528_INT_BUCK2_OCP_MASK 0x2
#define BD70528_INT_BUCK3_OCP_MASK 0x4
#define BD70528_INT_LED1_OCP_MASK 0x8
#define BD70528_INT_LED2_OCP_MASK 0x10
#define BD70528_INT_BUCK1_FULLON_MASK 0x20
#define BD70528_INT_BUCK2_FULLON_MASK 0x40

#define BD70528_INT_SHORTPUSH_MASK 0x1
#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
#define BD70528_INT_STATE_CHANGE_MASK 0x10

#define BD70528_INT_BAT_OV_RES_MASK 0x1
#define BD70528_INT_BAT_OV_DET_MASK 0x2
#define BD70528_INT_DBAT_DET_MASK 0x4
#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
#define BD70528_INT_CHG_TSD_MASK 0x80

#define BD70528_INT_BAT_RMV_MASK 0x1
#define BD70528_INT_BAT_DET_MASK 0x2
#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
#define BD70528_INT_DCIN2_RMV_MASK 0x10
#define BD70528_INT_DCIN2_DET_MASK 0x20
#define BD70528_INT_DCIN1_RMV_MASK 0x40
#define BD70528_INT_DCIN1_DET_MASK 0x80

#define BD70528_INT_RTC_ALARM_MASK 0x1
#define BD70528_INT_ELPS_TIM_MASK 0x2

#define BD70528_INT_GPIO0_MASK 0x1
#define BD70528_INT_GPIO1_MASK 0x2
#define BD70528_INT_GPIO2_MASK 0x4
#define BD70528_INT_GPIO3_MASK 0x8

#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20

#define BD70528_DEBOUNCE_MASK 0x3

#define BD70528_DEBOUNCE_DISABLE 0
#define BD70528_DEBOUNCE_15MS 1
#define BD70528_DEBOUNCE_30MS 2
#define BD70528_DEBOUNCE_50MS 3

#define BD70528_GPIO_DRIVE_MASK 0x2
#define BD70528_GPIO_PUSH_PULL 0x0
#define BD70528_GPIO_OPEN_DRAIN 0x2

#define BD70528_GPIO_OUT_EN_MASK 0x80
#define BD70528_GPIO_OUT_ENABLE 0x80
#define BD70528_GPIO_OUT_DISABLE 0x0

#define BD70528_GPIO_OUT_HI 0x1
#define BD70528_GPIO_OUT_LO 0x0
#define BD70528_GPIO_OUT_MASK 0x1

#define BD70528_GPIO_IN_STATE_BASE 1

/* RTC masks to mask out reserved bits */

#define BD70528_MASK_ELAPSED_TIMER_EN	0x1
/* Mask second, min and hour fields
 * HW would support ALM irq for over 24h
 * (by setting day, month and year too)
 * but as we wish to keep this same as for
 * wake-up we limit ALM to 24H and only
 * unmask sec, min and hour
 */
#define BD70528_MASK_WAKE_EN		0x1

/* WDT masks */
#define BD70528_MASK_WDT_EN		0x1
#define BD70528_MASK_WDT_HOUR		0x1
#define BD70528_MASK_WDT_MINUTE		0x7f
#define BD70528_MASK_WDT_SEC		0x7f

#define BD70528_WDT_STATE_BIT		0x1
#define BD70528_ELAPSED_STATE_BIT	0x2
#define BD70528_WAKE_STATE_BIT		0x4

/* Charger masks */
#define BD70528_MASK_CHG_STAT		0x7f
#define BD70528_MASK_CHG_BAT_TIMER	0x20
#define BD70528_MASK_CHG_BAT_OVERVOLT	0x10
#define BD70528_MASK_CHG_BAT_DETECT	0x1
#define BD70528_MASK_CHG_DCIN1_UVLO	0x1
#define BD70528_MASK_CHG_DCIN_ILIM	0x3f
#define BD70528_MASK_CHG_CHG_CURR	0x1f
#define BD70528_MASK_CHG_TRICKLE_CURR	0x10

/*
 * Note, external battery register is the lonely rider at
 * address 0xc5. See how to stuff that in the regmap
 */
#define BD70528_MAX_REGISTER 0x94

/* Buck control masks */
#define BD70528_MASK_RUN_EN	0x4
#define BD70528_MASK_STBY_EN	0x2
#define BD70528_MASK_IDLE_EN	0x1
#define BD70528_MASK_LED1_EN	0x1
#define BD70528_MASK_LED2_EN	0x10

#define BD70528_MASK_BUCK_VOLT	0xf
#define BD70528_MASK_LDO_VOLT	0x1f
#define BD70528_MASK_LED1_VOLT	0x1
#define BD70528_MASK_LED2_VOLT	0x10

/* Misc irq masks */
#define BD70528_INT_MASK_SHORT_PUSH	1
#define BD70528_INT_MASK_AUTO_WAKE	2
#define BD70528_INT_MASK_POWER_STATE	4

#define BD70528_MASK_BUCK_RAMP 0x10
#define BD70528_SIFT_BUCK_RAMP 4

#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)

int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state);
void bd70528_wdt_lock(struct rohm_regmap_dev *data);
void bd70528_wdt_unlock(struct rohm_regmap_dev *data);

#else /* CONFIG_BD70528_WATCHDOG */

static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
				  int *old_state)
{
	return 0;
}

static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
{
}

static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
{
}

#endif /* CONFIG_BD70528_WATCHDOG */

#endif /* __LINUX_MFD_BD70528_H__ */
Commit	Line	Data
21b7c58f MV	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
	2	/* Copyright (C) 2018 ROHM Semiconductors */
	3
	4	#ifndef __LINUX_MFD_BD70528_H__
	5	#define __LINUX_MFD_BD70528_H__
	6
	7	#include <linux/bits.h>
	8	#include <linux/device.h>
	9	#include <linux/mfd/rohm-generic.h>
fe5a591b	10	#include <linux/mfd/rohm-shared.h>
21b7c58f MV	11	#include <linux/regmap.h>
	12
	13	enum {
	14	BD70528_BUCK1,
	15	BD70528_BUCK2,
	16	BD70528_BUCK3,
	17	BD70528_LDO1,
	18	BD70528_LDO2,
	19	BD70528_LDO3,
	20	BD70528_LED1,
	21	BD70528_LED2,
	22	};
	23
	24	struct bd70528_data {
	25	struct rohm_regmap_dev chip;
	26	struct mutex rtc_timer_lock;
	27	};
	28
0514582a	29	#define BD70528_BUCK_VOLTS 0x10
21b7c58f MV	30	#define BD70528_LDO_VOLTS 0x20
	31
	32	#define BD70528_REG_BUCK1_EN 0x0F
	33	#define BD70528_REG_BUCK1_VOLT 0x15
	34	#define BD70528_REG_BUCK2_EN 0x10
	35	#define BD70528_REG_BUCK2_VOLT 0x16
	36	#define BD70528_REG_BUCK3_EN 0x11
	37	#define BD70528_REG_BUCK3_VOLT 0x17
	38	#define BD70528_REG_LDO1_EN 0x1b
	39	#define BD70528_REG_LDO1_VOLT 0x1e
	40	#define BD70528_REG_LDO2_EN 0x1c
	41	#define BD70528_REG_LDO2_VOLT 0x1f
	42	#define BD70528_REG_LDO3_EN 0x1d
	43	#define BD70528_REG_LDO3_VOLT 0x20
	44	#define BD70528_REG_LED_CTRL 0x2b
	45	#define BD70528_REG_LED_VOLT 0x29
	46	#define BD70528_REG_LED_EN 0x2a
	47
	48	/* main irq registers */
	49	#define BD70528_REG_INT_MAIN 0x7E
	50	#define BD70528_REG_INT_MAIN_MASK 0x74
	51
	52	/* 'sub irq' registers */
	53	#define BD70528_REG_INT_SHDN 0x7F
	54	#define BD70528_REG_INT_PWR_FLT 0x80
	55	#define BD70528_REG_INT_VR_FLT 0x81
	56	#define BD70528_REG_INT_MISC 0x82
	57	#define BD70528_REG_INT_BAT1 0x83
	58	#define BD70528_REG_INT_BAT2 0x84
	59	#define BD70528_REG_INT_RTC 0x85
	60	#define BD70528_REG_INT_GPIO 0x86
	61	#define BD70528_REG_INT_OP_FAIL 0x87
	62
	63	#define BD70528_REG_INT_SHDN_MASK 0x75
	64	#define BD70528_REG_INT_PWR_FLT_MASK 0x76
	65	#define BD70528_REG_INT_VR_FLT_MASK 0x77
	66	#define BD70528_REG_INT_MISC_MASK 0x78
	67	#define BD70528_REG_INT_BAT1_MASK 0x79
	68	#define BD70528_REG_INT_BAT2_MASK 0x7a
	69	#define BD70528_REG_INT_RTC_MASK 0x7b
	70	#define BD70528_REG_INT_GPIO_MASK 0x7c
	71	#define BD70528_REG_INT_OP_FAIL_MASK 0x7d
	72
	73	/* Reset related 'magic' registers */
	74	#define BD70528_REG_SHIPMODE 0x03
	75	#define BD70528_REG_HWRESET 0x04
	76	#define BD70528_REG_WARMRESET 0x05
	77	#define BD70528_REG_STANDBY 0x06
	78
	79	/* GPIO registers */
	80	#define BD70528_REG_GPIO_STATE 0x8F
	81
	82	#define BD70528_REG_GPIO1_IN 0x4d
	83	#define BD70528_REG_GPIO2_IN 0x4f
	84	#define BD70528_REG_GPIO3_IN 0x51
	85	#define BD70528_REG_GPIO4_IN 0x53
	86	#define BD70528_REG_GPIO1_OUT 0x4e
	87	#define BD70528_REG_GPIO2_OUT 0x50
	88	#define BD70528_REG_GPIO3_OUT 0x52
	89	#define BD70528_REG_GPIO4_OUT 0x54
	90
21b7c58f MV	91	/* RTC */
	92
	93	#define BD70528_REG_RTC_COUNT_H 0x2d
	94	#define BD70528_REG_RTC_COUNT_L 0x2e
	95	#define BD70528_REG_RTC_SEC 0x2f
	96	#define BD70528_REG_RTC_MINUTE 0x30
	97	#define BD70528_REG_RTC_HOUR 0x31
	98	#define BD70528_REG_RTC_WEEK 0x32
	99	#define BD70528_REG_RTC_DAY 0x33
	100	#define BD70528_REG_RTC_MONTH 0x34
	101	#define BD70528_REG_RTC_YEAR 0x35
	102
	103	#define BD70528_REG_RTC_ALM_SEC 0x36
	104	#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC
	105	#define BD70528_REG_RTC_ALM_MINUTE 0x37
	106	#define BD70528_REG_RTC_ALM_HOUR 0x38
	107	#define BD70528_REG_RTC_ALM_WEEK 0x39
	108	#define BD70528_REG_RTC_ALM_DAY 0x3a
	109	#define BD70528_REG_RTC_ALM_MONTH 0x3b
	110	#define BD70528_REG_RTC_ALM_YEAR 0x3c
	111	#define BD70528_REG_RTC_ALM_MASK 0x3d
	112	#define BD70528_REG_RTC_ALM_REPEAT 0x3e
	113	#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC
	114
	115	#define BD70528_REG_RTC_WAKE_SEC 0x43
	116	#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC
	117	#define BD70528_REG_RTC_WAKE_MIN 0x44
	118	#define BD70528_REG_RTC_WAKE_HOUR 0x45
	119	#define BD70528_REG_RTC_WAKE_CTRL 0x46
	120
	121	#define BD70528_REG_ELAPSED_TIMER_EN 0x42
	122	#define BD70528_REG_WAKE_EN 0x46
	123
	124	/* WDT registers */
	125	#define BD70528_REG_WDT_CTRL 0x4A
	126	#define BD70528_REG_WDT_HOUR 0x49
	127	#define BD70528_REG_WDT_MINUTE 0x48
	128	#define BD70528_REG_WDT_SEC 0x47
	129
	130	/* Charger / Battery */
	131	#define BD70528_REG_CHG_CURR_STAT 0x59
	132	#define BD70528_REG_CHG_BAT_STAT 0x57
	133	#define BD70528_REG_CHG_BAT_TEMP 0x58
	134	#define BD70528_REG_CHG_IN_STAT 0x56
	135	#define BD70528_REG_CHG_DCIN_ILIM 0x5d
	136	#define BD70528_REG_CHG_CHG_CURR_WARM 0x61
	137	#define BD70528_REG_CHG_CHG_CURR_COLD 0x62
	138
	139	/* Masks for main IRQ register bits */
	140	enum {
	141	BD70528_INT_SHDN,
	142	#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN)
	143	BD70528_INT_PWR_FLT,
	144	#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT)
	145	BD70528_INT_VR_FLT,
	146	#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT)
	147	BD70528_INT_MISC,
	148	#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC)
	149	BD70528_INT_BAT1,
	150	#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1)
	151	BD70528_INT_RTC,
	152	#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC)
	153	BD70528_INT_GPIO,
	154	#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO)
155	BD70528_INT_OP_FAIL,
156	#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL)
157	};
158
159	/* IRQs */
160	enum {
161	/* Shutdown register IRQs */
162	BD70528_INT_LONGPUSH,
163	BD70528_INT_WDT,
164	BD70528_INT_HWRESET,
165	BD70528_INT_RSTB_FAULT,
166	BD70528_INT_VBAT_UVLO,
167	BD70528_INT_TSD,
168	BD70528_INT_RSTIN,
169	/* Power failure register IRQs */
170	BD70528_INT_BUCK1_FAULT,
171	BD70528_INT_BUCK2_FAULT,
172	BD70528_INT_BUCK3_FAULT,
173	BD70528_INT_LDO1_FAULT,
174	BD70528_INT_LDO2_FAULT,
175	BD70528_INT_LDO3_FAULT,
176	BD70528_INT_LED1_FAULT,
177	BD70528_INT_LED2_FAULT,
178	/* VR FAULT register IRQs */
179	BD70528_INT_BUCK1_OCP,
180	BD70528_INT_BUCK2_OCP,
181	BD70528_INT_BUCK3_OCP,
182	BD70528_INT_LED1_OCP,
183	BD70528_INT_LED2_OCP,
184	BD70528_INT_BUCK1_FULLON,
185	BD70528_INT_BUCK2_FULLON,
186	/* PMU register interrupts */
187	BD70528_INT_SHORTPUSH,
188	BD70528_INT_AUTO_WAKEUP,
189	BD70528_INT_STATE_CHANGE,
190	/* Charger 1 register IRQs */
191	BD70528_INT_BAT_OV_RES,
192	BD70528_INT_BAT_OV_DET,
193	BD70528_INT_DBAT_DET,
194	BD70528_INT_BATTSD_COLD_RES,
195	BD70528_INT_BATTSD_COLD_DET,
196	BD70528_INT_BATTSD_HOT_RES,
197	BD70528_INT_BATTSD_HOT_DET,
198	BD70528_INT_CHG_TSD,
199	/* Charger 2 register IRQs */
200	BD70528_INT_BAT_RMV,
201	BD70528_INT_BAT_DET,
202	BD70528_INT_DCIN2_OV_RES,
203	BD70528_INT_DCIN2_OV_DET,
204	BD70528_INT_DCIN2_RMV,
205	BD70528_INT_DCIN2_DET,
206	BD70528_INT_DCIN1_RMV,
207	BD70528_INT_DCIN1_DET,
208	/* RTC register IRQs */
209	BD70528_INT_RTC_ALARM,
210	BD70528_INT_ELPS_TIM,
211	/* GPIO register IRQs */
212	BD70528_INT_GPIO0,
213	BD70528_INT_GPIO1,
214	BD70528_INT_GPIO2,
215	BD70528_INT_GPIO3,
216	/* Invalid operation register IRQs */
217	BD70528_INT_BUCK1_DVS_OPFAIL,
218	BD70528_INT_BUCK2_DVS_OPFAIL,
219	BD70528_INT_BUCK3_DVS_OPFAIL,
220	BD70528_INT_LED1_VOLT_OPFAIL,
221	BD70528_INT_LED2_VOLT_OPFAIL,
222	};
223
224	/* Masks */
225	#define BD70528_INT_LONGPUSH_MASK 0x1
226	#define BD70528_INT_WDT_MASK 0x2
227	#define BD70528_INT_HWRESET_MASK 0x4
228	#define BD70528_INT_RSTB_FAULT_MASK 0x8
229	#define BD70528_INT_VBAT_UVLO_MASK 0x10
230	#define BD70528_INT_TSD_MASK 0x20
231	#define BD70528_INT_RSTIN_MASK 0x40
232
233	#define BD70528_INT_BUCK1_FAULT_MASK 0x1
234	#define BD70528_INT_BUCK2_FAULT_MASK 0x2
235	#define BD70528_INT_BUCK3_FAULT_MASK 0x4
236	#define BD70528_INT_LDO1_FAULT_MASK 0x8
237	#define BD70528_INT_LDO2_FAULT_MASK 0x10
238	#define BD70528_INT_LDO3_FAULT_MASK 0x20
239	#define BD70528_INT_LED1_FAULT_MASK 0x40
240	#define BD70528_INT_LED2_FAULT_MASK 0x80
241
242	#define BD70528_INT_BUCK1_OCP_MASK 0x1
243	#define BD70528_INT_BUCK2_OCP_MASK 0x2
244	#define BD70528_INT_BUCK3_OCP_MASK 0x4
245	#define BD70528_INT_LED1_OCP_MASK 0x8
246	#define BD70528_INT_LED2_OCP_MASK 0x10
247	#define BD70528_INT_BUCK1_FULLON_MASK 0x20
248	#define BD70528_INT_BUCK2_FULLON_MASK 0x40
249
250	#define BD70528_INT_SHORTPUSH_MASK 0x1
251	#define BD70528_INT_AUTO_WAKEUP_MASK 0x2
252	#define BD70528_INT_STATE_CHANGE_MASK 0x10
253
254	#define BD70528_INT_BAT_OV_RES_MASK 0x1
255	#define BD70528_INT_BAT_OV_DET_MASK 0x2
256	#define BD70528_INT_DBAT_DET_MASK 0x4
257	#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8
258	#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10
259	#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20
260	#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40
261	#define BD70528_INT_CHG_TSD_MASK 0x80
262
263	#define BD70528_INT_BAT_RMV_MASK 0x1
264	#define BD70528_INT_BAT_DET_MASK 0x2
265	#define BD70528_INT_DCIN2_OV_RES_MASK 0x4
266	#define BD70528_INT_DCIN2_OV_DET_MASK 0x8
267	#define BD70528_INT_DCIN2_RMV_MASK 0x10
268	#define BD70528_INT_DCIN2_DET_MASK 0x20
269	#define BD70528_INT_DCIN1_RMV_MASK 0x40
270	#define BD70528_INT_DCIN1_DET_MASK 0x80
271
272	#define BD70528_INT_RTC_ALARM_MASK 0x1
273	#define BD70528_INT_ELPS_TIM_MASK 0x2
274
275	#define BD70528_INT_GPIO0_MASK 0x1
276	#define BD70528_INT_GPIO1_MASK 0x2
277	#define BD70528_INT_GPIO2_MASK 0x4
278	#define BD70528_INT_GPIO3_MASK 0x8
279
280	#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1
281	#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2
282	#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4
283	#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10
284	#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20
285
286	#define BD70528_DEBOUNCE_MASK 0x3
287
288	#define BD70528_DEBOUNCE_DISABLE 0
289	#define BD70528_DEBOUNCE_15MS 1
290	#define BD70528_DEBOUNCE_30MS 2
291	#define BD70528_DEBOUNCE_50MS 3
292
293	#define BD70528_GPIO_DRIVE_MASK 0x2
294	#define BD70528_GPIO_PUSH_PULL 0x0
295	#define BD70528_GPIO_OPEN_DRAIN 0x2
296
297	#define BD70528_GPIO_OUT_EN_MASK 0x80
298	#define BD70528_GPIO_OUT_ENABLE 0x80
299	#define BD70528_GPIO_OUT_DISABLE 0x0
300
301	#define BD70528_GPIO_OUT_HI 0x1
302	#define BD70528_GPIO_OUT_LO 0x0
303	#define BD70528_GPIO_OUT_MASK 0x1
304
305	#define BD70528_GPIO_IN_STATE_BASE 1
306
21b7c58f MV	307	/* RTC masks to mask out reserved bits */
21b7c58f MV	308
21b7c58f MV	309	#define BD70528_MASK_ELAPSED_TIMER_EN 0x1
	310	/* Mask second, min and hour fields
	311	* HW would support ALM irq for over 24h
	312	* (by setting day, month and year too)
	313	* but as we wish to keep this same as for
	314	* wake-up we limit ALM to 24H and only
	315	* unmask sec, min and hour
	316	*/
21b7c58f MV	317	#define BD70528_MASK_WAKE_EN 0x1
	318
	319	/* WDT masks */
	320	#define BD70528_MASK_WDT_EN 0x1
	321	#define BD70528_MASK_WDT_HOUR 0x1
	322	#define BD70528_MASK_WDT_MINUTE 0x7f
	323	#define BD70528_MASK_WDT_SEC 0x7f
	324
	325	#define BD70528_WDT_STATE_BIT 0x1
	326	#define BD70528_ELAPSED_STATE_BIT 0x2
	327	#define BD70528_WAKE_STATE_BIT 0x4
	328
	329	/* Charger masks */
	330	#define BD70528_MASK_CHG_STAT 0x7f
	331	#define BD70528_MASK_CHG_BAT_TIMER 0x20
	332	#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10
	333	#define BD70528_MASK_CHG_BAT_DETECT 0x1
	334	#define BD70528_MASK_CHG_DCIN1_UVLO 0x1
	335	#define BD70528_MASK_CHG_DCIN_ILIM 0x3f
	336	#define BD70528_MASK_CHG_CHG_CURR 0x1f
	337	#define BD70528_MASK_CHG_TRICKLE_CURR 0x10
	338
	339	/*
	340	* Note, external battery register is the lonely rider at
	341	* address 0xc5. See how to stuff that in the regmap
	342	*/
	343	#define BD70528_MAX_REGISTER 0x94
	344
	345	/* Buck control masks */
	346	#define BD70528_MASK_RUN_EN 0x4
	347	#define BD70528_MASK_STBY_EN 0x2
	348	#define BD70528_MASK_IDLE_EN 0x1
	349	#define BD70528_MASK_LED1_EN 0x1
	350	#define BD70528_MASK_LED2_EN 0x10
	351
	352	#define BD70528_MASK_BUCK_VOLT 0xf
	353	#define BD70528_MASK_LDO_VOLT 0x1f
	354	#define BD70528_MASK_LED1_VOLT 0x1
	355	#define BD70528_MASK_LED2_VOLT 0x10
	356
	357	/* Misc irq masks */
	358	#define BD70528_INT_MASK_SHORT_PUSH 1
	359	#define BD70528_INT_MASK_AUTO_WAKE 2
	360	#define BD70528_INT_MASK_POWER_STATE 4
	361
	362	#define BD70528_MASK_BUCK_RAMP 0x10
	363	#define BD70528_SIFT_BUCK_RAMP 4
	364
	365	#if IS_ENABLED(CONFIG_BD70528_WATCHDOG)
	366
	367	int bd70528_wdt_set(struct rohm_regmap_dev data, int enable, int old_state);
	368	void bd70528_wdt_lock(struct rohm_regmap_dev *data);
	369	void bd70528_wdt_unlock(struct rohm_regmap_dev *data);
	370
	371	#else /* CONFIG_BD70528_WATCHDOG */
	372
	373	static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable,
	374	int *old_state)
	375	{
	376	return 0;
	377	}
	378
	379	static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data)
	380	{
381	}
382
383	static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data)
384	{
385	}
386
387	#endif /* CONFIG_BD70528_WATCHDOG */
388
389	#endif /* __LINUX_MFD_BD70528_H__ */