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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
8e005935 UKK |
2 | /* |
3 | * Copyright 2009-2010 Pengutronix | |
4 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | |
8e005935 UKK |
5 | */ |
6 | #ifndef __LINUX_MFD_MC13XXX_H | |
7 | #define __LINUX_MFD_MC13XXX_H | |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | ||
11 | struct mc13xxx; | |
12 | ||
13 | void mc13xxx_lock(struct mc13xxx *mc13xxx); | |
14 | void mc13xxx_unlock(struct mc13xxx *mc13xxx); | |
15 | ||
16 | int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val); | |
17 | int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val); | |
18 | int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset, | |
19 | u32 mask, u32 val); | |
20 | ||
8e005935 UKK |
21 | int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq, |
22 | irq_handler_t handler, const char *name, void *dev); | |
8e005935 UKK |
23 | int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev); |
24 | ||
8e005935 UKK |
25 | int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq, |
26 | int *enabled, int *pending); | |
8e005935 UKK |
27 | |
28 | int mc13xxx_get_flags(struct mc13xxx *mc13xxx); | |
29 | ||
fec316d6 | 30 | int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, |
1039d762 MT |
31 | unsigned int mode, unsigned int channel, |
32 | u8 ato, bool atox, unsigned int *sample); | |
fec316d6 | 33 | |
10f9edae AS |
34 | /* Deprecated calls */ |
35 | static inline int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq) | |
36 | { | |
37 | return 0; | |
38 | } | |
39 | ||
40 | static inline int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq, | |
41 | irq_handler_t handler, | |
42 | const char *name, void *dev) | |
43 | { | |
44 | return mc13xxx_irq_request(mc13xxx, irq, handler, name, dev); | |
45 | } | |
46 | ||
47 | int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq); | |
48 | int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq); | |
49 | ||
fd792f8f MB |
50 | #define MC13783_AUDIO_RX0 36 |
51 | #define MC13783_AUDIO_RX1 37 | |
52 | #define MC13783_AUDIO_TX 38 | |
53 | #define MC13783_SSI_NETWORK 39 | |
54 | #define MC13783_AUDIO_CODEC 40 | |
55 | #define MC13783_AUDIO_DAC 41 | |
56 | ||
8e005935 UKK |
57 | #define MC13XXX_IRQ_ADCDONE 0 |
58 | #define MC13XXX_IRQ_ADCBISDONE 1 | |
59 | #define MC13XXX_IRQ_TS 2 | |
60 | #define MC13XXX_IRQ_CHGDET 6 | |
61 | #define MC13XXX_IRQ_CHGREV 8 | |
62 | #define MC13XXX_IRQ_CHGSHORT 9 | |
63 | #define MC13XXX_IRQ_CCCV 10 | |
64 | #define MC13XXX_IRQ_CHGCURR 11 | |
65 | #define MC13XXX_IRQ_BPON 12 | |
66 | #define MC13XXX_IRQ_LOBATL 13 | |
67 | #define MC13XXX_IRQ_LOBATH 14 | |
68 | #define MC13XXX_IRQ_1HZ 24 | |
69 | #define MC13XXX_IRQ_TODA 25 | |
70 | #define MC13XXX_IRQ_SYSRST 30 | |
71 | #define MC13XXX_IRQ_RTCRST 31 | |
72 | #define MC13XXX_IRQ_PC 32 | |
73 | #define MC13XXX_IRQ_WARM 33 | |
74 | #define MC13XXX_IRQ_MEMHLD 34 | |
75 | #define MC13XXX_IRQ_THWARNL 36 | |
76 | #define MC13XXX_IRQ_THWARNH 37 | |
77 | #define MC13XXX_IRQ_CLK 38 | |
78 | ||
8e005935 UKK |
79 | struct regulator_init_data; |
80 | ||
81 | struct mc13xxx_regulator_init_data { | |
82 | int id; | |
83 | struct regulator_init_data *init_data; | |
93bcb23b | 84 | struct device_node *node; |
8e005935 UKK |
85 | }; |
86 | ||
87 | struct mc13xxx_regulator_platform_data { | |
88 | int num_regulators; | |
89 | struct mc13xxx_regulator_init_data *regulators; | |
90 | }; | |
91 | ||
9d263813 AS |
92 | enum { |
93 | /* MC13783 LED IDs */ | |
94 | MC13783_LED_MD, | |
95 | MC13783_LED_AD, | |
96 | MC13783_LED_KP, | |
97 | MC13783_LED_R1, | |
98 | MC13783_LED_G1, | |
99 | MC13783_LED_B1, | |
100 | MC13783_LED_R2, | |
101 | MC13783_LED_G2, | |
102 | MC13783_LED_B2, | |
103 | MC13783_LED_R3, | |
104 | MC13783_LED_G3, | |
105 | MC13783_LED_B3, | |
ae6cdb03 AS |
106 | /* MC13892 LED IDs */ |
107 | MC13892_LED_MD, | |
108 | MC13892_LED_AD, | |
109 | MC13892_LED_KP, | |
110 | MC13892_LED_R, | |
111 | MC13892_LED_G, | |
112 | MC13892_LED_B, | |
a59ce658 AS |
113 | /* MC34708 LED IDs */ |
114 | MC34708_LED_R, | |
115 | MC34708_LED_G, | |
9d263813 AS |
116 | }; |
117 | ||
8e005935 | 118 | struct mc13xxx_led_platform_data { |
8e005935 UKK |
119 | int id; |
120 | const char *name; | |
121 | const char *default_trigger; | |
8e005935 UKK |
122 | }; |
123 | ||
9d263813 AS |
124 | #define MAX_LED_CONTROL_REGS 6 |
125 | ||
01a7a063 | 126 | /* MC13783 LED Control 0 */ |
9d263813 AS |
127 | #define MC13783_LED_C0_ENABLE (1 << 0) |
128 | #define MC13783_LED_C0_TRIODE_MD (1 << 7) | |
129 | #define MC13783_LED_C0_TRIODE_AD (1 << 8) | |
130 | #define MC13783_LED_C0_TRIODE_KP (1 << 9) | |
131 | #define MC13783_LED_C0_BOOST (1 << 10) | |
132 | #define MC13783_LED_C0_ABMODE(x) (((x) & 0x7) << 11) | |
133 | #define MC13783_LED_C0_ABREF(x) (((x) & 0x3) << 14) | |
01a7a063 | 134 | /* MC13783 LED Control 1 */ |
9d263813 AS |
135 | #define MC13783_LED_C1_TC1HALF (1 << 18) |
136 | #define MC13783_LED_C1_SLEWLIM (1 << 23) | |
01a7a063 AS |
137 | /* MC13783 LED Control 2 */ |
138 | #define MC13783_LED_C2_CURRENT_MD(x) (((x) & 0x7) << 0) | |
139 | #define MC13783_LED_C2_CURRENT_AD(x) (((x) & 0x7) << 3) | |
140 | #define MC13783_LED_C2_CURRENT_KP(x) (((x) & 0x7) << 6) | |
9d263813 AS |
141 | #define MC13783_LED_C2_PERIOD(x) (((x) & 0x3) << 21) |
142 | #define MC13783_LED_C2_SLEWLIM (1 << 23) | |
01a7a063 AS |
143 | /* MC13783 LED Control 3 */ |
144 | #define MC13783_LED_C3_CURRENT_R1(x) (((x) & 0x3) << 0) | |
145 | #define MC13783_LED_C3_CURRENT_G1(x) (((x) & 0x3) << 2) | |
146 | #define MC13783_LED_C3_CURRENT_B1(x) (((x) & 0x3) << 4) | |
9d263813 AS |
147 | #define MC13783_LED_C3_PERIOD(x) (((x) & 0x3) << 21) |
148 | #define MC13783_LED_C3_TRIODE_TC1 (1 << 23) | |
01a7a063 AS |
149 | /* MC13783 LED Control 4 */ |
150 | #define MC13783_LED_C4_CURRENT_R2(x) (((x) & 0x3) << 0) | |
151 | #define MC13783_LED_C4_CURRENT_G2(x) (((x) & 0x3) << 2) | |
152 | #define MC13783_LED_C4_CURRENT_B2(x) (((x) & 0x3) << 4) | |
9d263813 AS |
153 | #define MC13783_LED_C4_PERIOD(x) (((x) & 0x3) << 21) |
154 | #define MC13783_LED_C4_TRIODE_TC2 (1 << 23) | |
01a7a063 AS |
155 | /* MC13783 LED Control 5 */ |
156 | #define MC13783_LED_C5_CURRENT_R3(x) (((x) & 0x3) << 0) | |
157 | #define MC13783_LED_C5_CURRENT_G3(x) (((x) & 0x3) << 2) | |
158 | #define MC13783_LED_C5_CURRENT_B3(x) (((x) & 0x3) << 4) | |
9d263813 AS |
159 | #define MC13783_LED_C5_PERIOD(x) (((x) & 0x3) << 21) |
160 | #define MC13783_LED_C5_TRIODE_TC3 (1 << 23) | |
01a7a063 AS |
161 | /* MC13892 LED Control 0 */ |
162 | #define MC13892_LED_C0_CURRENT_MD(x) (((x) & 0x7) << 9) | |
163 | #define MC13892_LED_C0_CURRENT_AD(x) (((x) & 0x7) << 21) | |
164 | /* MC13892 LED Control 1 */ | |
165 | #define MC13892_LED_C1_CURRENT_KP(x) (((x) & 0x7) << 9) | |
166 | /* MC13892 LED Control 2 */ | |
167 | #define MC13892_LED_C2_CURRENT_R(x) (((x) & 0x7) << 9) | |
168 | #define MC13892_LED_C2_CURRENT_G(x) (((x) & 0x7) << 21) | |
169 | /* MC13892 LED Control 3 */ | |
170 | #define MC13892_LED_C3_CURRENT_B(x) (((x) & 0x7) << 9) | |
a59ce658 AS |
171 | /* MC34708 LED Control 0 */ |
172 | #define MC34708_LED_C0_CURRENT_R(x) (((x) & 0x3) << 9) | |
173 | #define MC34708_LED_C0_CURRENT_G(x) (((x) & 0x3) << 21) | |
d09b711a AS |
174 | |
175 | struct mc13xxx_leds_platform_data { | |
176 | struct mc13xxx_led_platform_data *led; | |
177 | int num_leds; | |
9d263813 | 178 | u32 led_control[MAX_LED_CONTROL_REGS]; |
8e005935 UKK |
179 | }; |
180 | ||
30fc7ac3 PR |
181 | #define MC13783_BUTTON_DBNC_0MS 0 |
182 | #define MC13783_BUTTON_DBNC_30MS 1 | |
183 | #define MC13783_BUTTON_DBNC_150MS 2 | |
184 | #define MC13783_BUTTON_DBNC_750MS 3 | |
185 | #define MC13783_BUTTON_ENABLE (1 << 2) | |
186 | #define MC13783_BUTTON_POL_INVERT (1 << 3) | |
187 | #define MC13783_BUTTON_RESET_EN (1 << 4) | |
d09b711a AS |
188 | |
189 | struct mc13xxx_buttons_platform_data { | |
30fc7ac3 PR |
190 | int b1on_flags; |
191 | unsigned short b1on_key; | |
192 | int b2on_flags; | |
193 | unsigned short b2on_key; | |
194 | int b3on_flags; | |
195 | unsigned short b3on_key; | |
196 | }; | |
197 | ||
d09b711a AS |
198 | #define MC13783_TS_ATO_FIRST false |
199 | #define MC13783_TS_ATO_EACH true | |
200 | ||
1039d762 MT |
201 | struct mc13xxx_ts_platform_data { |
202 | /* Delay between Touchscreen polarization and ADC Conversion. | |
203 | * Given in clock ticks of a 32 kHz clock which gives a granularity of | |
204 | * about 30.5ms */ | |
205 | u8 ato; | |
1039d762 MT |
206 | /* Use the ATO delay only for the first conversion or for each one */ |
207 | bool atox; | |
208 | }; | |
209 | ||
e3a0871c PR |
210 | enum mc13783_ssi_port { |
211 | MC13783_SSI1_PORT, | |
212 | MC13783_SSI2_PORT, | |
213 | }; | |
214 | ||
215 | struct mc13xxx_codec_platform_data { | |
216 | enum mc13783_ssi_port adc_ssi_port; | |
217 | enum mc13783_ssi_port dac_ssi_port; | |
218 | }; | |
219 | ||
d09b711a | 220 | #define MC13XXX_USE_TOUCHSCREEN (1 << 0) |
8e005935 UKK |
221 | #define MC13XXX_USE_CODEC (1 << 1) |
222 | #define MC13XXX_USE_ADC (1 << 2) | |
223 | #define MC13XXX_USE_RTC (1 << 3) | |
d09b711a AS |
224 | |
225 | struct mc13xxx_platform_data { | |
8e005935 UKK |
226 | unsigned int flags; |
227 | ||
4ec1b54c | 228 | struct mc13xxx_regulator_platform_data regulators; |
8e005935 | 229 | struct mc13xxx_leds_platform_data *leds; |
30fc7ac3 | 230 | struct mc13xxx_buttons_platform_data *buttons; |
1039d762 | 231 | struct mc13xxx_ts_platform_data touch; |
e3a0871c | 232 | struct mc13xxx_codec_platform_data *codec; |
8e005935 UKK |
233 | }; |
234 | ||
fec316d6 UKK |
235 | #define MC13XXX_ADC_MODE_TS 1 |
236 | #define MC13XXX_ADC_MODE_SINGLE_CHAN 2 | |
237 | #define MC13XXX_ADC_MODE_MULT_CHAN 3 | |
238 | ||
239 | #define MC13XXX_ADC0 43 | |
2161891a RG |
240 | #define MC13XXX_ADC0_LICELLCON (1 << 0) |
241 | #define MC13XXX_ADC0_CHRGICON (1 << 1) | |
242 | #define MC13XXX_ADC0_BATICON (1 << 2) | |
ed645ccc AG |
243 | #define MC13XXX_ADC0_ADIN7SEL_DIE (1 << 4) |
244 | #define MC13XXX_ADC0_ADIN7SEL_UID (2 << 4) | |
fec316d6 UKK |
245 | #define MC13XXX_ADC0_ADREFEN (1 << 10) |
246 | #define MC13XXX_ADC0_TSMOD0 (1 << 12) | |
247 | #define MC13XXX_ADC0_TSMOD1 (1 << 13) | |
248 | #define MC13XXX_ADC0_TSMOD2 (1 << 14) | |
55143439 | 249 | #define MC13XXX_ADC0_CHRGRAWDIV (1 << 15) |
fec316d6 UKK |
250 | #define MC13XXX_ADC0_ADINC1 (1 << 16) |
251 | #define MC13XXX_ADC0_ADINC2 (1 << 17) | |
252 | ||
253 | #define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \ | |
254 | MC13XXX_ADC0_TSMOD1 | \ | |
255 | MC13XXX_ADC0_TSMOD2) | |
256 | ||
2161891a RG |
257 | #define MC13XXX_ADC0_CONFIG_MASK (MC13XXX_ADC0_TSMOD_MASK | \ |
258 | MC13XXX_ADC0_LICELLCON | \ | |
259 | MC13XXX_ADC0_CHRGICON | \ | |
260 | MC13XXX_ADC0_BATICON) | |
261 | ||
8e005935 | 262 | #endif /* ifndef __LINUX_MFD_MC13XXX_H */ |