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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
470eca47 MK |
2 | /* |
3 | * TI/National Semiconductor LP3943 Device | |
4 | * | |
5 | * Copyright 2013 Texas Instruments | |
6 | * | |
7 | * Author: Milo Kim <milo.kim@ti.com> | |
470eca47 MK |
8 | */ |
9 | ||
10 | #ifndef __MFD_LP3943_H__ | |
11 | #define __MFD_LP3943_H__ | |
12 | ||
13 | #include <linux/gpio.h> | |
14 | #include <linux/pwm.h> | |
15 | #include <linux/regmap.h> | |
16 | ||
17 | /* Registers */ | |
18 | #define LP3943_REG_GPIO_A 0x00 | |
19 | #define LP3943_REG_GPIO_B 0x01 | |
20 | #define LP3943_REG_PRESCALE0 0x02 | |
21 | #define LP3943_REG_PWM0 0x03 | |
22 | #define LP3943_REG_PRESCALE1 0x04 | |
23 | #define LP3943_REG_PWM1 0x05 | |
24 | #define LP3943_REG_MUX0 0x06 | |
25 | #define LP3943_REG_MUX1 0x07 | |
26 | #define LP3943_REG_MUX2 0x08 | |
27 | #define LP3943_REG_MUX3 0x09 | |
28 | ||
29 | /* Bit description for LP3943_REG_MUX0 ~ 3 */ | |
30 | #define LP3943_GPIO_IN 0x00 | |
31 | #define LP3943_GPIO_OUT_HIGH 0x00 | |
32 | #define LP3943_GPIO_OUT_LOW 0x01 | |
33 | #define LP3943_DIM_PWM0 0x02 | |
34 | #define LP3943_DIM_PWM1 0x03 | |
35 | ||
36 | #define LP3943_NUM_PWMS 2 | |
37 | ||
38 | enum lp3943_pwm_output { | |
39 | LP3943_PWM_OUT0, | |
40 | LP3943_PWM_OUT1, | |
41 | LP3943_PWM_OUT2, | |
42 | LP3943_PWM_OUT3, | |
43 | LP3943_PWM_OUT4, | |
44 | LP3943_PWM_OUT5, | |
45 | LP3943_PWM_OUT6, | |
46 | LP3943_PWM_OUT7, | |
47 | LP3943_PWM_OUT8, | |
48 | LP3943_PWM_OUT9, | |
49 | LP3943_PWM_OUT10, | |
50 | LP3943_PWM_OUT11, | |
51 | LP3943_PWM_OUT12, | |
52 | LP3943_PWM_OUT13, | |
53 | LP3943_PWM_OUT14, | |
54 | LP3943_PWM_OUT15, | |
55 | }; | |
56 | ||
57 | /* | |
58 | * struct lp3943_pwm_map | |
59 | * @output: Output pins which are mapped to each PWM channel | |
60 | * @num_outputs: Number of outputs | |
61 | */ | |
62 | struct lp3943_pwm_map { | |
63 | enum lp3943_pwm_output *output; | |
64 | int num_outputs; | |
65 | }; | |
66 | ||
67 | /* | |
68 | * struct lp3943_platform_data | |
69 | * @pwms: Output channel definitions for PWM channel 0 and 1 | |
70 | */ | |
71 | struct lp3943_platform_data { | |
72 | struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS]; | |
73 | }; | |
74 | ||
75 | /* | |
76 | * struct lp3943_reg_cfg | |
77 | * @reg: Register address | |
78 | * @mask: Register bit mask to be updated | |
79 | * @shift: Register bit shift | |
80 | */ | |
81 | struct lp3943_reg_cfg { | |
82 | u8 reg; | |
83 | u8 mask; | |
84 | u8 shift; | |
85 | }; | |
86 | ||
87 | /* | |
88 | * struct lp3943 | |
89 | * @dev: Parent device pointer | |
90 | * @regmap: Used for I2C communication on accessing registers | |
91 | * @pdata: LP3943 platform specific data | |
92 | * @mux_cfg: Register configuration for pin MUX | |
93 | * @pin_used: Bit mask for output pin used. | |
94 | * This bitmask is used for pin assignment management. | |
95 | * 1 = pin used, 0 = available. | |
96 | * Only LSB 16 bits are used, but it is unsigned long type | |
97 | * for atomic bitwise operations. | |
98 | */ | |
99 | struct lp3943 { | |
100 | struct device *dev; | |
101 | struct regmap *regmap; | |
102 | struct lp3943_platform_data *pdata; | |
103 | const struct lp3943_reg_cfg *mux_cfg; | |
104 | unsigned long pin_used; | |
105 | }; | |
106 | ||
107 | int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read); | |
108 | int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data); | |
109 | int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); | |
110 | #endif |