[linux-block.git] / include / linux / mfd / dbx500-prcmu.h

/*
 * Copyright (C) ST Ericsson SA 2011
 *
 * License Terms: GNU General Public License v2
 *
 * STE Ux500 PRCMU API
 */
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H

#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>

/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
	PRCMU_WAKEUP_INDEX_RTC,
	PRCMU_WAKEUP_INDEX_RTT0,
	PRCMU_WAKEUP_INDEX_RTT1,
	PRCMU_WAKEUP_INDEX_HSI0,
	PRCMU_WAKEUP_INDEX_HSI1,
	PRCMU_WAKEUP_INDEX_USB,
	PRCMU_WAKEUP_INDEX_ABB,
	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	PRCMU_WAKEUP_INDEX_ARM,
	PRCMU_WAKEUP_INDEX_CD_IRQ,
	NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))

/* EPOD (power domain) IDs */

/*
 * DB8500 EPODs
 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
 * - EPOD_ID_SGA: power domain for SGA
 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
 * - NUM_EPOD_ID: number of power domains
 *
 * TODO: These should be prefixed.
 */
#define EPOD_ID_SVAMMDSP	0
#define EPOD_ID_SVAPIPE		1
#define EPOD_ID_SIAMMDSP	2
#define EPOD_ID_SIAPIPE		3
#define EPOD_ID_SGA		4
#define EPOD_ID_B2R2_MCDE	5
#define EPOD_ID_ESRAM12		6
#define EPOD_ID_ESRAM34		7
#define NUM_EPOD_ID		8

/*
 * state definition for EPOD (power domain)
 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
 * - EPOD_STATE_OFF: The EPOD is switched off
 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
 *                         retention
 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
 * - EPOD_STATE_ON: Same as above, but with clock enabled
 */
#define EPOD_STATE_NO_CHANGE	0x00
#define EPOD_STATE_OFF		0x01
#define EPOD_STATE_RAMRET	0x02
#define EPOD_STATE_ON_CLK_OFF	0x03
#define EPOD_STATE_ON		0x04

/*
 * CLKOUT sources
 */
#define PRCMU_CLKSRC_CLK38M		0x00
#define PRCMU_CLKSRC_ACLK		0x01
#define PRCMU_CLKSRC_SYSCLK		0x02
#define PRCMU_CLKSRC_LCDCLK		0x03
#define PRCMU_CLKSRC_SDMMCCLK		0x04
#define PRCMU_CLKSRC_TVCLK		0x05
#define PRCMU_CLKSRC_TIMCLK		0x06
#define PRCMU_CLKSRC_CLK009		0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK	0x40
#define PRCMU_CLKSRC_I2CCLK		0x41
#define PRCMU_CLKSRC_MSP02CLK		0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK	0x43
#define PRCMU_CLKSRC_HSIRXCLK		0x44
#define PRCMU_CLKSRC_HSITXCLK		0x45
#define PRCMU_CLKSRC_ARMCLKFIX		0x46
#define PRCMU_CLKSRC_HDMICLK		0x47

/*
 * Clock identifiers.
 */
enum prcmu_clock {
	PRCMU_SGACLK,
	PRCMU_UARTCLK,
	PRCMU_MSP02CLK,
	PRCMU_MSP1CLK,
	PRCMU_I2CCLK,
	PRCMU_SDMMCCLK,
	PRCMU_SPARE1CLK,
	PRCMU_SLIMCLK,
	PRCMU_PER1CLK,
	PRCMU_PER2CLK,
	PRCMU_PER3CLK,
	PRCMU_PER5CLK,
	PRCMU_PER6CLK,
	PRCMU_PER7CLK,
	PRCMU_LCDCLK,
	PRCMU_BMLCLK,
	PRCMU_HSITXCLK,
	PRCMU_HSIRXCLK,
	PRCMU_HDMICLK,
	PRCMU_APEATCLK,
	PRCMU_APETRACECLK,
	PRCMU_MCDECLK,
	PRCMU_IPI2CCLK,
	PRCMU_DSIALTCLK,
	PRCMU_DMACLK,
	PRCMU_B2R2CLK,
	PRCMU_TVCLK,
	PRCMU_SSPCLK,
	PRCMU_RNGCLK,
	PRCMU_UICCCLK,
	PRCMU_PWMCLK,
	PRCMU_IRDACLK,
	PRCMU_IRRCCLK,
	PRCMU_SIACLK,
	PRCMU_SVACLK,
	PRCMU_ACLK,
	PRCMU_NUM_REG_CLOCKS,
	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
	PRCMU_CDCLK,
	PRCMU_TIMCLK,
	PRCMU_PLLSOC0,
	PRCMU_PLLSOC1,
	PRCMU_ARMSS,
	PRCMU_PLLDDR,
	PRCMU_PLLDSI,
	PRCMU_DSI0CLK,
	PRCMU_DSI1CLK,
	PRCMU_DSI0ESCCLK,
	PRCMU_DSI1ESCCLK,
	PRCMU_DSI2ESCCLK,
};

/**
 * enum ape_opp - APE OPP states definition
 * @APE_OPP_INIT:
 * @APE_NO_CHANGE: The APE operating point is unchanged
 * @APE_100_OPP: The new APE operating point is ape100opp
 * @APE_50_OPP: 50%
 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
 */
enum ape_opp {
	APE_OPP_INIT = 0x00,
	APE_NO_CHANGE = 0x01,
	APE_100_OPP = 0x02,
	APE_50_OPP = 0x03,
	APE_50_PARTLY_25_OPP = 0xFF,
};

/**
 * enum arm_opp - ARM OPP states definition
 * @ARM_OPP_INIT:
 * @ARM_NO_CHANGE: The ARM operating point is unchanged
 * @ARM_100_OPP: The new ARM operating point is arm100opp
 * @ARM_50_OPP: The new ARM operating point is arm50opp
 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
 * @ARM_EXTCLK: The new ARM operating point is armExtClk
 */
enum arm_opp {
	ARM_OPP_INIT = 0x00,
	ARM_NO_CHANGE = 0x01,
	ARM_100_OPP = 0x02,
	ARM_50_OPP = 0x03,
	ARM_MAX_OPP = 0x04,
	ARM_MAX_FREQ100OPP = 0x05,
	ARM_EXTCLK = 0x07
};

/**
 * enum ddr_opp - DDR OPP states definition
 * @DDR_100_OPP: The new DDR operating point is ddr100opp
 * @DDR_50_OPP: The new DDR operating point is ddr50opp
 * @DDR_25_OPP: The new DDR operating point is ddr25opp
 */
enum ddr_opp {
	DDR_100_OPP = 0x00,
	DDR_50_OPP = 0x01,
	DDR_25_OPP = 0x02,
};

/*
 * Definitions for controlling ESRAM0 in deep sleep.
 */
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2

/**
 * enum ddr_pwrst - DDR power states definition
 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
 * @DDR_PWR_STATE_ON:
 * @DDR_PWR_STATE_OFFLOWLAT:
 * @DDR_PWR_STATE_OFFHIGHLAT:
 */
enum ddr_pwrst {
	DDR_PWR_STATE_UNCHANGED     = 0x00,
	DDR_PWR_STATE_ON            = 0x01,
	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
};

#include <linux/mfd/db8500-prcmu.h>

#if defined(CONFIG_UX500_SOC_DB8500)

static inline void __init prcmu_early_init(void)
{
	return db8500_prcmu_early_init();
}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
		bool keep_ap_pll)
{
	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
		keep_ap_pll);
}

static inline u8 prcmu_get_power_state_result(void)
{
	return db8500_prcmu_get_power_state_result();
}

static inline int prcmu_gic_decouple(void)
{
	return db8500_prcmu_gic_decouple();
}

static inline int prcmu_gic_recouple(void)
{
	return db8500_prcmu_gic_recouple();
}

static inline bool prcmu_gic_pending_irq(void)
{
	return db8500_prcmu_gic_pending_irq();
}

static inline bool prcmu_is_cpu_in_wfi(int cpu)
{
	return db8500_prcmu_is_cpu_in_wfi(cpu);
}

static inline int prcmu_copy_gic_settings(void)
{
	return db8500_prcmu_copy_gic_settings();
}

static inline bool prcmu_pending_irq(void)
{
	return db8500_prcmu_pending_irq();
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return db8500_prcmu_set_epod(epod_id, epod_state);
}

static inline void prcmu_enable_wakeups(u32 wakeups)
{
	db8500_prcmu_enable_wakeups(wakeups);
}

static inline void prcmu_disable_wakeups(void)
{
	prcmu_enable_wakeups(0);
}

static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
	db8500_prcmu_config_abb_event_readout(abb_events);
}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	db8500_prcmu_get_abb_event_buffer(buf);
}

int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);

int prcmu_config_clkout(u8 clkout, u8 source, u8 div);

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return db8500_prcmu_request_clock(clock, enable);
}

unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);

static inline int prcmu_set_ddr_opp(u8 opp)
{
	return db8500_prcmu_set_ddr_opp(opp);
}
static inline int prcmu_get_ddr_opp(void)
{
	return db8500_prcmu_get_ddr_opp();
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return db8500_prcmu_set_arm_opp(opp);
}

static inline int prcmu_get_arm_opp(void)
{
	return db8500_prcmu_get_arm_opp();
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return db8500_prcmu_set_ape_opp(opp);
}

static inline int prcmu_get_ape_opp(void)
{
	return db8500_prcmu_get_ape_opp();
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return db8500_prcmu_request_ape_opp_100_voltage(enable);
}

static inline void prcmu_system_reset(u16 reset_code)
{
	return db8500_prcmu_system_reset(reset_code);
}

static inline u16 prcmu_get_reset_code(void)
{
	return db8500_prcmu_get_reset_code();
}

int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
	return db8500_prcmu_modem_reset();
}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return db8500_prcmu_is_ac_wake_requested();
}

static inline int prcmu_set_display_clocks(void)
{
	return db8500_prcmu_set_display_clocks();
}

static inline int prcmu_disable_dsipll(void)
{
	return db8500_prcmu_disable_dsipll();
}

static inline int prcmu_enable_dsipll(void)
{
	return db8500_prcmu_enable_dsipll();
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return db8500_prcmu_config_esram0_deep_sleep(state);
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return db8500_prcmu_config_hotdog(threshold);
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return db8500_prcmu_config_hotmon(low, high);
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return  db8500_prcmu_start_temp_sense(cycles32k);
}

static inline int prcmu_stop_temp_sense(void)
{
	return  db8500_prcmu_stop_temp_sense();
}

static inline u32 prcmu_read(unsigned int reg)
{
	return db8500_prcmu_read(reg);
}

static inline void prcmu_write(unsigned int reg, u32 value)
{
	db8500_prcmu_write(reg, value);
}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
	db8500_prcmu_write_masked(reg, mask, value);
}

static inline int prcmu_enable_a9wdog(u8 id)
{
	return db8500_prcmu_enable_a9wdog(id);
}

static inline int prcmu_disable_a9wdog(u8 id)
{
	return db8500_prcmu_disable_a9wdog(id);
}

static inline int prcmu_kick_a9wdog(u8 id)
{
	return db8500_prcmu_kick_a9wdog(id);
}

static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
	return db8500_prcmu_load_a9wdog(id, timeout);
}

static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else

static inline void __init prcmu_early_init(void) {}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	bool keep_ap_pll)
{
	return 0;
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return 0;
}

static inline void prcmu_enable_wakeups(u32 wakeups) {}

static inline void prcmu_disable_wakeups(void) {}

static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
	u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
	return 0;
}

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return 0;
}

static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline unsigned long prcmu_clock_rate(u8 clock)
{
	return 0;
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_ape_opp(void)
{
	return APE_100_OPP;
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return 0;
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_arm_opp(void)
{
	return ARM_100_OPP;
}

static inline int prcmu_set_ddr_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_ddr_opp(void)
{
	return DDR_100_OPP;
}

static inline void prcmu_system_reset(u16 reset_code) {}

static inline u16 prcmu_get_reset_code(void)
{
	return 0;
}

static inline int prcmu_ac_wake_req(void)
{
	return 0;
}

static inline void prcmu_ac_sleep_req(void) {}

static inline void prcmu_modem_reset(void) {}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return false;
}

static inline int prcmu_set_display_clocks(void)
{
	return 0;
}

static inline int prcmu_disable_dsipll(void)
{
	return 0;
}

static inline int prcmu_enable_dsipll(void)
{
	return 0;
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return 0;
}

static inline void prcmu_config_abb_event_readout(u32 abb_events) {}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	*buf = NULL;
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return 0;
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return 0;
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return 0;
}

static inline int prcmu_stop_temp_sense(void)
{
	return 0;
}

static inline u32 prcmu_read(unsigned int reg)
{
	return 0;
}

static inline void prcmu_write(unsigned int reg, u32 value) {}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}

#endif

static inline void prcmu_set(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, bits);
}

static inline void prcmu_clear(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, 0);
}

/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1

#ifdef CONFIG_DBX500_PRCMU_QOS_POWER

unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
void prcmu_qos_force_opp(int, s32);
int prcmu_qos_requirement(int pm_qos_class);
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
int prcmu_qos_add_notifier(int prcmu_qos_class,
			   struct notifier_block *notifier);
int prcmu_qos_remove_notifier(int prcmu_qos_class,
			      struct notifier_block *notifier);

#else

static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
{
	return 0;
}

static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}

static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}

static inline int prcmu_qos_requirement(int prcmu_qos_class)
{
	return 0;
}

static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
					    char *name, s32 value)
{
	return 0;
}

static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
					       char *name, s32 new_value)
{
	return 0;
}

static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}

static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
					 struct notifier_block *notifier)
{
	return 0;
}
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
					    struct notifier_block *notifier)
{
	return 0;
}

#endif

#endif /* __MACH_PRCMU_H */
Commit	Line	Data
fea799e3 MN	1	/*
	2	* Copyright (C) ST Ericsson SA 2011
	3	*
	4	* License Terms: GNU General Public License v2
	5	*
	6	* STE Ux500 PRCMU API
	7	*/
	8	#ifndef __MACH_PRCMU_H
	9	#define __MACH_PRCMU_H
	10
	11	#include <linux/interrupt.h>
	12	#include <linux/notifier.h>
0508901c	13	#include <linux/err.h>
fea799e3 MN	14
	15	/* PRCMU Wakeup defines */
	16	enum prcmu_wakeup_index {
	17	PRCMU_WAKEUP_INDEX_RTC,
	18	PRCMU_WAKEUP_INDEX_RTT0,
	19	PRCMU_WAKEUP_INDEX_RTT1,
	20	PRCMU_WAKEUP_INDEX_HSI0,
	21	PRCMU_WAKEUP_INDEX_HSI1,
	22	PRCMU_WAKEUP_INDEX_USB,
	23	PRCMU_WAKEUP_INDEX_ABB,
	24	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	25	PRCMU_WAKEUP_INDEX_ARM,
	26	PRCMU_WAKEUP_INDEX_CD_IRQ,
	27	NUM_PRCMU_WAKEUP_INDICES
	28	};
	29	#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
	30
	31	/* EPOD (power domain) IDs */
	32
	33	/*
	34	* DB8500 EPODs
	35	* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
	36	* - EPOD_ID_SVAPIPE: power domain for SVA pipe
	37	* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
	38	* - EPOD_ID_SIAPIPE: power domain for SIA pipe
	39	* - EPOD_ID_SGA: power domain for SGA
	40	* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
	41	* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
	42	* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
	43	* - NUM_EPOD_ID: number of power domains
	44	*
	45	* TODO: These should be prefixed.
	46	*/
	47	#define EPOD_ID_SVAMMDSP 0
	48	#define EPOD_ID_SVAPIPE 1
	49	#define EPOD_ID_SIAMMDSP 2
	50	#define EPOD_ID_SIAPIPE 3
	51	#define EPOD_ID_SGA 4
	52	#define EPOD_ID_B2R2_MCDE 5
	53	#define EPOD_ID_ESRAM12 6
	54	#define EPOD_ID_ESRAM34 7
	55	#define NUM_EPOD_ID 8
	56
fea799e3 MN	57	/*
	58	* state definition for EPOD (power domain)
	59	* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
	60	* - EPOD_STATE_OFF: The EPOD is switched off
	61	* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
	62	* retention
	63	* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
	64	* - EPOD_STATE_ON: Same as above, but with clock enabled
	65	*/
	66	#define EPOD_STATE_NO_CHANGE 0x00
	67	#define EPOD_STATE_OFF 0x01
	68	#define EPOD_STATE_RAMRET 0x02
	69	#define EPOD_STATE_ON_CLK_OFF 0x03
	70	#define EPOD_STATE_ON 0x04
	71
	72	/*
	73	* CLKOUT sources
	74	*/
	75	#define PRCMU_CLKSRC_CLK38M 0x00
	76	#define PRCMU_CLKSRC_ACLK 0x01
	77	#define PRCMU_CLKSRC_SYSCLK 0x02
	78	#define PRCMU_CLKSRC_LCDCLK 0x03
	79	#define PRCMU_CLKSRC_SDMMCCLK 0x04
	80	#define PRCMU_CLKSRC_TVCLK 0x05
	81	#define PRCMU_CLKSRC_TIMCLK 0x06
	82	#define PRCMU_CLKSRC_CLK009 0x07
	83	/* These are only valid for CLKOUT1: */
	84	#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
	85	#define PRCMU_CLKSRC_I2CCLK 0x41
	86	#define PRCMU_CLKSRC_MSP02CLK 0x42
	87	#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
	88	#define PRCMU_CLKSRC_HSIRXCLK 0x44
	89	#define PRCMU_CLKSRC_HSITXCLK 0x45
	90	#define PRCMU_CLKSRC_ARMCLKFIX 0x46
	91	#define PRCMU_CLKSRC_HDMICLK 0x47
	92
	93	/*
	94	* Clock identifiers.
	95	*/
	96	enum prcmu_clock {
	97	PRCMU_SGACLK,
	98	PRCMU_UARTCLK,
	99	PRCMU_MSP02CLK,
	100	PRCMU_MSP1CLK,
	101	PRCMU_I2CCLK,
	102	PRCMU_SDMMCCLK,
6b6fae2b	103	PRCMU_SPARE1CLK,
fea799e3 MN	104	PRCMU_SLIMCLK,
	105	PRCMU_PER1CLK,
	106	PRCMU_PER2CLK,
	107	PRCMU_PER3CLK,
	108	PRCMU_PER5CLK,
	109	PRCMU_PER6CLK,
	110	PRCMU_PER7CLK,
	111	PRCMU_LCDCLK,
	112	PRCMU_BMLCLK,
	113	PRCMU_HSITXCLK,
	114	PRCMU_HSIRXCLK,
	115	PRCMU_HDMICLK,
	116	PRCMU_APEATCLK,
	117	PRCMU_APETRACECLK,
	118	PRCMU_MCDECLK,
	119	PRCMU_IPI2CCLK,
	120	PRCMU_DSIALTCLK,
	121	PRCMU_DMACLK,
	122	PRCMU_B2R2CLK,
	123	PRCMU_TVCLK,
	124	PRCMU_SSPCLK,
	125	PRCMU_RNGCLK,
	126	PRCMU_UICCCLK,
	127	PRCMU_PWMCLK,
	128	PRCMU_IRDACLK,
	129	PRCMU_IRRCCLK,
	130	PRCMU_SIACLK,
	131	PRCMU_SVACLK,
6b6fae2b	132	PRCMU_ACLK,
fea799e3 MN	133	PRCMU_NUM_REG_CLOCKS,
fea799e3 MN	134	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
6b6fae2b	135	PRCMU_CDCLK,
fea799e3 MN	136	PRCMU_TIMCLK,
	137	PRCMU_PLLSOC0,
	138	PRCMU_PLLSOC1,
20aee5b6	139	PRCMU_ARMSS,
fea799e3	140	PRCMU_PLLDDR,
6b6fae2b MN	141	PRCMU_PLLDSI,
	142	PRCMU_DSI0CLK,
	143	PRCMU_DSI1CLK,
	144	PRCMU_DSI0ESCCLK,
	145	PRCMU_DSI1ESCCLK,
	146	PRCMU_DSI2ESCCLK,
fea799e3 MN	147	};
	148
	149	/**
	150	* enum ape_opp - APE OPP states definition
	151	* @APE_OPP_INIT:
	152	* @APE_NO_CHANGE: The APE operating point is unchanged
	153	* @APE_100_OPP: The new APE operating point is ape100opp
	154	* @APE_50_OPP: 50%
4d64d2e3	155	* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
fea799e3 MN	156	*/
	157	enum ape_opp {
	158	APE_OPP_INIT = 0x00,
	159	APE_NO_CHANGE = 0x01,
	160	APE_100_OPP = 0x02,
4d64d2e3 MN	161	APE_50_OPP = 0x03,
4d64d2e3 MN	162	APE_50_PARTLY_25_OPP = 0xFF,
fea799e3 MN	163	};
	164
	165	/**
	166	* enum arm_opp - ARM OPP states definition
	167	* @ARM_OPP_INIT:
	168	* @ARM_NO_CHANGE: The ARM operating point is unchanged
	169	* @ARM_100_OPP: The new ARM operating point is arm100opp
	170	* @ARM_50_OPP: The new ARM operating point is arm50opp
	171	* @ARM_MAX_OPP: Operating point is "max" (more than 100)
	172	* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
	173	* @ARM_EXTCLK: The new ARM operating point is armExtClk
	174	*/
	175	enum arm_opp {
	176	ARM_OPP_INIT = 0x00,
	177	ARM_NO_CHANGE = 0x01,
	178	ARM_100_OPP = 0x02,
	179	ARM_50_OPP = 0x03,
	180	ARM_MAX_OPP = 0x04,
	181	ARM_MAX_FREQ100OPP = 0x05,
	182	ARM_EXTCLK = 0x07
	183	};
	184
	185	/**
	186	* enum ddr_opp - DDR OPP states definition
	187	* @DDR_100_OPP: The new DDR operating point is ddr100opp
	188	* @DDR_50_OPP: The new DDR operating point is ddr50opp
	189	* @DDR_25_OPP: The new DDR operating point is ddr25opp
	190	*/
	191	enum ddr_opp {
	192	DDR_100_OPP = 0x00,
	193	DDR_50_OPP = 0x01,
	194	DDR_25_OPP = 0x02,
	195	};
	196
	197	/*
	198	* Definitions for controlling ESRAM0 in deep sleep.
	199	*/
	200	#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
	201	#define ESRAM0_DEEP_SLEEP_STATE_RET 2
	202
	203	/**
	204	* enum ddr_pwrst - DDR power states definition
	205	* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
	206	* @DDR_PWR_STATE_ON:
	207	* @DDR_PWR_STATE_OFFLOWLAT:
	208	* @DDR_PWR_STATE_OFFHIGHLAT:
	209	*/
	210	enum ddr_pwrst {
	211	DDR_PWR_STATE_UNCHANGED = 0x00,
	212	DDR_PWR_STATE_ON = 0x01,
	213	DDR_PWR_STATE_OFFLOWLAT = 0x02,
	214	DDR_PWR_STATE_OFFHIGHLAT = 0x03
	215	};
	216
	217	#include <linux/mfd/db8500-prcmu.h>
fea799e3	218
dece3709	219	#if defined(CONFIG_UX500_SOC_DB8500)
fea799e3 MN	220
	221	static inline void __init prcmu_early_init(void)
	222	{
dece3709	223	return db8500_prcmu_early_init();
fea799e3 MN	224	}
	225
	226	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	227	bool keep_ap_pll)
	228	{
dece3709 LW	229	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
dece3709 LW	230	keep_ap_pll);
fea799e3 MN	231	}
fea799e3 MN	232
4d64d2e3 MN	233	static inline u8 prcmu_get_power_state_result(void)
4d64d2e3 MN	234	{
dece3709	235	return db8500_prcmu_get_power_state_result();
4d64d2e3 MN	236	}
4d64d2e3 MN	237
485540dc DL	238	static inline int prcmu_gic_decouple(void)
485540dc DL	239	{
dece3709	240	return db8500_prcmu_gic_decouple();
485540dc DL	241	}
	242
	243	static inline int prcmu_gic_recouple(void)
	244	{
dece3709	245	return db8500_prcmu_gic_recouple();
485540dc DL	246	}
485540dc DL	247
cc9a0f68 DL	248	static inline bool prcmu_gic_pending_irq(void)
cc9a0f68 DL	249	{
dece3709	250	return db8500_prcmu_gic_pending_irq();
cc9a0f68 DL	251	}
cc9a0f68 DL	252
34fe6f10 DL	253	static inline bool prcmu_is_cpu_in_wfi(int cpu)
34fe6f10 DL	254	{
dece3709	255	return db8500_prcmu_is_cpu_in_wfi(cpu);
34fe6f10 DL	256	}
34fe6f10 DL	257
9f60d33e DL	258	static inline int prcmu_copy_gic_settings(void)
9f60d33e DL	259	{
dece3709	260	return db8500_prcmu_copy_gic_settings();
9f60d33e DL	261	}
9f60d33e DL	262
9ab492e1 DL	263	static inline bool prcmu_pending_irq(void)
9ab492e1 DL	264	{
dece3709	265	return db8500_prcmu_pending_irq();
9ab492e1 DL	266	}
9ab492e1 DL	267
fea799e3 MN	268	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
fea799e3 MN	269	{
dece3709	270	return db8500_prcmu_set_epod(epod_id, epod_state);
fea799e3 MN	271	}
	272
	273	static inline void prcmu_enable_wakeups(u32 wakeups)
	274	{
dece3709	275	db8500_prcmu_enable_wakeups(wakeups);
fea799e3 MN	276	}
	277
	278	static inline void prcmu_disable_wakeups(void)
	279	{
	280	prcmu_enable_wakeups(0);
	281	}
	282
	283	static inline void prcmu_config_abb_event_readout(u32 abb_events)
	284	{
dece3709	285	db8500_prcmu_config_abb_event_readout(abb_events);
fea799e3 MN	286	}
	287
	288	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	289	{
dece3709	290	db8500_prcmu_get_abb_event_buffer(buf);
fea799e3 MN	291	}
	292
	293	int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
	294	int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
3c3e4898	295	int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask, u8 size);
fea799e3 MN	296
	297	int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
	298
	299	static inline int prcmu_request_clock(u8 clock, bool enable)
	300	{
dece3709	301	return db8500_prcmu_request_clock(clock, enable);
fea799e3 MN	302	}
fea799e3 MN	303
0508901c MN	304	unsigned long prcmu_clock_rate(u8 clock);
	305	long prcmu_round_clock_rate(u8 clock, unsigned long rate);
	306	int prcmu_set_clock_rate(u8 clock, unsigned long rate);
	307
	308	static inline int prcmu_set_ddr_opp(u8 opp)
	309	{
dece3709	310	return db8500_prcmu_set_ddr_opp(opp);
0508901c MN	311	}
	312	static inline int prcmu_get_ddr_opp(void)
	313	{
dece3709	314	return db8500_prcmu_get_ddr_opp();
0508901c	315	}
fea799e3 MN	316
	317	static inline int prcmu_set_arm_opp(u8 opp)
	318	{
dece3709	319	return db8500_prcmu_set_arm_opp(opp);
fea799e3 MN	320	}
	321
	322	static inline int prcmu_get_arm_opp(void)
	323	{
dece3709	324	return db8500_prcmu_get_arm_opp();
fea799e3 MN	325	}
fea799e3 MN	326
0508901c MN	327	static inline int prcmu_set_ape_opp(u8 opp)
0508901c MN	328	{
dece3709	329	return db8500_prcmu_set_ape_opp(opp);
0508901c MN	330	}
	331
	332	static inline int prcmu_get_ape_opp(void)
	333	{
dece3709	334	return db8500_prcmu_get_ape_opp();
0508901c MN	335	}
0508901c MN	336
686f871b UH	337	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	338	{
	339	return db8500_prcmu_request_ape_opp_100_voltage(enable);
	340	}
	341
fea799e3 MN	342	static inline void prcmu_system_reset(u16 reset_code)
fea799e3 MN	343	{
dece3709	344	return db8500_prcmu_system_reset(reset_code);
fea799e3 MN	345	}
	346
	347	static inline u16 prcmu_get_reset_code(void)
	348	{
dece3709	349	return db8500_prcmu_get_reset_code();
fea799e3 MN	350	}
fea799e3 MN	351
5261e101	352	int prcmu_ac_wake_req(void);
fea799e3	353	void prcmu_ac_sleep_req(void);
0508901c MN	354	static inline void prcmu_modem_reset(void)
0508901c MN	355	{
dece3709	356	return db8500_prcmu_modem_reset();
0508901c MN	357	}
0508901c MN	358
fea799e3 MN	359	static inline bool prcmu_is_ac_wake_requested(void)
fea799e3 MN	360	{
dece3709	361	return db8500_prcmu_is_ac_wake_requested();
fea799e3 MN	362	}
	363
	364	static inline int prcmu_set_display_clocks(void)
	365	{
dece3709	366	return db8500_prcmu_set_display_clocks();
fea799e3 MN	367	}
	368
	369	static inline int prcmu_disable_dsipll(void)
	370	{
dece3709	371	return db8500_prcmu_disable_dsipll();
fea799e3 MN	372	}
	373
	374	static inline int prcmu_enable_dsipll(void)
	375	{
dece3709	376	return db8500_prcmu_enable_dsipll();
fea799e3 MN	377	}
	378
	379	static inline int prcmu_config_esram0_deep_sleep(u8 state)
	380	{
dece3709	381	return db8500_prcmu_config_esram0_deep_sleep(state);
fea799e3	382	}
0508901c MN	383
	384	static inline int prcmu_config_hotdog(u8 threshold)
	385	{
dece3709	386	return db8500_prcmu_config_hotdog(threshold);
0508901c MN	387	}
	388
	389	static inline int prcmu_config_hotmon(u8 low, u8 high)
	390	{
dece3709	391	return db8500_prcmu_config_hotmon(low, high);
0508901c MN	392	}
	393
	394	static inline int prcmu_start_temp_sense(u16 cycles32k)
	395	{
dece3709	396	return db8500_prcmu_start_temp_sense(cycles32k);
0508901c MN	397	}
	398
	399	static inline int prcmu_stop_temp_sense(void)
	400	{
dece3709	401	return db8500_prcmu_stop_temp_sense();
0508901c MN	402	}
0508901c MN	403
b4a6dbd5 MN	404	static inline u32 prcmu_read(unsigned int reg)
b4a6dbd5 MN	405	{
dece3709	406	return db8500_prcmu_read(reg);
b4a6dbd5 MN	407	}
	408
	409	static inline void prcmu_write(unsigned int reg, u32 value)
	410	{
dece3709	411	db8500_prcmu_write(reg, value);
b4a6dbd5 MN	412	}
	413
	414	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
	415	{
dece3709	416	db8500_prcmu_write_masked(reg, mask, value);
b4a6dbd5 MN	417	}
b4a6dbd5 MN	418
0508901c MN	419	static inline int prcmu_enable_a9wdog(u8 id)
0508901c MN	420	{
dece3709	421	return db8500_prcmu_enable_a9wdog(id);
0508901c MN	422	}
	423
	424	static inline int prcmu_disable_a9wdog(u8 id)
	425	{
dece3709	426	return db8500_prcmu_disable_a9wdog(id);
0508901c MN	427	}
	428
	429	static inline int prcmu_kick_a9wdog(u8 id)
	430	{
dece3709	431	return db8500_prcmu_kick_a9wdog(id);
0508901c MN	432	}
	433
	434	static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
	435	{
dece3709	436	return db8500_prcmu_load_a9wdog(id, timeout);
0508901c MN	437	}
	438
	439	static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
	440	{
dece3709	441	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
0508901c	442	}
fea799e3 MN	443	#else
	444
	445	static inline void __init prcmu_early_init(void) {}
	446
	447	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	448	bool keep_ap_pll)
	449	{
	450	return 0;
	451	}
	452
	453	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
	454	{
	455	return 0;
	456	}
	457
	458	static inline void prcmu_enable_wakeups(u32 wakeups) {}
	459
	460	static inline void prcmu_disable_wakeups(void) {}
	461
	462	static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
	463	{
	464	return -ENOSYS;
	465	}
	466
	467	static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
	468	{
	469	return -ENOSYS;
	470	}
	471
3c3e4898 MN	472	static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask,
	473	u8 size)
	474	{
	475	return -ENOSYS;
	476	}
	477
fea799e3 MN	478	static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
	479	{
	480	return 0;
	481	}
	482
	483	static inline int prcmu_request_clock(u8 clock, bool enable)
	484	{
	485	return 0;
6b6fae2b MN	486	}
	487
	488	static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
	489	{
	490	return 0;
	491	}
	492
	493	static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
	494	{
	495	return 0;
	496	}
	497
	498	static inline unsigned long prcmu_clock_rate(u8 clock)
	499	{
	500	return 0;
fea799e3 MN	501	}
	502
	503	static inline int prcmu_set_ape_opp(u8 opp)
	504	{
	505	return 0;
	506	}
	507
	508	static inline int prcmu_get_ape_opp(void)
	509	{
	510	return APE_100_OPP;
	511	}
	512
686f871b UH	513	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	514	{
	515	return 0;
	516	}
	517
fea799e3 MN	518	static inline int prcmu_set_arm_opp(u8 opp)
	519	{
	520	return 0;
	521	}
	522
	523	static inline int prcmu_get_arm_opp(void)
	524	{
	525	return ARM_100_OPP;
	526	}
	527
	528	static inline int prcmu_set_ddr_opp(u8 opp)
	529	{
	530	return 0;
	531	}
	532
	533	static inline int prcmu_get_ddr_opp(void)
	534	{
	535	return DDR_100_OPP;
	536	}
	537
	538	static inline void prcmu_system_reset(u16 reset_code) {}
	539
	540	static inline u16 prcmu_get_reset_code(void)
	541	{
	542	return 0;
	543	}
	544
5261e101 AM	545	static inline int prcmu_ac_wake_req(void)
	546	{
	547	return 0;
	548	}
fea799e3 MN	549
	550	static inline void prcmu_ac_sleep_req(void) {}
	551
	552	static inline void prcmu_modem_reset(void) {}
	553
	554	static inline bool prcmu_is_ac_wake_requested(void)
	555	{
	556	return false;
	557	}
	558
	559	static inline int prcmu_set_display_clocks(void)
	560	{
	561	return 0;
	562	}
	563
	564	static inline int prcmu_disable_dsipll(void)
	565	{
	566	return 0;
	567	}
	568
	569	static inline int prcmu_enable_dsipll(void)
	570	{
	571	return 0;
	572	}
	573
	574	static inline int prcmu_config_esram0_deep_sleep(u8 state)
	575	{
	576	return 0;
	577	}
	578
	579	static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
	580
	581	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	582	{
	583	*buf = NULL;
	584	}
	585
0508901c MN	586	static inline int prcmu_config_hotdog(u8 threshold)
	587	{
	588	return 0;
	589	}
	590
	591	static inline int prcmu_config_hotmon(u8 low, u8 high)
	592	{
	593	return 0;
	594	}
	595
	596	static inline int prcmu_start_temp_sense(u16 cycles32k)
	597	{
	598	return 0;
	599	}
	600
	601	static inline int prcmu_stop_temp_sense(void)
	602	{
	603	return 0;
	604	}
	605
b4a6dbd5 MN	606	static inline u32 prcmu_read(unsigned int reg)
	607	{
	608	return 0;
	609	}
	610
	611	static inline void prcmu_write(unsigned int reg, u32 value) {}
	612
	613	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
	614
	615	#endif
	616
	617	static inline void prcmu_set(unsigned int reg, u32 bits)
	618	{
	619	prcmu_write_masked(reg, bits, bits);
	620	}
	621
	622	static inline void prcmu_clear(unsigned int reg, u32 bits)
	623	{
	624	prcmu_write_masked(reg, bits, 0);
	625	}
	626
fea799e3 MN	627	/* PRCMU QoS APE OPP class */
	628	#define PRCMU_QOS_APE_OPP 1
	629	#define PRCMU_QOS_DDR_OPP 2
4d64d2e3	630	#define PRCMU_QOS_ARM_OPP 3
fea799e3 MN	631	#define PRCMU_QOS_DEFAULT_VALUE -1
fea799e3 MN	632
4d64d2e3	633	#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
fea799e3 MN	634
	635	unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
	636	void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
	637	void prcmu_qos_force_opp(int, s32);
	638	int prcmu_qos_requirement(int pm_qos_class);
	639	int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
	640	int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
	641	void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
	642	int prcmu_qos_add_notifier(int prcmu_qos_class,
	643	struct notifier_block *notifier);
	644	int prcmu_qos_remove_notifier(int prcmu_qos_class,
	645	struct notifier_block *notifier);
	646
	647	#else
	648
	649	static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
	650	{
	651	return 0;
	652	}
	653
	654	static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
	655
	656	static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
	657
	658	static inline int prcmu_qos_requirement(int prcmu_qos_class)
	659	{
	660	return 0;
	661	}
	662
	663	static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
	664	char *name, s32 value)
	665	{
	666	return 0;
	667	}
	668
	669	static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
	670	char *name, s32 new_value)
	671	{
	672	return 0;
	673	}
	674
	675	static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
	676	{
	677	}
	678
	679	static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
	680	struct notifier_block *notifier)
	681	{
	682	return 0;
	683	}
	684	static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
	685	struct notifier_block *notifier)
	686	{
	687	return 0;
	688	}
	689
	690	#endif
	691
	692	#endif /* __MACH_PRCMU_H */