[linux-block.git] / include / linux / mfd / dbx500-prcmu.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) ST Ericsson SA 2011
 *
 * STE Ux500 PRCMU API
 */
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H

#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>

#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */

/* Offset for the firmware version within the TCPM */
#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8

/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
	PRCMU_WAKEUP_INDEX_RTC,
	PRCMU_WAKEUP_INDEX_RTT0,
	PRCMU_WAKEUP_INDEX_RTT1,
	PRCMU_WAKEUP_INDEX_HSI0,
	PRCMU_WAKEUP_INDEX_HSI1,
	PRCMU_WAKEUP_INDEX_USB,
	PRCMU_WAKEUP_INDEX_ABB,
	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	PRCMU_WAKEUP_INDEX_ARM,
	PRCMU_WAKEUP_INDEX_CD_IRQ,
	NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))

/* EPOD (power domain) IDs */

/*
 * DB8500 EPODs
 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
 * - EPOD_ID_SGA: power domain for SGA
 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
 * - NUM_EPOD_ID: number of power domains
 *
 * TODO: These should be prefixed.
 */
#define EPOD_ID_SVAMMDSP	0
#define EPOD_ID_SVAPIPE		1
#define EPOD_ID_SIAMMDSP	2
#define EPOD_ID_SIAPIPE		3
#define EPOD_ID_SGA		4
#define EPOD_ID_B2R2_MCDE	5
#define EPOD_ID_ESRAM12		6
#define EPOD_ID_ESRAM34		7
#define NUM_EPOD_ID		8

/*
 * state definition for EPOD (power domain)
 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
 * - EPOD_STATE_OFF: The EPOD is switched off
 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
 *                         retention
 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
 * - EPOD_STATE_ON: Same as above, but with clock enabled
 */
#define EPOD_STATE_NO_CHANGE	0x00
#define EPOD_STATE_OFF		0x01
#define EPOD_STATE_RAMRET	0x02
#define EPOD_STATE_ON_CLK_OFF	0x03
#define EPOD_STATE_ON		0x04

/*
 * CLKOUT sources
 */
#define PRCMU_CLKSRC_CLK38M		0x00
#define PRCMU_CLKSRC_ACLK		0x01
#define PRCMU_CLKSRC_SYSCLK		0x02
#define PRCMU_CLKSRC_LCDCLK		0x03
#define PRCMU_CLKSRC_SDMMCCLK		0x04
#define PRCMU_CLKSRC_TVCLK		0x05
#define PRCMU_CLKSRC_TIMCLK		0x06
#define PRCMU_CLKSRC_CLK009		0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK	0x40
#define PRCMU_CLKSRC_I2CCLK		0x41
#define PRCMU_CLKSRC_MSP02CLK		0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK	0x43
#define PRCMU_CLKSRC_HSIRXCLK		0x44
#define PRCMU_CLKSRC_HSITXCLK		0x45
#define PRCMU_CLKSRC_ARMCLKFIX		0x46
#define PRCMU_CLKSRC_HDMICLK		0x47

/**
 * enum prcmu_wdog_id - PRCMU watchdog IDs
 * @PRCMU_WDOG_ALL: use all timers
 * @PRCMU_WDOG_CPU1: use first CPU timer only
 * @PRCMU_WDOG_CPU2: use second CPU timer conly
 */
enum prcmu_wdog_id {
	PRCMU_WDOG_ALL = 0x00,
	PRCMU_WDOG_CPU1 = 0x01,
	PRCMU_WDOG_CPU2 = 0x02,
};

/**
 * enum ape_opp - APE OPP states definition
 * @APE_OPP_INIT:
 * @APE_NO_CHANGE: The APE operating point is unchanged
 * @APE_100_OPP: The new APE operating point is ape100opp
 * @APE_50_OPP: 50%
 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
 */
enum ape_opp {
	APE_OPP_INIT = 0x00,
	APE_NO_CHANGE = 0x01,
	APE_100_OPP = 0x02,
	APE_50_OPP = 0x03,
	APE_50_PARTLY_25_OPP = 0xFF,
};

/**
 * enum arm_opp - ARM OPP states definition
 * @ARM_OPP_INIT:
 * @ARM_NO_CHANGE: The ARM operating point is unchanged
 * @ARM_100_OPP: The new ARM operating point is arm100opp
 * @ARM_50_OPP: The new ARM operating point is arm50opp
 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
 * @ARM_EXTCLK: The new ARM operating point is armExtClk
 */
enum arm_opp {
	ARM_OPP_INIT = 0x00,
	ARM_NO_CHANGE = 0x01,
	ARM_100_OPP = 0x02,
	ARM_50_OPP = 0x03,
	ARM_MAX_OPP = 0x04,
	ARM_MAX_FREQ100OPP = 0x05,
	ARM_EXTCLK = 0x07
};

/**
 * enum ddr_opp - DDR OPP states definition
 * @DDR_100_OPP: The new DDR operating point is ddr100opp
 * @DDR_50_OPP: The new DDR operating point is ddr50opp
 * @DDR_25_OPP: The new DDR operating point is ddr25opp
 */
enum ddr_opp {
	DDR_100_OPP = 0x00,
	DDR_50_OPP = 0x01,
	DDR_25_OPP = 0x02,
};

/*
 * Definitions for controlling ESRAM0 in deep sleep.
 */
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2

/**
 * enum ddr_pwrst - DDR power states definition
 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
 * @DDR_PWR_STATE_ON:
 * @DDR_PWR_STATE_OFFLOWLAT:
 * @DDR_PWR_STATE_OFFHIGHLAT:
 */
enum ddr_pwrst {
	DDR_PWR_STATE_UNCHANGED     = 0x00,
	DDR_PWR_STATE_ON            = 0x01,
	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
};

#define DB8500_PRCMU_LEGACY_OFFSET		0xDD4

#define PRCMU_FW_PROJECT_U8500		2
#define PRCMU_FW_PROJECT_U8400		3
#define PRCMU_FW_PROJECT_U9500		4 /* Customer specific */
#define PRCMU_FW_PROJECT_U8500_MBB	5
#define PRCMU_FW_PROJECT_U8500_C1	6
#define PRCMU_FW_PROJECT_U8500_C2	7
#define PRCMU_FW_PROJECT_U8500_C3	8
#define PRCMU_FW_PROJECT_U8500_C4	9
#define PRCMU_FW_PROJECT_U9500_MBL	10
#define PRCMU_FW_PROJECT_U8500_SSG1	11 /* Samsung specific */
#define PRCMU_FW_PROJECT_U8500_MBL2	12 /* Customer specific */
#define PRCMU_FW_PROJECT_U8520		13
#define PRCMU_FW_PROJECT_U8420		14
#define PRCMU_FW_PROJECT_U8500_SSG2	15 /* Samsung specific */
#define PRCMU_FW_PROJECT_U8420_SYSCLK	17
#define PRCMU_FW_PROJECT_A9420		20
/* [32..63] 9540 and derivatives */
#define PRCMU_FW_PROJECT_U9540		32
/* [64..95] 8540 and derivatives */
#define PRCMU_FW_PROJECT_L8540		64
/* [96..126] 8580 and derivatives */
#define PRCMU_FW_PROJECT_L8580		96

#define PRCMU_FW_PROJECT_NAME_LEN	20
struct prcmu_fw_version {
	u32 project; /* Notice, project shifted with 8 on ux540 */
	u8 api_version;
	u8 func_version;
	u8 errata;
	char project_name[PRCMU_FW_PROJECT_NAME_LEN];
};

#include <linux/mfd/db8500-prcmu.h>

#if defined(CONFIG_UX500_SOC_DB8500)

static inline void prcmu_early_init(void)
{
	return db8500_prcmu_early_init();
}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
		bool keep_ap_pll)
{
	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
		keep_ap_pll);
}

static inline u8 prcmu_get_power_state_result(void)
{
	return db8500_prcmu_get_power_state_result();
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return db8500_prcmu_set_epod(epod_id, epod_state);
}

static inline void prcmu_enable_wakeups(u32 wakeups)
{
	db8500_prcmu_enable_wakeups(wakeups);
}

static inline void prcmu_disable_wakeups(void)
{
	prcmu_enable_wakeups(0);
}

static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
	db8500_prcmu_config_abb_event_readout(abb_events);
}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	db8500_prcmu_get_abb_event_buffer(buf);
}

int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);

int prcmu_config_clkout(u8 clkout, u8 source, u8 div);

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return db8500_prcmu_request_clock(clock, enable);
}

unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);

static inline int prcmu_get_ddr_opp(void)
{
	return db8500_prcmu_get_ddr_opp();
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return db8500_prcmu_set_arm_opp(opp);
}

static inline int prcmu_get_arm_opp(void)
{
	return db8500_prcmu_get_arm_opp();
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return db8500_prcmu_set_ape_opp(opp);
}

static inline int prcmu_get_ape_opp(void)
{
	return db8500_prcmu_get_ape_opp();
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return db8500_prcmu_request_ape_opp_100_voltage(enable);
}

static inline void prcmu_system_reset(u16 reset_code)
{
	return db8500_prcmu_system_reset(reset_code);
}

static inline u16 prcmu_get_reset_code(void)
{
	return db8500_prcmu_get_reset_code();
}

int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
	return db8500_prcmu_modem_reset();
}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return db8500_prcmu_is_ac_wake_requested();
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return db8500_prcmu_config_esram0_deep_sleep(state);
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return db8500_prcmu_config_hotdog(threshold);
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return db8500_prcmu_config_hotmon(low, high);
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return  db8500_prcmu_start_temp_sense(cycles32k);
}

static inline int prcmu_stop_temp_sense(void)
{
	return  db8500_prcmu_stop_temp_sense();
}

static inline u32 prcmu_read(unsigned int reg)
{
	return db8500_prcmu_read(reg);
}

static inline void prcmu_write(unsigned int reg, u32 value)
{
	db8500_prcmu_write(reg, value);
}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
	db8500_prcmu_write_masked(reg, mask, value);
}

static inline int prcmu_enable_a9wdog(u8 id)
{
	return db8500_prcmu_enable_a9wdog(id);
}

static inline int prcmu_disable_a9wdog(u8 id)
{
	return db8500_prcmu_disable_a9wdog(id);
}

static inline int prcmu_kick_a9wdog(u8 id)
{
	return db8500_prcmu_kick_a9wdog(id);
}

static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
	return db8500_prcmu_load_a9wdog(id, timeout);
}

static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else

static inline void prcmu_early_init(void) {}

static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	bool keep_ap_pll)
{
	return 0;
}

static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
	return 0;
}

static inline void prcmu_enable_wakeups(u32 wakeups) {}

static inline void prcmu_disable_wakeups(void) {}

static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
	u8 size)
{
	return -ENOSYS;
}

static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
	return 0;
}

static inline int prcmu_request_clock(u8 clock, bool enable)
{
	return 0;
}

static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
	return 0;
}

static inline unsigned long prcmu_clock_rate(u8 clock)
{
	return 0;
}

static inline int prcmu_set_ape_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_ape_opp(void)
{
	return APE_100_OPP;
}

static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
	return 0;
}

static inline int prcmu_set_arm_opp(u8 opp)
{
	return 0;
}

static inline int prcmu_get_arm_opp(void)
{
	return ARM_100_OPP;
}

static inline int prcmu_get_ddr_opp(void)
{
	return DDR_100_OPP;
}

static inline void prcmu_system_reset(u16 reset_code) {}

static inline u16 prcmu_get_reset_code(void)
{
	return 0;
}

static inline int prcmu_ac_wake_req(void)
{
	return 0;
}

static inline void prcmu_ac_sleep_req(void) {}

static inline void prcmu_modem_reset(void) {}

static inline bool prcmu_is_ac_wake_requested(void)
{
	return false;
}

static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
	return 0;
}

static inline void prcmu_config_abb_event_readout(u32 abb_events) {}

static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
	*buf = NULL;
}

static inline int prcmu_config_hotdog(u8 threshold)
{
	return 0;
}

static inline int prcmu_config_hotmon(u8 low, u8 high)
{
	return 0;
}

static inline int prcmu_start_temp_sense(u16 cycles32k)
{
	return 0;
}

static inline int prcmu_stop_temp_sense(void)
{
	return 0;
}

static inline u32 prcmu_read(unsigned int reg)
{
	return 0;
}

static inline void prcmu_write(unsigned int reg, u32 value) {}

static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}

#endif

static inline void prcmu_set(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, bits);
}

static inline void prcmu_clear(unsigned int reg, u32 bits)
{
	prcmu_write_masked(reg, bits, 0);
}

/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1

static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
{
	return 0;
}

static inline int prcmu_qos_requirement(int prcmu_qos_class)
{
	return 0;
}

static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
					    char *name, s32 value)
{
	return 0;
}

static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
					       char *name, s32 new_value)
{
	return 0;
}

static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}

static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
					 struct notifier_block *notifier)
{
	return 0;
}
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
					    struct notifier_block *notifier)
{
	return 0;
}

#endif /* __MACH_PRCMU_H */
Commit	Line	Data
0376148f	1	/* SPDX-License-Identifier: GPL-2.0-only */
fea799e3 MN	2	/*
	3	* Copyright (C) ST Ericsson SA 2011
	4	*
fea799e3 MN	5	* STE Ux500 PRCMU API
	6	*/
	7	#ifndef __MACH_PRCMU_H
	8	#define __MACH_PRCMU_H
	9
	10	#include <linux/interrupt.h>
	11	#include <linux/notifier.h>
0508901c	12	#include <linux/err.h>
fea799e3	13
67f13daa LJ	14	#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
67f13daa LJ	15
05ec260e LW	16	/* Offset for the firmware version within the TCPM */
	17	#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
	18	#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
	19
fea799e3 MN	20	/* PRCMU Wakeup defines */
	21	enum prcmu_wakeup_index {
	22	PRCMU_WAKEUP_INDEX_RTC,
	23	PRCMU_WAKEUP_INDEX_RTT0,
	24	PRCMU_WAKEUP_INDEX_RTT1,
	25	PRCMU_WAKEUP_INDEX_HSI0,
	26	PRCMU_WAKEUP_INDEX_HSI1,
	27	PRCMU_WAKEUP_INDEX_USB,
	28	PRCMU_WAKEUP_INDEX_ABB,
	29	PRCMU_WAKEUP_INDEX_ABB_FIFO,
	30	PRCMU_WAKEUP_INDEX_ARM,
	31	PRCMU_WAKEUP_INDEX_CD_IRQ,
	32	NUM_PRCMU_WAKEUP_INDICES
	33	};
	34	#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
	35
	36	/* EPOD (power domain) IDs */
	37
	38	/*
	39	* DB8500 EPODs
	40	* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
	41	* - EPOD_ID_SVAPIPE: power domain for SVA pipe
	42	* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
	43	* - EPOD_ID_SIAPIPE: power domain for SIA pipe
	44	* - EPOD_ID_SGA: power domain for SGA
	45	* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
	46	* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
	47	* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
	48	* - NUM_EPOD_ID: number of power domains
	49	*
	50	* TODO: These should be prefixed.
	51	*/
	52	#define EPOD_ID_SVAMMDSP 0
	53	#define EPOD_ID_SVAPIPE 1
	54	#define EPOD_ID_SIAMMDSP 2
	55	#define EPOD_ID_SIAPIPE 3
	56	#define EPOD_ID_SGA 4
	57	#define EPOD_ID_B2R2_MCDE 5
	58	#define EPOD_ID_ESRAM12 6
	59	#define EPOD_ID_ESRAM34 7
	60	#define NUM_EPOD_ID 8
	61
fea799e3 MN	62	/*
	63	* state definition for EPOD (power domain)
	64	* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
	65	* - EPOD_STATE_OFF: The EPOD is switched off
	66	* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
	67	* retention
	68	* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
	69	* - EPOD_STATE_ON: Same as above, but with clock enabled
	70	*/
	71	#define EPOD_STATE_NO_CHANGE 0x00
	72	#define EPOD_STATE_OFF 0x01
	73	#define EPOD_STATE_RAMRET 0x02
	74	#define EPOD_STATE_ON_CLK_OFF 0x03
	75	#define EPOD_STATE_ON 0x04
	76
	77	/*
	78	* CLKOUT sources
	79	*/
	80	#define PRCMU_CLKSRC_CLK38M 0x00
	81	#define PRCMU_CLKSRC_ACLK 0x01
	82	#define PRCMU_CLKSRC_SYSCLK 0x02
	83	#define PRCMU_CLKSRC_LCDCLK 0x03
	84	#define PRCMU_CLKSRC_SDMMCCLK 0x04
	85	#define PRCMU_CLKSRC_TVCLK 0x05
	86	#define PRCMU_CLKSRC_TIMCLK 0x06
	87	#define PRCMU_CLKSRC_CLK009 0x07
	88	/* These are only valid for CLKOUT1: */
	89	#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
	90	#define PRCMU_CLKSRC_I2CCLK 0x41
	91	#define PRCMU_CLKSRC_MSP02CLK 0x42
	92	#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
	93	#define PRCMU_CLKSRC_HSIRXCLK 0x44
	94	#define PRCMU_CLKSRC_HSITXCLK 0x45
	95	#define PRCMU_CLKSRC_ARMCLKFIX 0x46
	96	#define PRCMU_CLKSRC_HDMICLK 0x47
	97
98c60a0d FB	98	/**
	99	* enum prcmu_wdog_id - PRCMU watchdog IDs
	100	* @PRCMU_WDOG_ALL: use all timers
	101	* @PRCMU_WDOG_CPU1: use first CPU timer only
	102	* @PRCMU_WDOG_CPU2: use second CPU timer conly
	103	*/
	104	enum prcmu_wdog_id {
	105	PRCMU_WDOG_ALL = 0x00,
	106	PRCMU_WDOG_CPU1 = 0x01,
	107	PRCMU_WDOG_CPU2 = 0x02,
	108	};
	109
fea799e3 MN	110	/**
	111	* enum ape_opp - APE OPP states definition
	112	* @APE_OPP_INIT:
	113	* @APE_NO_CHANGE: The APE operating point is unchanged
	114	* @APE_100_OPP: The new APE operating point is ape100opp
	115	* @APE_50_OPP: 50%
4d64d2e3	116	* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
fea799e3 MN	117	*/
	118	enum ape_opp {
	119	APE_OPP_INIT = 0x00,
	120	APE_NO_CHANGE = 0x01,
	121	APE_100_OPP = 0x02,
4d64d2e3 MN	122	APE_50_OPP = 0x03,
4d64d2e3 MN	123	APE_50_PARTLY_25_OPP = 0xFF,
fea799e3 MN	124	};
	125
	126	/**
	127	* enum arm_opp - ARM OPP states definition
	128	* @ARM_OPP_INIT:
	129	* @ARM_NO_CHANGE: The ARM operating point is unchanged
	130	* @ARM_100_OPP: The new ARM operating point is arm100opp
	131	* @ARM_50_OPP: The new ARM operating point is arm50opp
	132	* @ARM_MAX_OPP: Operating point is "max" (more than 100)
	133	* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
	134	* @ARM_EXTCLK: The new ARM operating point is armExtClk
	135	*/
	136	enum arm_opp {
	137	ARM_OPP_INIT = 0x00,
	138	ARM_NO_CHANGE = 0x01,
	139	ARM_100_OPP = 0x02,
	140	ARM_50_OPP = 0x03,
	141	ARM_MAX_OPP = 0x04,
	142	ARM_MAX_FREQ100OPP = 0x05,
	143	ARM_EXTCLK = 0x07
	144	};
	145
	146	/**
	147	* enum ddr_opp - DDR OPP states definition
	148	* @DDR_100_OPP: The new DDR operating point is ddr100opp
	149	* @DDR_50_OPP: The new DDR operating point is ddr50opp
	150	* @DDR_25_OPP: The new DDR operating point is ddr25opp
	151	*/
	152	enum ddr_opp {
	153	DDR_100_OPP = 0x00,
	154	DDR_50_OPP = 0x01,
	155	DDR_25_OPP = 0x02,
	156	};
	157
	158	/*
	159	* Definitions for controlling ESRAM0 in deep sleep.
	160	*/
	161	#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
	162	#define ESRAM0_DEEP_SLEEP_STATE_RET 2
	163
	164	/**
	165	* enum ddr_pwrst - DDR power states definition
	166	* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
	167	* @DDR_PWR_STATE_ON:
	168	* @DDR_PWR_STATE_OFFLOWLAT:
	169	* @DDR_PWR_STATE_OFFHIGHLAT:
	170	*/
	171	enum ddr_pwrst {
	172	DDR_PWR_STATE_UNCHANGED = 0x00,
	173	DDR_PWR_STATE_ON = 0x01,
	174	DDR_PWR_STATE_OFFLOWLAT = 0x02,
	175	DDR_PWR_STATE_OFFHIGHLAT = 0x03
	176	};
	177
05ec260e LW	178	#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
05ec260e LW	179
05ec260e LW	180	#define PRCMU_FW_PROJECT_U8500 2
	181	#define PRCMU_FW_PROJECT_U8400 3
	182	#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
	183	#define PRCMU_FW_PROJECT_U8500_MBB 5
	184	#define PRCMU_FW_PROJECT_U8500_C1 6
	185	#define PRCMU_FW_PROJECT_U8500_C2 7
	186	#define PRCMU_FW_PROJECT_U8500_C3 8
	187	#define PRCMU_FW_PROJECT_U8500_C4 9
	188	#define PRCMU_FW_PROJECT_U9500_MBL 10
9050ad81	189	#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
05ec260e LW	190	#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
	191	#define PRCMU_FW_PROJECT_U8520 13
	192	#define PRCMU_FW_PROJECT_U8420 14
9050ad81	193	#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
22fb3ad0	194	#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
05ec260e LW	195	#define PRCMU_FW_PROJECT_A9420 20
	196	/* [32..63] 9540 and derivatives */
	197	#define PRCMU_FW_PROJECT_U9540 32
	198	/* [64..95] 8540 and derivatives */
	199	#define PRCMU_FW_PROJECT_L8540 64
	200	/* [96..126] 8580 and derivatives */
	201	#define PRCMU_FW_PROJECT_L8580 96
	202
	203	#define PRCMU_FW_PROJECT_NAME_LEN 20
	204	struct prcmu_fw_version {
	205	u32 project; /* Notice, project shifted with 8 on ux540 */
	206	u8 api_version;
	207	u8 func_version;
	208	u8 errata;
	209	char project_name[PRCMU_FW_PROJECT_NAME_LEN];
	210	};
	211
fea799e3	212	#include <linux/mfd/db8500-prcmu.h>
fea799e3	213
dece3709	214	#if defined(CONFIG_UX500_SOC_DB8500)
fea799e3	215
22fb3ad0	216	static inline void prcmu_early_init(void)
fea799e3	217	{
22fb3ad0	218	return db8500_prcmu_early_init();
fea799e3 MN	219	}
	220
	221	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	222	bool keep_ap_pll)
	223	{
dece3709 LW	224	return db8500_prcmu_set_power_state(state, keep_ulp_clk,
dece3709 LW	225	keep_ap_pll);
fea799e3 MN	226	}
fea799e3 MN	227
4d64d2e3 MN	228	static inline u8 prcmu_get_power_state_result(void)
4d64d2e3 MN	229	{
dece3709	230	return db8500_prcmu_get_power_state_result();
4d64d2e3 MN	231	}
4d64d2e3 MN	232
fea799e3 MN	233	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
fea799e3 MN	234	{
dece3709	235	return db8500_prcmu_set_epod(epod_id, epod_state);
fea799e3 MN	236	}
	237
	238	static inline void prcmu_enable_wakeups(u32 wakeups)
	239	{
dece3709	240	db8500_prcmu_enable_wakeups(wakeups);
fea799e3 MN	241	}
	242
	243	static inline void prcmu_disable_wakeups(void)
	244	{
	245	prcmu_enable_wakeups(0);
	246	}
	247
	248	static inline void prcmu_config_abb_event_readout(u32 abb_events)
	249	{
dece3709	250	db8500_prcmu_config_abb_event_readout(abb_events);
fea799e3 MN	251	}
	252
	253	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	254	{
dece3709	255	db8500_prcmu_get_abb_event_buffer(buf);
fea799e3 MN	256	}
	257
	258	int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
	259	int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
3c3e4898	260	int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask, u8 size);
fea799e3 MN	261
	262	int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
	263
	264	static inline int prcmu_request_clock(u8 clock, bool enable)
	265	{
dece3709	266	return db8500_prcmu_request_clock(clock, enable);
fea799e3 MN	267	}
fea799e3 MN	268
0508901c MN	269	unsigned long prcmu_clock_rate(u8 clock);
	270	long prcmu_round_clock_rate(u8 clock, unsigned long rate);
	271	int prcmu_set_clock_rate(u8 clock, unsigned long rate);
	272
0508901c MN	273	static inline int prcmu_get_ddr_opp(void)
0508901c MN	274	{
dece3709	275	return db8500_prcmu_get_ddr_opp();
0508901c	276	}
fea799e3 MN	277
	278	static inline int prcmu_set_arm_opp(u8 opp)
	279	{
dece3709	280	return db8500_prcmu_set_arm_opp(opp);
fea799e3 MN	281	}
	282
	283	static inline int prcmu_get_arm_opp(void)
	284	{
dece3709	285	return db8500_prcmu_get_arm_opp();
fea799e3 MN	286	}
fea799e3 MN	287
0508901c MN	288	static inline int prcmu_set_ape_opp(u8 opp)
0508901c MN	289	{
dece3709	290	return db8500_prcmu_set_ape_opp(opp);
0508901c MN	291	}
	292
	293	static inline int prcmu_get_ape_opp(void)
	294	{
dece3709	295	return db8500_prcmu_get_ape_opp();
0508901c MN	296	}
0508901c MN	297
686f871b UH	298	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	299	{
	300	return db8500_prcmu_request_ape_opp_100_voltage(enable);
	301	}
	302
fea799e3 MN	303	static inline void prcmu_system_reset(u16 reset_code)
fea799e3 MN	304	{
dece3709	305	return db8500_prcmu_system_reset(reset_code);
fea799e3 MN	306	}
	307
	308	static inline u16 prcmu_get_reset_code(void)
	309	{
dece3709	310	return db8500_prcmu_get_reset_code();
fea799e3 MN	311	}
fea799e3 MN	312
5261e101	313	int prcmu_ac_wake_req(void);
fea799e3	314	void prcmu_ac_sleep_req(void);
0508901c MN	315	static inline void prcmu_modem_reset(void)
0508901c MN	316	{
dece3709	317	return db8500_prcmu_modem_reset();
0508901c MN	318	}
0508901c MN	319
fea799e3 MN	320	static inline bool prcmu_is_ac_wake_requested(void)
fea799e3 MN	321	{
dece3709	322	return db8500_prcmu_is_ac_wake_requested();
fea799e3 MN	323	}
fea799e3 MN	324
fea799e3 MN	325	static inline int prcmu_config_esram0_deep_sleep(u8 state)
fea799e3 MN	326	{
dece3709	327	return db8500_prcmu_config_esram0_deep_sleep(state);
fea799e3	328	}
0508901c MN	329
	330	static inline int prcmu_config_hotdog(u8 threshold)
	331	{
dece3709	332	return db8500_prcmu_config_hotdog(threshold);
0508901c MN	333	}
	334
	335	static inline int prcmu_config_hotmon(u8 low, u8 high)
	336	{
dece3709	337	return db8500_prcmu_config_hotmon(low, high);
0508901c MN	338	}
	339
	340	static inline int prcmu_start_temp_sense(u16 cycles32k)
	341	{
dece3709	342	return db8500_prcmu_start_temp_sense(cycles32k);
0508901c MN	343	}
	344
	345	static inline int prcmu_stop_temp_sense(void)
	346	{
dece3709	347	return db8500_prcmu_stop_temp_sense();
0508901c MN	348	}
0508901c MN	349
b4a6dbd5 MN	350	static inline u32 prcmu_read(unsigned int reg)
b4a6dbd5 MN	351	{
dece3709	352	return db8500_prcmu_read(reg);
b4a6dbd5 MN	353	}
	354
	355	static inline void prcmu_write(unsigned int reg, u32 value)
	356	{
dece3709	357	db8500_prcmu_write(reg, value);
b4a6dbd5 MN	358	}
	359
	360	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
	361	{
dece3709	362	db8500_prcmu_write_masked(reg, mask, value);
b4a6dbd5 MN	363	}
b4a6dbd5 MN	364
0508901c MN	365	static inline int prcmu_enable_a9wdog(u8 id)
0508901c MN	366	{
dece3709	367	return db8500_prcmu_enable_a9wdog(id);
0508901c MN	368	}
	369
	370	static inline int prcmu_disable_a9wdog(u8 id)
	371	{
dece3709	372	return db8500_prcmu_disable_a9wdog(id);
0508901c MN	373	}
	374
	375	static inline int prcmu_kick_a9wdog(u8 id)
	376	{
dece3709	377	return db8500_prcmu_kick_a9wdog(id);
0508901c MN	378	}
	379
	380	static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
	381	{
dece3709	382	return db8500_prcmu_load_a9wdog(id, timeout);
0508901c MN	383	}
	384
	385	static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
	386	{
dece3709	387	return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
0508901c	388	}
fea799e3 MN	389	#else
fea799e3 MN	390
22fb3ad0	391	static inline void prcmu_early_init(void) {}
fea799e3 MN	392
	393	static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
	394	bool keep_ap_pll)
	395	{
	396	return 0;
	397	}
	398
	399	static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
	400	{
	401	return 0;
	402	}
	403
	404	static inline void prcmu_enable_wakeups(u32 wakeups) {}
	405
	406	static inline void prcmu_disable_wakeups(void) {}
	407
	408	static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
	409	{
	410	return -ENOSYS;
	411	}
	412
	413	static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
	414	{
	415	return -ENOSYS;
	416	}
	417
3c3e4898 MN	418	static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 value, u8 mask,
	419	u8 size)
	420	{
	421	return -ENOSYS;
	422	}
	423
fea799e3 MN	424	static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
	425	{
	426	return 0;
	427	}
	428
	429	static inline int prcmu_request_clock(u8 clock, bool enable)
	430	{
	431	return 0;
6b6fae2b MN	432	}
	433
	434	static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
	435	{
	436	return 0;
	437	}
	438
	439	static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
	440	{
	441	return 0;
	442	}
	443
	444	static inline unsigned long prcmu_clock_rate(u8 clock)
	445	{
	446	return 0;
fea799e3 MN	447	}
	448
	449	static inline int prcmu_set_ape_opp(u8 opp)
	450	{
	451	return 0;
	452	}
	453
	454	static inline int prcmu_get_ape_opp(void)
	455	{
	456	return APE_100_OPP;
	457	}
	458
686f871b UH	459	static inline int prcmu_request_ape_opp_100_voltage(bool enable)
	460	{
	461	return 0;
	462	}
	463
fea799e3 MN	464	static inline int prcmu_set_arm_opp(u8 opp)
	465	{
	466	return 0;
	467	}
	468
	469	static inline int prcmu_get_arm_opp(void)
	470	{
	471	return ARM_100_OPP;
	472	}
	473
fea799e3 MN	474	static inline int prcmu_get_ddr_opp(void)
	475	{
	476	return DDR_100_OPP;
	477	}
	478
	479	static inline void prcmu_system_reset(u16 reset_code) {}
	480
	481	static inline u16 prcmu_get_reset_code(void)
	482	{
	483	return 0;
	484	}
	485
5261e101 AM	486	static inline int prcmu_ac_wake_req(void)
	487	{
	488	return 0;
	489	}
fea799e3 MN	490
	491	static inline void prcmu_ac_sleep_req(void) {}
	492
	493	static inline void prcmu_modem_reset(void) {}
	494
	495	static inline bool prcmu_is_ac_wake_requested(void)
	496	{
	497	return false;
	498	}
	499
fea799e3 MN	500	static inline int prcmu_config_esram0_deep_sleep(u8 state)
	501	{
	502	return 0;
	503	}
	504
	505	static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
	506
	507	static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
	508	{
	509	*buf = NULL;
	510	}
	511
0508901c MN	512	static inline int prcmu_config_hotdog(u8 threshold)
	513	{
	514	return 0;
	515	}
	516
	517	static inline int prcmu_config_hotmon(u8 low, u8 high)
	518	{
	519	return 0;
	520	}
	521
	522	static inline int prcmu_start_temp_sense(u16 cycles32k)
	523	{
	524	return 0;
	525	}
	526
	527	static inline int prcmu_stop_temp_sense(void)
	528	{
	529	return 0;
	530	}
	531
b4a6dbd5 MN	532	static inline u32 prcmu_read(unsigned int reg)
	533	{
	534	return 0;
	535	}
	536
	537	static inline void prcmu_write(unsigned int reg, u32 value) {}
	538
	539	static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
	540
	541	#endif
	542
	543	static inline void prcmu_set(unsigned int reg, u32 bits)
	544	{
	545	prcmu_write_masked(reg, bits, bits);
	546	}
	547
	548	static inline void prcmu_clear(unsigned int reg, u32 bits)
	549	{
	550	prcmu_write_masked(reg, bits, 0);
	551	}
	552
fea799e3 MN	553	/* PRCMU QoS APE OPP class */
	554	#define PRCMU_QOS_APE_OPP 1
	555	#define PRCMU_QOS_DDR_OPP 2
4d64d2e3	556	#define PRCMU_QOS_ARM_OPP 3
fea799e3 MN	557	#define PRCMU_QOS_DEFAULT_VALUE -1
fea799e3 MN	558
fea799e3 MN	559	static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
	560	{
	561	return 0;
	562	}
	563
fea799e3 MN	564	static inline int prcmu_qos_requirement(int prcmu_qos_class)
	565	{
	566	return 0;
	567	}
	568
	569	static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
	570	char *name, s32 value)
	571	{
	572	return 0;
	573	}
	574
	575	static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
	576	char *name, s32 new_value)
	577	{
	578	return 0;
	579	}
	580
	581	static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
	582	{
	583	}
	584
	585	static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
	586	struct notifier_block *notifier)
	587	{
	588	return 0;
	589	}
	590	static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
	591	struct notifier_block *notifier)
	592	{
	593	return 0;
	594	}
	595
fea799e3	596	#endif /* __MACH_PRCMU_H */