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8317797c LW |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * | |
6 | * U5500 PRCMU API. | |
7 | */ | |
73180f85 MN |
8 | #ifndef __MFD_DB5500_PRCMU_H |
9 | #define __MFD_DB5500_PRCMU_H | |
8317797c | 10 | |
4accdff7 | 11 | static inline int prcmu_resetout(u8 resoutn, u8 state) |
8317797c | 12 | { |
4accdff7 | 13 | return 0; |
8317797c LW |
14 | } |
15 | ||
4accdff7 | 16 | static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) |
8317797c | 17 | { |
4accdff7 | 18 | return 0; |
8317797c LW |
19 | } |
20 | ||
73180f85 MN |
21 | static inline int db5500_prcmu_request_clock(u8 clock, bool enable) |
22 | { | |
23 | return 0; | |
24 | } | |
25 | ||
4accdff7 DL |
26 | static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, |
27 | bool keep_ap_pll) | |
73180f85 MN |
28 | { |
29 | return 0; | |
30 | } | |
31 | ||
4accdff7 | 32 | static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) |
73180f85 MN |
33 | { |
34 | return 0; | |
35 | } | |
36 | ||
4accdff7 | 37 | static inline u16 db5500_prcmu_get_reset_code(void) |
73180f85 MN |
38 | { |
39 | return 0; | |
40 | } | |
8317797c | 41 | |
4accdff7 | 42 | static inline bool db5500_prcmu_is_ac_wake_requested(void) |
8317797c | 43 | { |
8317797c | 44 | return 0; |
8317797c LW |
45 | } |
46 | ||
4accdff7 | 47 | static inline int db5500_prcmu_set_arm_opp(u8 opp) |
73180f85 MN |
48 | { |
49 | return 0; | |
50 | } | |
51 | ||
4accdff7 | 52 | static inline int db5500_prcmu_get_arm_opp(void) |
73180f85 MN |
53 | { |
54 | return 0; | |
55 | } | |
56 | ||
73180f85 MN |
57 | static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {} |
58 | ||
4accdff7 | 59 | static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {} |
73180f85 MN |
60 | |
61 | static inline void db5500_prcmu_system_reset(u16 reset_code) {} | |
62 | ||
4accdff7 DL |
63 | static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} |
64 | ||
65 | #ifdef CONFIG_MFD_DB5500_PRCMU | |
66 | ||
67 | void db5500_prcmu_early_init(void); | |
68 | int db5500_prcmu_set_display_clocks(void); | |
69 | int db5500_prcmu_disable_dsipll(void); | |
70 | int db5500_prcmu_enable_dsipll(void); | |
71 | int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); | |
72 | int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | |
73 | ||
74 | #else /* !CONFIG_UX500_SOC_DB5500 */ | |
75 | ||
76 | static inline void db5500_prcmu_early_init(void) {} | |
77 | ||
78 | static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
73180f85 | 79 | { |
4accdff7 | 80 | return -ENOSYS; |
73180f85 MN |
81 | } |
82 | ||
4accdff7 | 83 | static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) |
73180f85 | 84 | { |
4accdff7 | 85 | return -ENOSYS; |
73180f85 MN |
86 | } |
87 | ||
4accdff7 | 88 | static inline int db5500_prcmu_set_display_clocks(void) |
73180f85 MN |
89 | { |
90 | return 0; | |
91 | } | |
92 | ||
4accdff7 | 93 | static inline int db5500_prcmu_disable_dsipll(void) |
73180f85 MN |
94 | { |
95 | return 0; | |
96 | } | |
97 | ||
4accdff7 DL |
98 | static inline int db5500_prcmu_enable_dsipll(void) |
99 | { | |
100 | return 0; | |
101 | } | |
73180f85 MN |
102 | |
103 | #endif /* CONFIG_MFD_DB5500_PRCMU */ | |
104 | ||
105 | #endif /* __MFD_DB5500_PRCMU_H */ |