projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 84c99db8 AJ |
1 | /* |
| 2 | * Register declarations for DA9052 PMICs. | |
| 3 | * | |
| 4 | * Copyright(c) 2011 Dialog Semiconductor Ltd. | |
| 5 | * | |
| 6 | * Author: David Dajun Chen <dchen@diasemi.com> | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify | |
| 9 | * it under the terms of the GNU General Public License as published by | |
| 10 | * the Free Software Foundation; either version 2 of the License, or | |
| 11 | * (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
| 21 | * | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __LINUX_MFD_DA9052_REG_H | |
| 25 | #define __LINUX_MFD_DA9052_REG_H | |
| 26 | ||
| 27 | /* PAGE REGISTERS */ | |
| 28 | #define DA9052_PAGE0_CON_REG 0 | |
| 29 | #define DA9052_PAGE1_CON_REG 128 | |
| 30 | ||
| 31 | /* STATUS REGISTERS */ | |
| 32 | #define DA9052_STATUS_A_REG 1 | |
| 33 | #define DA9052_STATUS_B_REG 2 | |
| 34 | #define DA9052_STATUS_C_REG 3 | |
| 35 | #define DA9052_STATUS_D_REG 4 | |
| 36 | ||
| 0a8c290a AJ |
37 | /* PARK REGISTER */ |
| 38 | #define DA9052_PARK_REGISTER DA9052_STATUS_D_REG | |
| 39 | ||
| 84c99db8 AJ |
40 | /* EVENT REGISTERS */ |
| 41 | #define DA9052_EVENT_A_REG 5 | |
| 42 | #define DA9052_EVENT_B_REG 6 | |
| 43 | #define DA9052_EVENT_C_REG 7 | |
| 44 | #define DA9052_EVENT_D_REG 8 | |
| 45 | #define DA9052_FAULTLOG_REG 9 | |
| 46 | ||
| 47 | /* IRQ REGISTERS */ | |
| 48 | #define DA9052_IRQ_MASK_A_REG 10 | |
| 49 | #define DA9052_IRQ_MASK_B_REG 11 | |
| 50 | #define DA9052_IRQ_MASK_C_REG 12 | |
| 51 | #define DA9052_IRQ_MASK_D_REG 13 | |
| 52 | ||
| 53 | /* CONTROL REGISTERS */ | |
| 54 | #define DA9052_CONTROL_A_REG 14 | |
| 55 | #define DA9052_CONTROL_B_REG 15 | |
| 56 | #define DA9052_CONTROL_C_REG 16 | |
| 57 | #define DA9052_CONTROL_D_REG 17 | |
| 58 | ||
| 59 | #define DA9052_PDDIS_REG 18 | |
| 60 | #define DA9052_INTERFACE_REG 19 | |
| 61 | #define DA9052_RESET_REG 20 | |
| 62 | ||
| 63 | /* GPIO REGISTERS */ | |
| 64 | #define DA9052_GPIO_0_1_REG 21 | |
| 65 | #define DA9052_GPIO_2_3_REG 22 | |
| 66 | #define DA9052_GPIO_4_5_REG 23 | |
| 67 | #define DA9052_GPIO_6_7_REG 24 | |
| 0386af30 ST |
68 | #define DA9052_GPIO_8_9_REG 25 |
| 69 | #define DA9052_GPIO_10_11_REG 26 | |
| 70 | #define DA9052_GPIO_12_13_REG 27 | |
| 84c99db8 AJ |
71 | #define DA9052_GPIO_14_15_REG 28 |
| 72 | ||
| 73 | /* POWER SEQUENCER CONTROL REGISTERS */ | |
| 74 | #define DA9052_ID_0_1_REG 29 | |
| 75 | #define DA9052_ID_2_3_REG 30 | |
| 76 | #define DA9052_ID_4_5_REG 31 | |
| 77 | #define DA9052_ID_6_7_REG 32 | |
| 78 | #define DA9052_ID_8_9_REG 33 | |
| 79 | #define DA9052_ID_10_11_REG 34 | |
| 80 | #define DA9052_ID_12_13_REG 35 | |
| 81 | #define DA9052_ID_14_15_REG 36 | |
| 82 | #define DA9052_ID_16_17_REG 37 | |
| 83 | #define DA9052_ID_18_19_REG 38 | |
| 84 | #define DA9052_ID_20_21_REG 39 | |
| 85 | #define DA9052_SEQ_STATUS_REG 40 | |
| 86 | #define DA9052_SEQ_A_REG 41 | |
| 87 | #define DA9052_SEQ_B_REG 42 | |
| 88 | #define DA9052_SEQ_TIMER_REG 43 | |
| 89 | ||
| 90 | /* LDO AND BUCK REGISTERS */ | |
| 91 | #define DA9052_BUCKA_REG 44 | |
| 92 | #define DA9052_BUCKB_REG 45 | |
| 93 | #define DA9052_BUCKCORE_REG 46 | |
| 94 | #define DA9052_BUCKPRO_REG 47 | |
| 95 | #define DA9052_BUCKMEM_REG 48 | |
| 96 | #define DA9052_BUCKPERI_REG 49 | |
| 97 | #define DA9052_LDO1_REG 50 | |
| 98 | #define DA9052_LDO2_REG 51 | |
| 99 | #define DA9052_LDO3_REG 52 | |
| 100 | #define DA9052_LDO4_REG 53 | |
| 101 | #define DA9052_LDO5_REG 54 | |
| 102 | #define DA9052_LDO6_REG 55 | |
| 103 | #define DA9052_LDO7_REG 56 | |
| 104 | #define DA9052_LDO8_REG 57 | |
| 105 | #define DA9052_LDO9_REG 58 | |
| 106 | #define DA9052_LDO10_REG 59 | |
| 107 | #define DA9052_SUPPLY_REG 60 | |
| 108 | #define DA9052_PULLDOWN_REG 61 | |
| 109 | #define DA9052_CHGBUCK_REG 62 | |
| 110 | #define DA9052_WAITCONT_REG 63 | |
| 111 | #define DA9052_ISET_REG 64 | |
| 112 | #define DA9052_BATCHG_REG 65 | |
| 113 | ||
| 114 | /* BATTERY CONTROL REGISTRS */ | |
| 115 | #define DA9052_CHG_CONT_REG 66 | |
| 116 | #define DA9052_INPUT_CONT_REG 67 | |
| 117 | #define DA9052_CHG_TIME_REG 68 | |
| 118 | #define DA9052_BBAT_CONT_REG 69 | |
| 119 | ||
| 120 | /* LED CONTROL REGISTERS */ | |
| 121 | #define DA9052_BOOST_REG 70 | |
| 122 | #define DA9052_LED_CONT_REG 71 | |
| 123 | #define DA9052_LEDMIN123_REG 72 | |
| 124 | #define DA9052_LED1_CONF_REG 73 | |
| 125 | #define DA9052_LED2_CONF_REG 74 | |
| 126 | #define DA9052_LED3_CONF_REG 75 | |
| 127 | #define DA9052_LED1CONT_REG 76 | |
| 128 | #define DA9052_LED2CONT_REG 77 | |
| 129 | #define DA9052_LED3CONT_REG 78 | |
| 130 | #define DA9052_LED_CONT_4_REG 79 | |
| 131 | #define DA9052_LED_CONT_5_REG 80 | |
| 132 | ||
| 133 | /* ADC CONTROL REGISTERS */ | |
| 134 | #define DA9052_ADC_MAN_REG 81 | |
| 135 | #define DA9052_ADC_CONT_REG 82 | |
| 136 | #define DA9052_ADC_RES_L_REG 83 | |
| 137 | #define DA9052_ADC_RES_H_REG 84 | |
| 138 | #define DA9052_VDD_RES_REG 85 | |
| 139 | #define DA9052_VDD_MON_REG 86 | |
| 140 | ||
| 141 | #define DA9052_ICHG_AV_REG 87 | |
| 142 | #define DA9052_ICHG_THD_REG 88 | |
| 143 | #define DA9052_ICHG_END_REG 89 | |
| 144 | #define DA9052_TBAT_RES_REG 90 | |
| 145 | #define DA9052_TBAT_HIGHP_REG 91 | |
| 146 | #define DA9052_TBAT_HIGHN_REG 92 | |
| 147 | #define DA9052_TBAT_LOW_REG 93 | |
| 148 | #define DA9052_T_OFFSET_REG 94 | |
| 149 | ||
| 150 | #define DA9052_ADCIN4_RES_REG 95 | |
| 151 | #define DA9052_AUTO4_HIGH_REG 96 | |
| 152 | #define DA9052_AUTO4_LOW_REG 97 | |
| 153 | #define DA9052_ADCIN5_RES_REG 98 | |
| 154 | #define DA9052_AUTO5_HIGH_REG 99 | |
| 155 | #define DA9052_AUTO5_LOW_REG 100 | |
| 156 | #define DA9052_ADCIN6_RES_REG 101 | |
| 157 | #define DA9052_AUTO6_HIGH_REG 102 | |
| 158 | #define DA9052_AUTO6_LOW_REG 103 | |
| 159 | ||
| 160 | #define DA9052_TJUNC_RES_REG 104 | |
| 161 | ||
| 162 | /* TSI CONTROL REGISTERS */ | |
| 163 | #define DA9052_TSI_CONT_A_REG 105 | |
| 164 | #define DA9052_TSI_CONT_B_REG 106 | |
| 165 | #define DA9052_TSI_X_MSB_REG 107 | |
| 166 | #define DA9052_TSI_Y_MSB_REG 108 | |
| 167 | #define DA9052_TSI_LSB_REG 109 | |
| 168 | #define DA9052_TSI_Z_MSB_REG 110 | |
| 169 | ||
| 170 | /* RTC COUNT REGISTERS */ | |
| 171 | #define DA9052_COUNT_S_REG 111 | |
| 172 | #define DA9052_COUNT_MI_REG 112 | |
| 173 | #define DA9052_COUNT_H_REG 113 | |
| 174 | #define DA9052_COUNT_D_REG 114 | |
| 175 | #define DA9052_COUNT_MO_REG 115 | |
| 176 | #define DA9052_COUNT_Y_REG 116 | |
| 177 | ||
| 178 | /* RTC CONTROL REGISTERS */ | |
| 179 | #define DA9052_ALARM_MI_REG 117 | |
| 180 | #define DA9052_ALARM_H_REG 118 | |
| 181 | #define DA9052_ALARM_D_REG 119 | |
| 182 | #define DA9052_ALARM_MO_REG 120 | |
| 183 | #define DA9052_ALARM_Y_REG 121 | |
| 184 | #define DA9052_SECOND_A_REG 122 | |
| 185 | #define DA9052_SECOND_B_REG 123 | |
| 186 | #define DA9052_SECOND_C_REG 124 | |
| 187 | #define DA9052_SECOND_D_REG 125 | |
| 188 | ||
| 189 | /* PAGE CONFIGURATION BIT */ | |
| 190 | #define DA9052_PAGE_CONF 0X80 | |
| 191 | ||
| 192 | /* STATUS REGISTER A BITS */ | |
| 193 | #define DA9052_STATUSA_VDATDET 0X80 | |
| 194 | #define DA9052_STATUSA_VBUSSEL 0X40 | |
| 195 | #define DA9052_STATUSA_DCINSEL 0X20 | |
| 196 | #define DA9052_STATUSA_VBUSDET 0X10 | |
| 197 | #define DA9052_STATUSA_DCINDET 0X08 | |
| 198 | #define DA9052_STATUSA_IDGND 0X04 | |
| 199 | #define DA9052_STATUSA_IDFLOAT 0X02 | |
| 200 | #define DA9052_STATUSA_NONKEY 0X01 | |
| 201 | ||
| 202 | /* STATUS REGISTER B BITS */ | |
| 203 | #define DA9052_STATUSB_COMPDET 0X80 | |
| 204 | #define DA9052_STATUSB_SEQUENCING 0X40 | |
| 205 | #define DA9052_STATUSB_GPFB2 0X20 | |
| 206 | #define DA9052_STATUSB_CHGTO 0X10 | |
| 207 | #define DA9052_STATUSB_CHGEND 0X08 | |
| 208 | #define DA9052_STATUSB_CHGLIM 0X04 | |
| 209 | #define DA9052_STATUSB_CHGPRE 0X02 | |
| 210 | #define DA9052_STATUSB_CHGATT 0X01 | |
| 211 | ||
| 212 | /* STATUS REGISTER C BITS */ | |
| 213 | #define DA9052_STATUSC_GPI7 0X80 | |
| 214 | #define DA9052_STATUSC_GPI6 0X40 | |
| 215 | #define DA9052_STATUSC_GPI5 0X20 | |
| 216 | #define DA9052_STATUSC_GPI4 0X10 | |
| 217 | #define DA9052_STATUSC_GPI3 0X08 | |
| 218 | #define DA9052_STATUSC_GPI2 0X04 | |
| 219 | #define DA9052_STATUSC_GPI1 0X02 | |
| 220 | #define DA9052_STATUSC_GPI0 0X01 | |
| 221 | ||
| 222 | /* STATUS REGISTER D BITS */ | |
| 223 | #define DA9052_STATUSD_GPI15 0X80 | |
| 224 | #define DA9052_STATUSD_GPI14 0X40 | |
| 225 | #define DA9052_STATUSD_GPI13 0X20 | |
| 226 | #define DA9052_STATUSD_GPI12 0X10 | |
| 227 | #define DA9052_STATUSD_GPI11 0X08 | |
| 228 | #define DA9052_STATUSD_GPI10 0X04 | |
| 229 | #define DA9052_STATUSD_GPI9 0X02 | |
| 230 | #define DA9052_STATUSD_GPI8 0X01 | |
| 231 | ||
| 232 | /* EVENT REGISTER A BITS */ | |
| 233 | #define DA9052_EVENTA_ECOMP1V2 0X80 | |
| 234 | #define DA9052_EVENTA_ESEQRDY 0X40 | |
| 235 | #define DA9052_EVENTA_EALRAM 0X20 | |
| 236 | #define DA9052_EVENTA_EVDDLOW 0X10 | |
| 237 | #define DA9052_EVENTA_EVBUSREM 0X08 | |
| 238 | #define DA9052_EVENTA_EDCINREM 0X04 | |
| 239 | #define DA9052_EVENTA_EVBUSDET 0X02 | |
| 240 | #define DA9052_EVENTA_EDCINDET 0X01 | |
| 241 | ||
| 242 | /* EVENT REGISTER B BITS */ | |
| 243 | #define DA9052_EVENTB_ETSIREADY 0X80 | |
| 244 | #define DA9052_EVENTB_EPENDOWN 0X40 | |
| 245 | #define DA9052_EVENTB_EADCEOM 0X20 | |
| 246 | #define DA9052_EVENTB_ETBAT 0X10 | |
| 247 | #define DA9052_EVENTB_ECHGEND 0X08 | |
| 248 | #define DA9052_EVENTB_EIDGND 0X04 | |
| 249 | #define DA9052_EVENTB_EIDFLOAT 0X02 | |
| 250 | #define DA9052_EVENTB_ENONKEY 0X01 | |
| 251 | ||
| 252 | /* EVENT REGISTER C BITS */ | |
| 253 | #define DA9052_EVENTC_EGPI7 0X80 | |
| 254 | #define DA9052_EVENTC_EGPI6 0X40 | |
| 255 | #define DA9052_EVENTC_EGPI5 0X20 | |
| 256 | #define DA9052_EVENTC_EGPI4 0X10 | |
| 257 | #define DA9052_EVENTC_EGPI3 0X08 | |
| 258 | #define DA9052_EVENTC_EGPI2 0X04 | |
| 259 | #define DA9052_EVENTC_EGPI1 0X02 | |
| 260 | #define DA9052_EVENTC_EGPI0 0X01 | |
| 261 | ||
| 262 | /* EVENT REGISTER D BITS */ | |
| 263 | #define DA9052_EVENTD_EGPI15 0X80 | |
| 264 | #define DA9052_EVENTD_EGPI14 0X40 | |
| 265 | #define DA9052_EVENTD_EGPI13 0X20 | |
| 266 | #define DA9052_EVENTD_EGPI12 0X10 | |
| 267 | #define DA9052_EVENTD_EGPI11 0X08 | |
| 268 | #define DA9052_EVENTD_EGPI10 0X04 | |
| 269 | #define DA9052_EVENTD_EGPI9 0X02 | |
| 270 | #define DA9052_EVENTD_EGPI8 0X01 | |
| 271 | ||
| 272 | /* IRQ MASK REGISTERS BITS */ | |
| 273 | #define DA9052_M_NONKEY 0X0100 | |
| 274 | ||
| 275 | /* TSI EVENT REGISTERS BITS */ | |
| 276 | #define DA9052_E_PEN_DOWN 0X4000 | |
| 277 | #define DA9052_E_TSI_READY 0X8000 | |
| 278 | ||
| 279 | /* FAULT LOG REGISTER BITS */ | |
| 280 | #define DA9052_FAULTLOG_WAITSET 0X80 | |
| 281 | #define DA9052_FAULTLOG_NSDSET 0X40 | |
| 282 | #define DA9052_FAULTLOG_KEYSHUT 0X20 | |
| 283 | #define DA9052_FAULTLOG_TEMPOVER 0X08 | |
| 284 | #define DA9052_FAULTLOG_VDDSTART 0X04 | |
| 285 | #define DA9052_FAULTLOG_VDDFAULT 0X02 | |
| 286 | #define DA9052_FAULTLOG_TWDERROR 0X01 | |
| 287 | ||
| 288 | /* CONTROL REGISTER A BITS */ | |
| 289 | #define DA9052_CONTROLA_GPIV 0X80 | |
| 290 | #define DA9052_CONTROLA_PMOTYPE 0X20 | |
| 291 | #define DA9052_CONTROLA_PMOV 0X10 | |
| 292 | #define DA9052_CONTROLA_PMIV 0X08 | |
| 293 | #define DA9052_CONTROLA_PMIFV 0X08 | |
| 294 | #define DA9052_CONTROLA_PWR1EN 0X04 | |
| 295 | #define DA9052_CONTROLA_PWREN 0X02 | |
| 296 | #define DA9052_CONTROLA_SYSEN 0X01 | |
| 297 | ||
| 298 | /* CONTROL REGISTER B BITS */ | |
| 299 | #define DA9052_CONTROLB_SHUTDOWN 0X80 | |
| 300 | #define DA9052_CONTROLB_DEEPSLEEP 0X40 | |
| 301 | #define DA9052_CONTROL_B_WRITEMODE 0X20 | |
| 302 | #define DA9052_CONTROLB_BBATEN 0X10 | |
| 303 | #define DA9052_CONTROLB_OTPREADEN 0X08 | |
| 304 | #define DA9052_CONTROLB_AUTOBOOT 0X04 | |
| 305 | #define DA9052_CONTROLB_ACTDIODE 0X02 | |
| 306 | #define DA9052_CONTROLB_BUCKMERGE 0X01 | |
| 307 | ||
| 308 | /* CONTROL REGISTER C BITS */ | |
| 309 | #define DA9052_CONTROLC_BLINKDUR 0X80 | |
| 310 | #define DA9052_CONTROLC_BLINKFRQ 0X60 | |
| 311 | #define DA9052_CONTROLC_DEBOUNCING 0X1C | |
| 312 | #define DA9052_CONTROLC_PMFB2PIN 0X02 | |
| 313 | #define DA9052_CONTROLC_PMFB1PIN 0X01 | |
| 314 | ||
| 315 | /* CONTROL REGISTER D BITS */ | |
| 316 | #define DA9052_CONTROLD_WATCHDOG 0X80 | |
| 317 | #define DA9052_CONTROLD_ACCDETEN 0X40 | |
| 318 | #define DA9052_CONTROLD_GPI1415SD 0X20 | |
| 319 | #define DA9052_CONTROLD_NONKEYSD 0X10 | |
| 320 | #define DA9052_CONTROLD_KEEPACTEN 0X08 | |
| 321 | #define DA9052_CONTROLD_TWDSCALE 0X07 | |
| 322 | ||
| 323 | /* POWER DOWN DISABLE REGISTER BITS */ | |
| 324 | #define DA9052_PDDIS_PMCONTPD 0X80 | |
| 325 | #define DA9052_PDDIS_OUT32KPD 0X40 | |
| 326 | #define DA9052_PDDIS_CHGBBATPD 0X20 | |
| 327 | #define DA9052_PDDIS_CHGPD 0X10 | |
| 328 | #define DA9052_PDDIS_HS2WIREPD 0X08 | |
| 329 | #define DA9052_PDDIS_PMIFPD 0X04 | |
| 330 | #define DA9052_PDDIS_GPADCPD 0X02 | |
| 331 | #define DA9052_PDDIS_GPIOPD 0X01 | |
| 332 | ||
| 333 | /* CONTROL REGISTER D BITS */ | |
| 334 | #define DA9052_INTERFACE_IFBASEADDR 0XE0 | |
| 335 | #define DA9052_INTERFACE_NCSPOL 0X10 | |
| 336 | #define DA9052_INTERFACE_RWPOL 0X08 | |
| 337 | #define DA9052_INTERFACE_CPHA 0X04 | |
| 338 | #define DA9052_INTERFACE_CPOL 0X02 | |
| 339 | #define DA9052_INTERFACE_IFTYPE 0X01 | |
| 340 | ||
| 341 | /* CONTROL REGISTER D BITS */ | |
| 342 | #define DA9052_RESET_RESETEVENT 0XC0 | |
| 343 | #define DA9052_RESET_RESETTIMER 0X3F | |
| 344 | ||
| 345 | /* GPIO REGISTERS */ | |
| 346 | /* GPIO CONTROL REGISTER BITS */ | |
| 347 | #define DA9052_GPIO_EVEN_PORT_PIN 0X03 | |
| 348 | #define DA9052_GPIO_EVEN_PORT_TYPE 0X04 | |
| 349 | #define DA9052_GPIO_EVEN_PORT_MODE 0X08 | |
| 350 | ||
| 351 | #define DA9052_GPIO_ODD_PORT_PIN 0X30 | |
| 352 | #define DA9052_GPIO_ODD_PORT_TYPE 0X40 | |
| 353 | #define DA9052_GPIO_ODD_PORT_MODE 0X80 | |
| 354 | ||
| 355 | /*POWER SEQUENCER REGISTER BITS */ | |
| 356 | /* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */ | |
| 357 | #define DA9052_ID01_LDO1STEP 0XF0 | |
| 358 | #define DA9052_ID01_SYSPRE 0X04 | |
| 359 | #define DA9052_ID01_DEFSUPPLY 0X02 | |
| 360 | #define DA9052_ID01_NRESMODE 0X01 | |
| 361 | ||
| 362 | /* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */ | |
| 363 | #define DA9052_ID23_LDO3STEP 0XF0 | |
| 364 | #define DA9052_ID23_LDO2STEP 0X0F | |
| 365 | ||
| 366 | /* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */ | |
| 367 | #define DA9052_ID45_LDO5STEP 0XF0 | |
| 368 | #define DA9052_ID45_LDO4STEP 0X0F | |
| 369 | ||
| 370 | /* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */ | |
| 371 | #define DA9052_ID67_LDO7STEP 0XF0 | |
| 372 | #define DA9052_ID67_LDO6STEP 0X0F | |
| 373 | ||
| 374 | /* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */ | |
| 375 | #define DA9052_ID89_LDO9STEP 0XF0 | |
| 376 | #define DA9052_ID89_LDO8STEP 0X0F | |
| 377 | ||
| 378 | /* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */ | |
| 379 | #define DA9052_ID1011_PDDISSTEP 0XF0 | |
| 380 | #define DA9052_ID1011_LDO10STEP 0X0F | |
| 381 | ||
| 382 | /* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */ | |
| 383 | #define DA9052_ID1213_VMEMSWSTEP 0XF0 | |
| 384 | #define DA9052_ID1213_VPERISWSTEP 0X0F | |
| 385 | ||
| 386 | /* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */ | |
| 387 | #define DA9052_ID1415_BUCKPROSTEP 0XF0 | |
| 388 | #define DA9052_ID1415_BUCKCORESTEP 0X0F | |
| 389 | ||
| 390 | /* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */ | |
| 391 | #define DA9052_ID1617_BUCKPERISTEP 0XF0 | |
| 392 | #define DA9052_ID1617_BUCKMEMSTEP 0X0F | |
| 393 | ||
| 394 | /* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */ | |
| 395 | #define DA9052_ID1819_GPRISE2STEP 0XF0 | |
| 396 | #define DA9052_ID1819_GPRISE1STEP 0X0F | |
| 397 | ||
| 398 | /* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */ | |
| 399 | #define DA9052_ID2021_GPFALL2STEP 0XF0 | |
| 400 | #define DA9052_ID2021_GPFALL1STEP 0X0F | |
| 401 | ||
| 402 | /* POWER SEQ STATUS REGISTER BITS */ | |
| 403 | #define DA9052_SEQSTATUS_SEQPOINTER 0XF0 | |
| 404 | #define DA9052_SEQSTATUS_WAITSTEP 0X0F | |
| 405 | ||
| 406 | /* POWER SEQ A REGISTER BITS */ | |
| 407 | #define DA9052_SEQA_POWEREND 0XF0 | |
| 408 | #define DA9052_SEQA_SYSTEMEND 0X0F | |
| 409 | ||
| 410 | /* POWER SEQ B REGISTER BITS */ | |
| 411 | #define DA9052_SEQB_PARTDOWN 0XF0 | |
| 412 | #define DA9052_SEQB_MAXCOUNT 0X0F | |
| 413 | ||
| 414 | /* POWER SEQ TIMER REGISTER BITS */ | |
| 415 | #define DA9052_SEQTIMER_SEQDUMMY 0XF0 | |
| 416 | #define DA9052_SEQTIMER_SEQTIME 0X0F | |
| 417 | ||
| 418 | /*POWER SUPPLY CONTROL REGISTER BITS */ | |
| 419 | /* BUCK REGISTER A BITS */ | |
| 420 | #define DA9052_BUCKA_BPROILIM 0XC0 | |
| 421 | #define DA9052_BUCKA_BPROMODE 0X30 | |
| 422 | #define DA9052_BUCKA_BCOREILIM 0X0C | |
| 423 | #define DA9052_BUCKA_BCOREMODE 0X03 | |
| 424 | ||
| 425 | /* BUCK REGISTER B BITS */ | |
| 426 | #define DA9052_BUCKB_BERIILIM 0XC0 | |
| 427 | #define DA9052_BUCKB_BPERIMODE 0X30 | |
| 428 | #define DA9052_BUCKB_BMEMILIM 0X0C | |
| 429 | #define DA9052_BUCKB_BMEMMODE 0X03 | |
| 430 | ||
| 431 | /* BUCKCORE REGISTER BITS */ | |
| 432 | #define DA9052_BUCKCORE_BCORECONF 0X80 | |
| 433 | #define DA9052_BUCKCORE_BCOREEN 0X40 | |
| 434 | #define DA9052_BUCKCORE_VBCORE 0X3F | |
| 435 | ||
| 436 | /* BUCKPRO REGISTER BITS */ | |
| 437 | #define DA9052_BUCKPRO_BPROCONF 0X80 | |
| 438 | #define DA9052_BUCKPRO_BPROEN 0X40 | |
| 439 | #define DA9052_BUCKPRO_VBPRO 0X3F | |
| 440 | ||
| 441 | /* BUCKMEM REGISTER BITS */ | |
| 442 | #define DA9052_BUCKMEM_BMEMCONF 0X80 | |
| 443 | #define DA9052_BUCKMEM_BMEMEN 0X40 | |
| 444 | #define DA9052_BUCKMEM_VBMEM 0X3F | |
| 445 | ||
| 446 | /* BUCKPERI REGISTER BITS */ | |
| 447 | #define DA9052_BUCKPERI_BPERICONF 0X80 | |
| 448 | #define DA9052_BUCKPERI_BPERIEN 0X40 | |
| 449 | #define DA9052_BUCKPERI_BPERIHS 0X20 | |
| 450 | #define DA9052_BUCKPERI_VBPERI 0X1F | |
| 451 | ||
| 452 | /* LDO1 REGISTER BITS */ | |
| 453 | #define DA9052_LDO1_LDO1CONF 0X80 | |
| 454 | #define DA9052_LDO1_LDO1EN 0X40 | |
| 455 | #define DA9052_LDO1_VLDO1 0X1F | |
| 456 | ||
| 457 | /* LDO2 REGISTER BITS */ | |
| 458 | #define DA9052_LDO2_LDO2CONF 0X80 | |
| 459 | #define DA9052_LDO2_LDO2EN 0X40 | |
| 460 | #define DA9052_LDO2_VLDO2 0X3F | |
| 461 | ||
| 462 | /* LDO3 REGISTER BITS */ | |
| 463 | #define DA9052_LDO3_LDO3CONF 0X80 | |
| 464 | #define DA9052_LDO3_LDO3EN 0X40 | |
| 465 | #define DA9052_LDO3_VLDO3 0X3F | |
| 466 | ||
| 467 | /* LDO4 REGISTER BITS */ | |
| 468 | #define DA9052_LDO4_LDO4CONF 0X80 | |
| 469 | #define DA9052_LDO4_LDO4EN 0X40 | |
| 470 | #define DA9052_LDO4_VLDO4 0X3F | |
| 471 | ||
| 472 | /* LDO5 REGISTER BITS */ | |
| 473 | #define DA9052_LDO5_LDO5CONF 0X80 | |
| 474 | #define DA9052_LDO5_LDO5EN 0X40 | |
| 475 | #define DA9052_LDO5_VLDO5 0X3F | |
| 476 | ||
| 477 | /* LDO6 REGISTER BITS */ | |
| 478 | #define DA9052_LDO6_LDO6CONF 0X80 | |
| 479 | #define DA9052_LDO6_LDO6EN 0X40 | |
| 480 | #define DA9052_LDO6_VLDO6 0X3F | |
| 481 | ||
| 482 | /* LDO7 REGISTER BITS */ | |
| 483 | #define DA9052_LDO7_LDO7CONF 0X80 | |
| 484 | #define DA9052_LDO7_LDO7EN 0X40 | |
| 485 | #define DA9052_LDO7_VLDO7 0X3F | |
| 486 | ||
| 487 | /* LDO8 REGISTER BITS */ | |
| 488 | #define DA9052_LDO8_LDO8CONF 0X80 | |
| 489 | #define DA9052_LDO8_LDO8EN 0X40 | |
| 490 | #define DA9052_LDO8_VLDO8 0X3F | |
| 491 | ||
| 492 | /* LDO9 REGISTER BITS */ | |
| 493 | #define DA9052_LDO9_LDO9CONF 0X80 | |
| 494 | #define DA9052_LDO9_LDO9EN 0X40 | |
| 495 | #define DA9052_LDO9_VLDO9 0X3F | |
| 496 | ||
| 497 | /* LDO10 REGISTER BITS */ | |
| 498 | #define DA9052_LDO10_LDO10CONF 0X80 | |
| 499 | #define DA9052_LDO10_LDO10EN 0X40 | |
| 500 | #define DA9052_LDO10_VLDO10 0X3F | |
| 501 | ||
| 502 | /* SUPPLY REGISTER BITS */ | |
| 503 | #define DA9052_SUPPLY_VLOCK 0X80 | |
| 504 | #define DA9052_SUPPLY_VMEMSWEN 0X40 | |
| 505 | #define DA9052_SUPPLY_VPERISWEN 0X20 | |
| 506 | #define DA9052_SUPPLY_VLDO3GO 0X10 | |
| 507 | #define DA9052_SUPPLY_VLDO2GO 0X08 | |
| 508 | #define DA9052_SUPPLY_VBMEMGO 0X04 | |
| 509 | #define DA9052_SUPPLY_VBPROGO 0X02 | |
| 510 | #define DA9052_SUPPLY_VBCOREGO 0X01 | |
| 511 | ||
| 512 | /* PULLDOWN REGISTER BITS */ | |
| 513 | #define DA9052_PULLDOWN_LDO5PDDIS 0X20 | |
| 514 | #define DA9052_PULLDOWN_LDO2PDDIS 0X10 | |
| 515 | #define DA9052_PULLDOWN_LDO1PDDIS 0X08 | |
| 516 | #define DA9052_PULLDOWN_MEMPDDIS 0X04 | |
| 517 | #define DA9052_PULLDOWN_PROPDDIS 0X02 | |
| 518 | #define DA9052_PULLDOWN_COREPDDIS 0X01 | |
| 519 | ||
| 520 | /* BAT CHARGER REGISTER BITS */ | |
| 521 | /* CHARGER BUCK REGISTER BITS */ | |
| 522 | #define DA9052_CHGBUCK_CHGTEMP 0X80 | |
| 523 | #define DA9052_CHGBUCK_CHGUSBILIM 0X40 | |
| 524 | #define DA9052_CHGBUCK_CHGBUCKLP 0X20 | |
| 525 | #define DA9052_CHGBUCK_CHGBUCKEN 0X10 | |
| 526 | #define DA9052_CHGBUCK_ISETBUCK 0X0F | |
| 527 | ||
| 528 | /* WAIT COUNTER REGISTER BITS */ | |
| 529 | #define DA9052_WAITCONT_WAITDIR 0X80 | |
| 530 | #define DA9052_WAITCONT_RTCCLOCK 0X40 | |
| 531 | #define DA9052_WAITCONT_WAITMODE 0X20 | |
| 532 | #define DA9052_WAITCONT_EN32KOUT 0X10 | |
| 533 | #define DA9052_WAITCONT_DELAYTIME 0X0F | |
| 534 | ||
| 535 | /* ISET CONTROL REGISTER BITS */ | |
| 536 | #define DA9052_ISET_ISETDCIN 0XF0 | |
| 537 | #define DA9052_ISET_ISETVBUS 0X0F | |
| 538 | ||
| 539 | /* BATTERY CHARGER CONTROL REGISTER BITS */ | |
| 540 | #define DA9052_BATCHG_ICHGPRE 0XC0 | |
| 541 | #define DA9052_BATCHG_ICHGBAT 0X3F | |
| 542 | ||
| 543 | /* CHARGER COUNTER REGISTER BITS */ | |
| 544 | #define DA9052_CHG_CONT_VCHG_BAT 0XF8 | |
| 545 | #define DA9052_CHG_CONT_TCTR 0X07 | |
| 546 | ||
| 547 | /* INPUT CONTROL REGISTER BITS */ | |
| 548 | #define DA9052_INPUT_CONT_TCTR_MODE 0X80 | |
| 549 | #define DA9052_INPUT_CONT_VBUS_SUSP 0X10 | |
| 550 | #define DA9052_INPUT_CONT_DCIN_SUSP 0X08 | |
| 551 | ||
| 552 | /* CHARGING TIME REGISTER BITS */ | |
| 553 | #define DA9052_CHGTIME_CHGTIME 0XFF | |
| 554 | ||
| 555 | /* BACKUP BATTERY CONTROL REGISTER BITS */ | |
| 556 | #define DA9052_BBATCONT_BCHARGERISET 0XF0 | |
| 557 | #define DA9052_BBATCONT_BCHARGERVSET 0X0F | |
| 558 | ||
| 559 | /* LED REGISTERS BITS */ | |
| 560 | /* LED BOOST REGISTER BITS */ | |
| 561 | #define DA9052_BOOST_EBFAULT 0X80 | |
| 562 | #define DA9052_BOOST_MBFAULT 0X40 | |
| 563 | #define DA9052_BOOST_BOOSTFRQ 0X20 | |
| 564 | #define DA9052_BOOST_BOOSTILIM 0X10 | |
| 565 | #define DA9052_BOOST_LED3INEN 0X08 | |
| 566 | #define DA9052_BOOST_LED2INEN 0X04 | |
| 567 | #define DA9052_BOOST_LED1INEN 0X02 | |
| 568 | #define DA9052_BOOST_BOOSTEN 0X01 | |
| 569 | ||
| 570 | /* LED CONTROL REGISTER BITS */ | |
| 571 | #define DA9052_LEDCONT_SELLEDMODE 0X80 | |
| 572 | #define DA9052_LEDCONT_LED3ICONT 0X40 | |
| 573 | #define DA9052_LEDCONT_LED3RAMP 0X20 | |
| 574 | #define DA9052_LEDCONT_LED3EN 0X10 | |
| 575 | #define DA9052_LEDCONT_LED2RAMP 0X08 | |
| 576 | #define DA9052_LEDCONT_LED2EN 0X04 | |
| 577 | #define DA9052_LEDCONT_LED1RAMP 0X02 | |
| 578 | #define DA9052_LEDCONT_LED1EN 0X01 | |
| 579 | ||
| 580 | /* LEDMIN123 REGISTER BIT */ | |
| 581 | #define DA9052_LEDMIN123_LEDMINCURRENT 0XFF | |
| 582 | ||
| 583 | /* LED1CONF REGISTER BIT */ | |
| 584 | #define DA9052_LED1CONF_LED1CURRENT 0XFF | |
| 585 | ||
| 586 | /* LED2CONF REGISTER BIT */ | |
| 587 | #define DA9052_LED2CONF_LED2CURRENT 0XFF | |
| 588 | ||
| 589 | /* LED3CONF REGISTER BIT */ | |
| 590 | #define DA9052_LED3CONF_LED3CURRENT 0XFF | |
| 591 | ||
| 592 | /* LED COUNT REGISTER BIT */ | |
| 593 | #define DA9052_LED_CONT_DIM 0X80 | |
| 594 | ||
| 595 | /* ADC MAN REGISTERS BITS */ | |
| 596 | #define DA9052_ADC_MAN_MAN_CONV 0X10 | |
| 597 | #define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00 | |
| 598 | #define DA9052_ADC_MAN_MUXSEL_ICH 0X01 | |
| 599 | #define DA9052_ADC_MAN_MUXSEL_TBAT 0X02 | |
| 600 | #define DA9052_ADC_MAN_MUXSEL_VBAT 0X03 | |
| 601 | #define DA9052_ADC_MAN_MUXSEL_AD4 0X04 | |
| 602 | #define DA9052_ADC_MAN_MUXSEL_AD5 0X05 | |
| 603 | #define DA9052_ADC_MAN_MUXSEL_AD6 0X06 | |
| 604 | #define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09 | |
| 605 | ||
| 606 | /* ADC CONTROL REGSISTERS BITS */ | |
| 607 | #define DA9052_ADCCONT_COMP1V2EN 0X80 | |
| 608 | #define DA9052_ADCCONT_ADCMODE 0X40 | |
| 609 | #define DA9052_ADCCONT_TBATISRCEN 0X20 | |
| 610 | #define DA9052_ADCCONT_AD4ISRCEN 0X10 | |
| 611 | #define DA9052_ADCCONT_AUTOAD6EN 0X08 | |
| 612 | #define DA9052_ADCCONT_AUTOAD5EN 0X04 | |
| 613 | #define DA9052_ADCCONT_AUTOAD4EN 0X02 | |
| 614 | #define DA9052_ADCCONT_AUTOVDDEN 0X01 | |
| 615 | ||
| 616 | /* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */ | |
| 617 | #define DA9052_ADC_RES_LSB 0X03 | |
| 618 | ||
| 619 | /* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */ | |
| 620 | #define DA9052_ADCRESH_ADCRESMSB 0XFF | |
| 621 | ||
| 622 | /* VDD RES REGSISTER BIT*/ | |
| 623 | #define DA9052_VDDRES_VDDOUTRES 0XFF | |
| 624 | ||
| 625 | /* VDD MON REGSISTER BIT */ | |
| 626 | #define DA9052_VDDMON_VDDOUTMON 0XFF | |
| 627 | ||
| 628 | /* ICHG_AV REGSISTER BIT */ | |
| 629 | #define DA9052_ICHGAV_ICHGAV 0XFF | |
| 630 | ||
| 631 | /* ICHG_THD REGSISTER BIT */ | |
| 632 | #define DA9052_ICHGTHD_ICHGTHD 0XFF | |
| 633 | ||
| 634 | /* ICHG_END REGSISTER BIT */ | |
| 635 | #define DA9052_ICHGEND_ICHGEND 0XFF | |
| 636 | ||
| 637 | /* TBAT_RES REGSISTER BIT */ | |
| 638 | #define DA9052_TBATRES_TBATRES 0XFF | |
| 639 | ||
| 640 | /* TBAT_HIGHP REGSISTER BIT */ | |
| 641 | #define DA9052_TBATHIGHP_TBATHIGHP 0XFF | |
| 642 | ||
| 643 | /* TBAT_HIGHN REGSISTER BIT */ | |
| 644 | #define DA9052_TBATHIGHN_TBATHIGHN 0XFF | |
| 645 | ||
| 646 | /* TBAT_LOW REGSISTER BIT */ | |
| 647 | #define DA9052_TBATLOW_TBATLOW 0XFF | |
| 648 | ||
| 649 | /* T_OFFSET REGSISTER BIT */ | |
| 650 | #define DA9052_TOFFSET_TOFFSET 0XFF | |
| 651 | ||
| 652 | /* ADCIN4_RES REGSISTER BIT */ | |
| 653 | #define DA9052_ADCIN4RES_ADCIN4RES 0XFF | |
| 654 | ||
| 655 | /* ADCIN4_HIGH REGSISTER BIT */ | |
| 656 | #define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF | |
| 657 | ||
| 658 | /* ADCIN4_LOW REGSISTER BIT */ | |
| 659 | #define DA9052_AUTO4LOW_AUTO4LOW 0XFF | |
| 660 | ||
| 661 | /* ADCIN5_RES REGSISTER BIT */ | |
| 662 | #define DA9052_ADCIN5RES_ADCIN5RES 0XFF | |
| 663 | ||
| 664 | /* ADCIN5_HIGH REGSISTER BIT */ | |
| 665 | #define DA9052_AUTO5HIGH_AUTOHIGH 0XFF | |
| 666 | ||
| 667 | /* ADCIN5_LOW REGSISTER BIT */ | |
| 668 | #define DA9052_AUTO5LOW_AUTO5LOW 0XFF | |
| 669 | ||
| 670 | /* ADCIN6_RES REGSISTER BIT */ | |
| 671 | #define DA9052_ADCIN6RES_ADCIN6RES 0XFF | |
| 672 | ||
| 673 | /* ADCIN6_HIGH REGSISTER BIT */ | |
| 674 | #define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF | |
| 675 | ||
| 676 | /* ADCIN6_LOW REGSISTER BIT */ | |
| 677 | #define DA9052_AUTO6LOW_AUTO6LOW 0XFF | |
| 678 | ||
| 679 | /* TJUNC_RES REGSISTER BIT*/ | |
| 680 | #define DA9052_TJUNCRES_TJUNCRES 0XFF | |
| 681 | ||
| 682 | /* TSI REGISTER */ | |
| 683 | /* TSI CONTROL REGISTER A BITS */ | |
| 684 | #define DA9052_TSICONTA_TSIDELAY 0XC0 | |
| 685 | #define DA9052_TSICONTA_TSISKIP 0X38 | |
| 686 | #define DA9052_TSICONTA_TSIMODE 0X04 | |
| 687 | #define DA9052_TSICONTA_PENDETEN 0X02 | |
| 688 | #define DA9052_TSICONTA_AUTOTSIEN 0X01 | |
| 689 | ||
| 690 | /* TSI CONTROL REGISTER B BITS */ | |
| 691 | #define DA9052_TSICONTB_ADCREF 0X80 | |
| 692 | #define DA9052_TSICONTB_TSIMAN 0X40 | |
| 693 | #define DA9052_TSICONTB_TSIMUX 0X30 | |
| 694 | #define DA9052_TSICONTB_TSISEL3 0X08 | |
| 695 | #define DA9052_TSICONTB_TSISEL2 0X04 | |
| 696 | #define DA9052_TSICONTB_TSISEL1 0X02 | |
| 697 | #define DA9052_TSICONTB_TSISEL0 0X01 | |
| 698 | ||
| 699 | /* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */ | |
| 700 | #define DA9052_TSIXMSB_TSIXM 0XFF | |
| 701 | ||
| 702 | /* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */ | |
| 703 | #define DA9052_TSIYMSB_TSIYM 0XFF | |
| 704 | ||
| 705 | /* TSI CO-ORDINATE LSB RESULT REGISTER BITS */ | |
| 706 | #define DA9052_TSILSB_PENDOWN 0X40 | |
| 707 | #define DA9052_TSILSB_TSIZL 0X30 | |
| 708 | #define DA9052_TSILSB_TSIYL 0X0C | |
| 709 | #define DA9052_TSILSB_TSIXL 0X03 | |
| 710 | ||
| 711 | /* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */ | |
| 712 | #define DA9052_TSIZMSB_TSIZM 0XFF | |
| 713 | ||
| 714 | /* RTC REGISTER */ | |
| 715 | /* RTC TIMER SECONDS REGISTER BITS */ | |
| 716 | #define DA9052_COUNTS_MONITOR 0X40 | |
| 717 | #define DA9052_RTC_SEC 0X3F | |
| 718 | ||
| 719 | /* RTC TIMER MINUTES REGISTER BIT */ | |
| 720 | #define DA9052_RTC_MIN 0X3F | |
| 721 | ||
| 722 | /* RTC TIMER HOUR REGISTER BIT */ | |
| 723 | #define DA9052_RTC_HOUR 0X1F | |
| 724 | ||
| 725 | /* RTC TIMER DAYS REGISTER BIT */ | |
| 726 | #define DA9052_RTC_DAY 0X1F | |
| 727 | ||
| 728 | /* RTC TIMER MONTHS REGISTER BIT */ | |
| 729 | #define DA9052_RTC_MONTH 0X0F | |
| 730 | ||
| 731 | /* RTC TIMER YEARS REGISTER BIT */ | |
| 732 | #define DA9052_RTC_YEAR 0X3F | |
| 733 | ||
| 734 | /* RTC ALARM MINUTES REGISTER BITS */ | |
| 735 | #define DA9052_ALARMM_I_TICK_TYPE 0X80 | |
| 736 | #define DA9052_ALARMMI_ALARMTYPE 0X40 | |
| 737 | ||
| 738 | /* RTC ALARM YEARS REGISTER BITS */ | |
| 739 | #define DA9052_ALARM_Y_TICK_ON 0X80 | |
| 740 | #define DA9052_ALARM_Y_ALARM_ON 0X40 | |
| 741 | ||
| 742 | /* RTC SECONDS REGISTER A BITS */ | |
| 743 | #define DA9052_SECONDA_SECONDSA 0XFF | |
| 744 | ||
| 745 | /* RTC SECONDS REGISTER B BITS */ | |
| 746 | #define DA9052_SECONDB_SECONDSB 0XFF | |
| 747 | ||
| 748 | /* RTC SECONDS REGISTER C BITS */ | |
| 749 | #define DA9052_SECONDC_SECONDSC 0XFF | |
| 750 | ||
| 751 | /* RTC SECONDS REGISTER D BITS */ | |
| 752 | #define DA9052_SECONDD_SECONDSD 0XFF | |
| 753 | ||
| 754 | #endif | |
| 755 | /* __LINUX_MFD_DA9052_REG_H */ |