[linux-2.6-block.git] / include / linux / mfd / abx500 / ab8500.h

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License v2
 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
 */
#ifndef MFD_AB8500_H
#define MFD_AB8500_H

#include <linux/atomic.h>
#include <linux/mutex.h>
#include <linux/irqdomain.h>

struct device;

/*
 * AB IC versions
 *
 * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
 * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
 * print of version string.
 */
enum ab8500_version {
	AB8500_VERSION_AB8500 = 0x0,
	AB8500_VERSION_AB8505 = 0x1,
	AB8500_VERSION_AB9540 = 0x2,
	AB8500_VERSION_AB8540 = 0x4,
	AB8500_VERSION_UNDEFINED,
};

/* AB8500 CIDs*/
#define AB8500_CUTEARLY	0x00
#define AB8500_CUT1P0	0x10
#define AB8500_CUT1P1	0x11
#define AB8500_CUT1P2	0x12 /* Only valid for AB8540 */
#define AB8500_CUT2P0	0x20
#define AB8500_CUT3P0	0x30
#define AB8500_CUT3P3	0x33

/*
 * AB8500 bank addresses
 */
#define AB8500_M_FSM_RANK	0x0
#define AB8500_SYS_CTRL1_BLOCK	0x1
#define AB8500_SYS_CTRL2_BLOCK	0x2
#define AB8500_REGU_CTRL1	0x3
#define AB8500_REGU_CTRL2	0x4
#define AB8500_USB		0x5
#define AB8500_TVOUT		0x6
#define AB8500_DBI		0x7
#define AB8500_ECI_AV_ACC	0x8
#define AB8500_RESERVED		0x9
#define AB8500_GPADC		0xA
#define AB8500_CHARGER		0xB
#define AB8500_GAS_GAUGE	0xC
#define AB8500_AUDIO		0xD
#define AB8500_INTERRUPT	0xE
#define AB8500_RTC		0xF
#define AB8500_MISC		0x10
#define AB8500_DEVELOPMENT	0x11
#define AB8500_DEBUG		0x12
#define AB8500_PROD_TEST	0x13
#define AB8500_STE_TEST		0x14
#define AB8500_OTP_EMUL		0x15

/*
 * Interrupts
 * Values used to index into array ab8500_irq_regoffset[] defined in
 * drivers/mdf/ab8500-core.c
 */
/* Definitions for AB8500, AB9540 and AB8540 */
/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
#define AB8500_INT_MAIN_EXT_CH_NOT_OK	0 /* not 8505/9540 */
#define AB8500_INT_UN_PLUG_TV_DET	1 /* not 8505/9540/8540 */
#define AB8500_INT_PLUG_TV_DET		2 /* not 8505/9540/8540 */
#define AB8500_INT_TEMP_WARM		3
#define AB8500_INT_PON_KEY2DB_F		4
#define AB8500_INT_PON_KEY2DB_R		5
#define AB8500_INT_PON_KEY1DB_F		6
#define AB8500_INT_PON_KEY1DB_R		7
/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
#define AB8500_INT_BATT_OVV		8
#define AB8500_INT_MAIN_CH_UNPLUG_DET	10 /* not 8505/8540 */
#define AB8500_INT_MAIN_CH_PLUG_DET	11 /* not 8505/8540 */
#define AB8500_INT_VBUS_DET_F		14
#define AB8500_INT_VBUS_DET_R		15
/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
#define AB8500_INT_VBUS_CH_DROP_END	16
#define AB8500_INT_RTC_60S		17
#define AB8500_INT_RTC_ALARM		18
#define AB8540_INT_BIF_INT		19
#define AB8500_INT_BAT_CTRL_INDB	20
#define AB8500_INT_CH_WD_EXP		21
#define AB8500_INT_VBUS_OVV		22
#define AB8500_INT_MAIN_CH_DROP_END	23 /* not 8505/9540/8540 */
/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
#define AB8500_INT_CCN_CONV_ACC		24
#define AB8500_INT_INT_AUD		25
#define AB8500_INT_CCEOC		26
#define AB8500_INT_CC_INT_CALIB		27
#define AB8500_INT_LOW_BAT_F		28
#define AB8500_INT_LOW_BAT_R		29
#define AB8500_INT_BUP_CHG_NOT_OK	30
#define AB8500_INT_BUP_CHG_OK		31
/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
#define AB8500_INT_GP_HW_ADC_CONV_END	32 /* not 8505/8540 */
#define AB8500_INT_ACC_DETECT_1DB_F	33
#define AB8500_INT_ACC_DETECT_1DB_R	34
#define AB8500_INT_ACC_DETECT_22DB_F	35
#define AB8500_INT_ACC_DETECT_22DB_R	36
#define AB8500_INT_ACC_DETECT_21DB_F	37
#define AB8500_INT_ACC_DETECT_21DB_R	38
#define AB8500_INT_GP_SW_ADC_CONV_END	39
/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
#define AB8500_INT_GPIO6R		40 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO7R		41 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO8R		42 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO9R		43 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO10R		44 /* not 8540 */
#define AB8500_INT_GPIO11R		45 /* not 8540 */
#define AB8500_INT_GPIO12R		46 /* not 8505/8540 */
#define AB8500_INT_GPIO13R		47 /* not 8540 */
/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
#define AB8500_INT_GPIO24R		48 /* not 8505/8540 */
#define AB8500_INT_GPIO25R		49 /* not 8505/8540 */
#define AB8500_INT_GPIO36R		50 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37R		51 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38R		52 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39R		53 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40R		54 /* not 8540 */
#define AB8500_INT_GPIO41R		55 /* not 8540 */
/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
#define AB8500_INT_GPIO6F		56 /* not 8505/9540 */
#define AB8500_INT_GPIO7F		57 /* not 8505/9540 */
#define AB8500_INT_GPIO8F		58 /* not 8505/9540 */
#define AB8500_INT_GPIO9F		59 /* not 8505/9540 */
#define AB8500_INT_GPIO10F		60
#define AB8500_INT_GPIO11F		61
#define AB8500_INT_GPIO12F		62 /* not 8505 */
#define AB8500_INT_GPIO13F		63
/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
#define AB8500_INT_GPIO24F		64 /* not 8505/8540 */
#define AB8500_INT_GPIO25F		65 /* not 8505/8540 */
#define AB8500_INT_GPIO36F		66 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO37F		67 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO38F		68 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO39F		69 /* not 8505/9540/8540 */
#define AB8500_INT_GPIO40F		70 /* not 8540 */
#define AB8500_INT_GPIO41F		71 /* not 8540 */
/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
#define AB8500_INT_ADP_SOURCE_ERROR	72
#define AB8500_INT_ADP_SINK_ERROR	73
#define AB8500_INT_ADP_PROBE_PLUG	74
#define AB8500_INT_ADP_PROBE_UNPLUG	75
#define AB8500_INT_ADP_SENSE_OFF	76
#define AB8500_INT_USB_PHY_POWER_ERR	78
#define AB8500_INT_USB_LINK_STATUS	79
/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
#define AB8500_INT_BTEMP_LOW		80
#define AB8500_INT_BTEMP_LOW_MEDIUM	81
#define AB8500_INT_BTEMP_MEDIUM_HIGH	82
#define AB8500_INT_BTEMP_HIGH		83
/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
#define AB8500_INT_SRP_DETECT		88
#define AB8500_INT_USB_CHARGER_NOT_OKR	89
#define AB8500_INT_ID_WAKEUP_R		90
#define AB8500_INT_ID_DET_PLUGR         91 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1R		92
#define AB8500_INT_ID_DET_R2R		93
#define AB8500_INT_ID_DET_R3R		94
#define AB8500_INT_ID_DET_R4R		95
/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
#define AB8500_INT_ID_WAKEUP_F		96 /* not 8505/9540 */
#define AB8500_INT_ID_DET_PLUGF		97 /* 8505/9540 cut2.0 */
#define AB8500_INT_ID_DET_R1F		98 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R2F		99 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R3F		100 /* not 8505/9540 */
#define AB8500_INT_ID_DET_R4F		101 /* not 8505/9540 */
#define AB8500_INT_CHAUTORESTARTAFTSEC	102 /* not 8505/9540 */
#define AB8500_INT_CHSTOPBYSEC		103
/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
#define AB8500_INT_USB_CH_TH_PROT_F	104
#define AB8500_INT_USB_CH_TH_PROT_R	105
#define AB8500_INT_MAIN_CH_TH_PROT_F	106 /* not 8505/9540 */
#define AB8500_INT_MAIN_CH_TH_PROT_R	107 /* not 8505/9540 */
#define AB8500_INT_CHCURLIMNOHSCHIRP	109
#define AB8500_INT_CHCURLIMHSCHIRP	110
#define AB8500_INT_XTAL32K_KO		111

/* Definitions for AB9540 / AB8505 */
/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
#define AB9540_INT_GPIO50R		113 /* not 8540 */
#define AB9540_INT_GPIO51R		114 /* not 8505/8540 */
#define AB9540_INT_GPIO52R		115 /* not 8540 */
#define AB9540_INT_GPIO53R		116 /* not 8540 */
#define AB9540_INT_GPIO54R		117 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_R	118
/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
#define AB9540_INT_GPIO50F		121 /* not 8540 */
#define AB9540_INT_GPIO51F		122 /* not 8505/8540 */
#define AB9540_INT_GPIO52F		123 /* not 8540 */
#define AB9540_INT_GPIO53F		124 /* not 8540 */
#define AB9540_INT_GPIO54F		125 /* not 8505/8540 */
#define AB9540_INT_IEXT_CH_RF_BFN_F	126
/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
#define AB8505_INT_KEYSTUCK		128
#define AB8505_INT_IKR			129
#define AB8505_INT_IKP			130
#define AB8505_INT_KP			131
#define AB8505_INT_KEYDEGLITCH		132
#define AB8505_INT_MODPWRSTATUSF	134
#define AB8505_INT_MODPWRSTATUSR	135
/* ab8500_irq_regoffset[17] -> IT[Source|Latch|Mask]6 */
#define AB8500_INT_HOOK_DET_NEG_F	138
#define AB8500_INT_HOOK_DET_NEG_R	139
#define AB8500_INT_HOOK_DET_POS_F	140
#define AB8500_INT_HOOK_DET_POS_R	141
#define AB8500_INT_PLUG_DET_COMP_F	142
#define AB8500_INT_PLUG_DET_COMP_R	143
/* ab8500_irq_regoffset[18] -> IT[Source|Latch|Mask]23 */
#define AB8505_INT_COLL			144
#define AB8505_INT_RESERR		145
#define AB8505_INT_FRAERR		146
#define AB8505_INT_COMERR		147
#define AB8505_INT_SPDSET		148
#define AB8505_INT_DSENT		149
#define AB8505_INT_DREC			150
#define AB8505_INT_ACC_INT		151
/* ab8500_irq_regoffset[19] -> IT[Source|Latch|Mask]24 */
#define AB8505_INT_NOPINT		152
/* ab8540_irq_regoffset[20] -> IT[Source|Latch|Mask]26 */
#define AB8540_INT_IDPLUGDETCOMPF	160
#define AB8540_INT_IDPLUGDETCOMPR	161
#define AB8540_INT_FMDETCOMPLOF		162
#define AB8540_INT_FMDETCOMPLOR		163
#define AB8540_INT_FMDETCOMPHIF		164
#define AB8540_INT_FMDETCOMPHIR		165
#define AB8540_INT_ID5VDETCOMPF		166
#define AB8540_INT_ID5VDETCOMPR		167
/* ab8540_irq_regoffset[21] -> IT[Source|Latch|Mask]27 */
#define AB8540_INT_GPIO43F		168
#define AB8540_INT_GPIO43R		169
#define AB8540_INT_GPIO44F		170
#define AB8540_INT_GPIO44R		171
#define AB8540_INT_KEYPOSDETCOMPF	172
#define AB8540_INT_KEYPOSDETCOMPR	173
#define AB8540_INT_KEYNEGDETCOMPF	174
#define AB8540_INT_KEYNEGDETCOMPR	175
/* ab8540_irq_regoffset[22] -> IT[Source|Latch|Mask]28 */
#define AB8540_INT_GPIO1VBATF		176
#define AB8540_INT_GPIO1VBATR		177
#define AB8540_INT_GPIO2VBATF		178
#define AB8540_INT_GPIO2VBATR		179
#define AB8540_INT_GPIO3VBATF		180
#define AB8540_INT_GPIO3VBATR		181
#define AB8540_INT_GPIO4VBATF		182
#define AB8540_INT_GPIO4VBATR		183
/* ab8540_irq_regoffset[23] -> IT[Source|Latch|Mask]29 */
#define AB8540_INT_SYSCLKREQ2F		184
#define AB8540_INT_SYSCLKREQ2R		185
#define AB8540_INT_SYSCLKREQ3F		186
#define AB8540_INT_SYSCLKREQ3R		187
#define AB8540_INT_SYSCLKREQ4F		188
#define AB8540_INT_SYSCLKREQ4R		189
#define AB8540_INT_SYSCLKREQ5F		190
#define AB8540_INT_SYSCLKREQ5R		191
/* ab8540_irq_regoffset[24] -> IT[Source|Latch|Mask]30 */
#define AB8540_INT_PWMOUT1F		192
#define AB8540_INT_PWMOUT1R		193
#define AB8540_INT_PWMCTRL0F		194
#define AB8540_INT_PWMCTRL0R		195
#define AB8540_INT_PWMCTRL1F		196
#define AB8540_INT_PWMCTRL1R		197
#define AB8540_INT_SYSCLKREQ6F		198
#define AB8540_INT_SYSCLKREQ6R		199
/* ab8540_irq_regoffset[25] -> IT[Source|Latch|Mask]31 */
#define AB8540_INT_PWMEXTVIBRA1F	200
#define AB8540_INT_PWMEXTVIBRA1R	201
#define AB8540_INT_PWMEXTVIBRA2F	202
#define AB8540_INT_PWMEXTVIBRA2R	203
#define AB8540_INT_PWMOUT2F		204
#define AB8540_INT_PWMOUT2R		205
#define AB8540_INT_PWMOUT3F		206
#define AB8540_INT_PWMOUT3R		207
/* ab8540_irq_regoffset[26] -> IT[Source|Latch|Mask]32 */
#define AB8540_INT_ADDATA2F		208
#define AB8540_INT_ADDATA2R		209
#define AB8540_INT_DADATA2F		210
#define AB8540_INT_DADATA2R		211
#define AB8540_INT_FSYNC2F		212
#define AB8540_INT_FSYNC2R		213
#define AB8540_INT_BITCLK2F		214
#define AB8540_INT_BITCLK2R		215
/* ab8540_irq_regoffset[27] -> IT[Source|Latch|Mask]33 */
#define AB8540_INT_RTC_1S		216

/*
 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
 * entire platform. This is a "compile time" constant so this must be set to
 * the largest possible value that may be encountered with different AB SOCs.
 * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
 * which is larger.
 */
#define AB8500_NR_IRQS			112
#define AB8505_NR_IRQS			153
#define AB9540_NR_IRQS			153
#define AB8540_NR_IRQS			216
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS		AB8540_NR_IRQS

#define AB8500_NUM_IRQ_REGS		14
#define AB9540_NUM_IRQ_REGS		20
#define AB8540_NUM_IRQ_REGS		27

/* Turn On Status Event */
#define AB8500_POR_ON_VBAT		0x01
#define AB8500_POW_KEY_1_ON		0x02
#define AB8500_POW_KEY_2_ON		0x04
#define AB8500_RTC_ALARM		0x08
#define AB8500_MAIN_CH_DET		0x10
#define AB8500_VBUS_DET			0x20
#define AB8500_USB_ID_DET		0x40

/**
 * struct ab8500 - ab8500 internal structure
 * @dev: parent device
 * @lock: read/write operations lock
 * @irq_lock: genirq bus lock
 * @transfer_ongoing: 0 if no transfer ongoing
 * @irq: irq line
 * @irq_domain: irq domain
 * @version: chip version id (e.g. ab8500 or ab9540)
 * @chip_id: chip revision id
 * @write: register write
 * @write_masked: masked register write
 * @read: register read
 * @rx_buf: rx buf for SPI
 * @tx_buf: tx buf for SPI
 * @mask: cache of IRQ regs for bus lock
 * @oldmask: cache of previous IRQ regs for bus lock
 * @mask_size: Actual number of valid entries in mask[], oldmask[] and
 * irq_reg_offset
 * @irq_reg_offset: Array of offsets into IRQ registers
 */
struct ab8500 {
	struct device	*dev;
	struct mutex	lock;
	struct mutex	irq_lock;
	atomic_t	transfer_ongoing;
	int		irq_base;
	int		irq;
	struct irq_domain  *domain;
	enum ab8500_version version;
	u8		chip_id;

	int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
	int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
	int (*read)(struct ab8500 *ab8500, u16 addr);

	unsigned long	tx_buf[4];
	unsigned long	rx_buf[4];

	u8 *mask;
	u8 *oldmask;
	int mask_size;
	const int *irq_reg_offset;
	int it_latchhier_num;
};

struct ab8500_regulator_platform_data;
struct ab8500_gpio_platform_data;
struct ab8500_codec_platform_data;
struct ab8500_sysctrl_platform_data;

/**
 * struct ab8500_platform_data - AB8500 platform data
 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
 * @init: board-specific initialization after detection of ab8500
 * @regulator: machine-specific constraints for regulators
 */
struct ab8500_platform_data {
	int irq_base;
	void (*init) (struct ab8500 *);
	struct ab8500_regulator_platform_data *regulator;
	struct abx500_gpio_platform_data *gpio;
	struct ab8500_codec_platform_data *codec;
	struct ab8500_sysctrl_platform_data *sysctrl;
};

extern int ab8500_init(struct ab8500 *ab8500,
				 enum ab8500_version version);
extern int ab8500_exit(struct ab8500 *ab8500);

extern int ab8500_suspend(struct ab8500 *ab8500);

static inline int is_ab8500(struct ab8500 *ab)
{
	return ab->version == AB8500_VERSION_AB8500;
}

static inline int is_ab8505(struct ab8500 *ab)
{
	return ab->version == AB8500_VERSION_AB8505;
}

static inline int is_ab9540(struct ab8500 *ab)
{
	return ab->version == AB8500_VERSION_AB9540;
}

static inline int is_ab8540(struct ab8500 *ab)
{
	return ab->version == AB8500_VERSION_AB8540;
}

/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
{
	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
}

/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
{
	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
}

/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
{
	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
}

static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
{
	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
}

/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0(struct ab8500 *ab)
{
	return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}

static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
{
	return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
}

static inline int is_ab8505_2p0(struct ab8500 *ab)
{
	return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
}

static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
{
	return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
}

static inline int is_ab9540_2p0(struct ab8500 *ab)
{
	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
}

/*
 * Be careful, the marketing name for this chip is 2.1
 * but the value read from the chip is 3.0 (0x30)
 */
static inline int is_ab9540_3p0(struct ab8500 *ab)
{
	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
}

static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
{
	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
}

static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
{
	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
}

static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
{
	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
}

static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
{
	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
}

static inline int is_ab8540_2p0(struct ab8500 *ab)
{
	return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
}

static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
{
	return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
}

static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
{
	return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
}

void ab8500_override_turn_on_stat(u8 mask, u8 set);

#ifdef CONFIG_AB8500_DEBUG
void ab8500_dump_all_banks(struct device *dev);
void ab8500_debug_register_interrupt(int line);
#else
static inline void ab8500_dump_all_banks(struct device *dev) {}
static inline void ab8500_debug_register_interrupt(int line) {}
#endif

#endif /* MFD_AB8500_H */
Commit	Line	Data
62579266 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License v2
	5	* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
	6	*/
	7	#ifndef MFD_AB8500_H
	8	#define MFD_AB8500_H
	9
112a80d2	10	#include <linux/atomic.h>
313162d0	11	#include <linux/mutex.h>
06e589ef	12	#include <linux/irqdomain.h>
313162d0 PG	13
313162d0 PG	14	struct device;
62579266	15
0f620837 LW	16	/*
	17	* AB IC versions
	18	*
	19	* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
	20	* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
	21	* print of version string.
	22	*/
	23	enum ab8500_version {
	24	AB8500_VERSION_AB8500 = 0x0,
	25	AB8500_VERSION_AB8505 = 0x1,
	26	AB8500_VERSION_AB9540 = 0x2,
56813f79	27	AB8500_VERSION_AB8540 = 0x4,
0f620837 LW	28	AB8500_VERSION_UNDEFINED,
	29	};
	30
	31	/* AB8500 CIDs*/
	32	#define AB8500_CUTEARLY 0x00
	33	#define AB8500_CUT1P0 0x10
	34	#define AB8500_CUT1P1 0x11
56813f79	35	#define AB8500_CUT1P2 0x12 /* Only valid for AB8540 */
0f620837 LW	36	#define AB8500_CUT2P0 0x20
	37	#define AB8500_CUT3P0 0x30
	38	#define AB8500_CUT3P3 0x33
62579266	39
47c16975 MW	40	/*
	41	* AB8500 bank addresses
	42	*/
56813f79	43	#define AB8500_M_FSM_RANK 0x0
47c16975 MW	44	#define AB8500_SYS_CTRL1_BLOCK 0x1
	45	#define AB8500_SYS_CTRL2_BLOCK 0x2
	46	#define AB8500_REGU_CTRL1 0x3
	47	#define AB8500_REGU_CTRL2 0x4
	48	#define AB8500_USB 0x5
	49	#define AB8500_TVOUT 0x6
	50	#define AB8500_DBI 0x7
	51	#define AB8500_ECI_AV_ACC 0x8
	52	#define AB8500_RESERVED 0x9
	53	#define AB8500_GPADC 0xA
	54	#define AB8500_CHARGER 0xB
	55	#define AB8500_GAS_GAUGE 0xC
	56	#define AB8500_AUDIO 0xD
	57	#define AB8500_INTERRUPT 0xE
	58	#define AB8500_RTC 0xF
	59	#define AB8500_MISC 0x10
0a1b0897	60	#define AB8500_DEVELOPMENT 0x11
47c16975 MW	61	#define AB8500_DEBUG 0x12
47c16975 MW	62	#define AB8500_PROD_TEST 0x13
56813f79	63	#define AB8500_STE_TEST 0x14
47c16975 MW	64	#define AB8500_OTP_EMUL 0x15
47c16975 MW	65
62579266 RV	66	/*
62579266 RV	67	* Interrupts
d6255529 LW	68	* Values used to index into array ab8500_irq_regoffset[] defined in
d6255529 LW	69	* drivers/mdf/ab8500-core.c
62579266	70	*/
56813f79	71	/* Definitions for AB8500, AB9540 and AB8540 */
d6255529	72	/* ab8500_irq_regoffset[0] -> IT[Source\|Latch\|Mask]1 */
a982362c	73	#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
56813f79 LW	74	#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540/8540 */
56813f79 LW	75	#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540/8540 */
62579266 RV	76	#define AB8500_INT_TEMP_WARM 3
	77	#define AB8500_INT_PON_KEY2DB_F 4
	78	#define AB8500_INT_PON_KEY2DB_R 5
	79	#define AB8500_INT_PON_KEY1DB_F 6
	80	#define AB8500_INT_PON_KEY1DB_R 7
d6255529	81	/* ab8500_irq_regoffset[1] -> IT[Source\|Latch\|Mask]2 */
62579266	82	#define AB8500_INT_BATT_OVV 8
56813f79 LW	83	#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505/8540 */
56813f79 LW	84	#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505/8540 */
62579266 RV	85	#define AB8500_INT_VBUS_DET_F 14
62579266 RV	86	#define AB8500_INT_VBUS_DET_R 15
d6255529	87	/* ab8500_irq_regoffset[2] -> IT[Source\|Latch\|Mask]3 */
62579266 RV	88	#define AB8500_INT_VBUS_CH_DROP_END 16
	89	#define AB8500_INT_RTC_60S 17
	90	#define AB8500_INT_RTC_ALARM 18
56813f79	91	#define AB8540_INT_BIF_INT 19
62579266 RV	92	#define AB8500_INT_BAT_CTRL_INDB 20
	93	#define AB8500_INT_CH_WD_EXP 21
	94	#define AB8500_INT_VBUS_OVV 22
56813f79	95	#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540/8540 */
d6255529	96	/* ab8500_irq_regoffset[3] -> IT[Source\|Latch\|Mask]4 */
62579266 RV	97	#define AB8500_INT_CCN_CONV_ACC 24
	98	#define AB8500_INT_INT_AUD 25
	99	#define AB8500_INT_CCEOC 26
	100	#define AB8500_INT_CC_INT_CALIB 27
	101	#define AB8500_INT_LOW_BAT_F 28
	102	#define AB8500_INT_LOW_BAT_R 29
	103	#define AB8500_INT_BUP_CHG_NOT_OK 30
	104	#define AB8500_INT_BUP_CHG_OK 31
d6255529	105	/* ab8500_irq_regoffset[4] -> IT[Source\|Latch\|Mask]5 */
56813f79	106	#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505/8540 */
62579266 RV	107	#define AB8500_INT_ACC_DETECT_1DB_F 33
	108	#define AB8500_INT_ACC_DETECT_1DB_R 34
	109	#define AB8500_INT_ACC_DETECT_22DB_F 35
	110	#define AB8500_INT_ACC_DETECT_22DB_R 36
	111	#define AB8500_INT_ACC_DETECT_21DB_F 37
	112	#define AB8500_INT_ACC_DETECT_21DB_R 38
	113	#define AB8500_INT_GP_SW_ADC_CONV_END 39
d6255529	114	/* ab8500_irq_regoffset[5] -> IT[Source\|Latch\|Mask]7 */
56813f79 LW	115	#define AB8500_INT_GPIO6R 40 /* not 8505/9540/8540 */
	116	#define AB8500_INT_GPIO7R 41 /* not 8505/9540/8540 */
	117	#define AB8500_INT_GPIO8R 42 /* not 8505/9540/8540 */
	118	#define AB8500_INT_GPIO9R 43 /* not 8505/9540/8540 */
	119	#define AB8500_INT_GPIO10R 44 /* not 8540 */
	120	#define AB8500_INT_GPIO11R 45 /* not 8540 */
	121	#define AB8500_INT_GPIO12R 46 /* not 8505/8540 */
	122	#define AB8500_INT_GPIO13R 47 /* not 8540 */
d6255529	123	/* ab8500_irq_regoffset[6] -> IT[Source\|Latch\|Mask]8 */
56813f79 LW	124	#define AB8500_INT_GPIO24R 48 /* not 8505/8540 */
	125	#define AB8500_INT_GPIO25R 49 /* not 8505/8540 */
	126	#define AB8500_INT_GPIO36R 50 /* not 8505/9540/8540 */
	127	#define AB8500_INT_GPIO37R 51 /* not 8505/9540/8540 */
	128	#define AB8500_INT_GPIO38R 52 /* not 8505/9540/8540 */
	129	#define AB8500_INT_GPIO39R 53 /* not 8505/9540/8540 */
	130	#define AB8500_INT_GPIO40R 54 /* not 8540 */
	131	#define AB8500_INT_GPIO41R 55 /* not 8540 */
d6255529	132	/* ab8500_irq_regoffset[7] -> IT[Source\|Latch\|Mask]9 */
a982362c BJ	133	#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
	134	#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
	135	#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
	136	#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
0cb3fcd7 BB	137	#define AB8500_INT_GPIO10F 60
0cb3fcd7 BB	138	#define AB8500_INT_GPIO11F 61
a982362c	139	#define AB8500_INT_GPIO12F 62 /* not 8505 */
0cb3fcd7	140	#define AB8500_INT_GPIO13F 63
d6255529	141	/* ab8500_irq_regoffset[8] -> IT[Source\|Latch\|Mask]10 */
56813f79 LW	142	#define AB8500_INT_GPIO24F 64 /* not 8505/8540 */
	143	#define AB8500_INT_GPIO25F 65 /* not 8505/8540 */
	144	#define AB8500_INT_GPIO36F 66 /* not 8505/9540/8540 */
	145	#define AB8500_INT_GPIO37F 67 /* not 8505/9540/8540 */
	146	#define AB8500_INT_GPIO38F 68 /* not 8505/9540/8540 */
	147	#define AB8500_INT_GPIO39F 69 /* not 8505/9540/8540 */
	148	#define AB8500_INT_GPIO40F 70 /* not 8540 */
	149	#define AB8500_INT_GPIO41F 71 /* not 8540 */
d6255529	150	/* ab8500_irq_regoffset[9] -> IT[Source\|Latch\|Mask]12 */
92d50a41 MW	151	#define AB8500_INT_ADP_SOURCE_ERROR 72
	152	#define AB8500_INT_ADP_SINK_ERROR 73
	153	#define AB8500_INT_ADP_PROBE_PLUG 74
	154	#define AB8500_INT_ADP_PROBE_UNPLUG 75
	155	#define AB8500_INT_ADP_SENSE_OFF 76
	156	#define AB8500_INT_USB_PHY_POWER_ERR 78
	157	#define AB8500_INT_USB_LINK_STATUS 79
d6255529	158	/* ab8500_irq_regoffset[10] -> IT[Source\|Latch\|Mask]19 */
92d50a41 MW	159	#define AB8500_INT_BTEMP_LOW 80
	160	#define AB8500_INT_BTEMP_LOW_MEDIUM 81
	161	#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
	162	#define AB8500_INT_BTEMP_HIGH 83
d6255529	163	/* ab8500_irq_regoffset[11] -> IT[Source\|Latch\|Mask]20 */
a982362c BJ	164	#define AB8500_INT_SRP_DETECT 88
a982362c BJ	165	#define AB8500_INT_USB_CHARGER_NOT_OKR 89
92d50a41	166	#define AB8500_INT_ID_WAKEUP_R 90
56813f79	167	#define AB8500_INT_ID_DET_PLUGR 91 /* 8505/9540 cut2.0 */
92d50a41 MW	168	#define AB8500_INT_ID_DET_R1R 92
	169	#define AB8500_INT_ID_DET_R2R 93
	170	#define AB8500_INT_ID_DET_R3R 94
	171	#define AB8500_INT_ID_DET_R4R 95
d6255529	172	/* ab8500_irq_regoffset[12] -> IT[Source\|Latch\|Mask]21 */
56813f79 LW	173	#define AB8500_INT_ID_WAKEUP_F 96 /* not 8505/9540 */
	174	#define AB8500_INT_ID_DET_PLUGF 97 /* 8505/9540 cut2.0 */
	175	#define AB8500_INT_ID_DET_R1F 98 /* not 8505/9540 */
	176	#define AB8500_INT_ID_DET_R2F 99 /* not 8505/9540 */
	177	#define AB8500_INT_ID_DET_R3F 100 /* not 8505/9540 */
	178	#define AB8500_INT_ID_DET_R4F 101 /* not 8505/9540 */
	179	#define AB8500_INT_CHAUTORESTARTAFTSEC 102 /* not 8505/9540 */
a982362c	180	#define AB8500_INT_CHSTOPBYSEC 103
d6255529	181	/* ab8500_irq_regoffset[13] -> IT[Source\|Latch\|Mask]22 */
92d50a41	182	#define AB8500_INT_USB_CH_TH_PROT_F 104
56813f79	183	#define AB8500_INT_USB_CH_TH_PROT_R 105
a982362c BJ	184	#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
	185	#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
	186	#define AB8500_INT_CHCURLIMNOHSCHIRP 109
	187	#define AB8500_INT_CHCURLIMHSCHIRP 110
	188	#define AB8500_INT_XTAL32K_KO 111
62579266	189
56813f79	190	/* Definitions for AB9540 / AB8505 */
d6255529	191	/* ab8500_irq_regoffset[14] -> IT[Source\|Latch\|Mask]13 */
56813f79 LW	192	#define AB9540_INT_GPIO50R 113 /* not 8540 */
	193	#define AB9540_INT_GPIO51R 114 /* not 8505/8540 */
	194	#define AB9540_INT_GPIO52R 115 /* not 8540 */
	195	#define AB9540_INT_GPIO53R 116 /* not 8540 */
	196	#define AB9540_INT_GPIO54R 117 /* not 8505/8540 */
d6255529	197	#define AB9540_INT_IEXT_CH_RF_BFN_R 118
d6255529	198	/* ab8500_irq_regoffset[15] -> IT[Source\|Latch\|Mask]14 */
56813f79 LW	199	#define AB9540_INT_GPIO50F 121 /* not 8540 */
	200	#define AB9540_INT_GPIO51F 122 /* not 8505/8540 */
	201	#define AB9540_INT_GPIO52F 123 /* not 8540 */
	202	#define AB9540_INT_GPIO53F 124 /* not 8540 */
	203	#define AB9540_INT_GPIO54F 125 /* not 8505/8540 */
	204	#define AB9540_INT_IEXT_CH_RF_BFN_F 126
44f72e53 VS	205	/* ab8500_irq_regoffset[16] -> IT[Source\|Latch\|Mask]25 */
	206	#define AB8505_INT_KEYSTUCK 128
	207	#define AB8505_INT_IKR 129
	208	#define AB8505_INT_IKP 130
	209	#define AB8505_INT_KP 131
	210	#define AB8505_INT_KEYDEGLITCH 132
	211	#define AB8505_INT_MODPWRSTATUSF 134
	212	#define AB8505_INT_MODPWRSTATUSR 135
56813f79 LW	213	/* ab8500_irq_regoffset[17] -> IT[Source\|Latch\|Mask]6 */
	214	#define AB8500_INT_HOOK_DET_NEG_F 138
	215	#define AB8500_INT_HOOK_DET_NEG_R 139
	216	#define AB8500_INT_HOOK_DET_POS_F 140
	217	#define AB8500_INT_HOOK_DET_POS_R 141
	218	#define AB8500_INT_PLUG_DET_COMP_F 142
	219	#define AB8500_INT_PLUG_DET_COMP_R 143
	220	/* ab8500_irq_regoffset[18] -> IT[Source\|Latch\|Mask]23 */
	221	#define AB8505_INT_COLL 144
	222	#define AB8505_INT_RESERR 145
	223	#define AB8505_INT_FRAERR 146
	224	#define AB8505_INT_COMERR 147
	225	#define AB8505_INT_SPDSET 148
	226	#define AB8505_INT_DSENT 149
	227	#define AB8505_INT_DREC 150
	228	#define AB8505_INT_ACC_INT 151
	229	/* ab8500_irq_regoffset[19] -> IT[Source\|Latch\|Mask]24 */
	230	#define AB8505_INT_NOPINT 152
	231	/* ab8540_irq_regoffset[20] -> IT[Source\|Latch\|Mask]26 */
	232	#define AB8540_INT_IDPLUGDETCOMPF 160
	233	#define AB8540_INT_IDPLUGDETCOMPR 161
	234	#define AB8540_INT_FMDETCOMPLOF 162
	235	#define AB8540_INT_FMDETCOMPLOR 163
	236	#define AB8540_INT_FMDETCOMPHIF 164
	237	#define AB8540_INT_FMDETCOMPHIR 165
	238	#define AB8540_INT_ID5VDETCOMPF 166
	239	#define AB8540_INT_ID5VDETCOMPR 167
	240	/* ab8540_irq_regoffset[21] -> IT[Source\|Latch\|Mask]27 */
	241	#define AB8540_INT_GPIO43F 168
	242	#define AB8540_INT_GPIO43R 169
	243	#define AB8540_INT_GPIO44F 170
	244	#define AB8540_INT_GPIO44R 171
	245	#define AB8540_INT_KEYPOSDETCOMPF 172
	246	#define AB8540_INT_KEYPOSDETCOMPR 173
	247	#define AB8540_INT_KEYNEGDETCOMPF 174
	248	#define AB8540_INT_KEYNEGDETCOMPR 175
	249	/* ab8540_irq_regoffset[22] -> IT[Source\|Latch\|Mask]28 */
	250	#define AB8540_INT_GPIO1VBATF 176
	251	#define AB8540_INT_GPIO1VBATR 177
	252	#define AB8540_INT_GPIO2VBATF 178
	253	#define AB8540_INT_GPIO2VBATR 179
	254	#define AB8540_INT_GPIO3VBATF 180
	255	#define AB8540_INT_GPIO3VBATR 181
	256	#define AB8540_INT_GPIO4VBATF 182
	257	#define AB8540_INT_GPIO4VBATR 183
	258	/* ab8540_irq_regoffset[23] -> IT[Source\|Latch\|Mask]29 */
	259	#define AB8540_INT_SYSCLKREQ2F 184
	260	#define AB8540_INT_SYSCLKREQ2R 185
	261	#define AB8540_INT_SYSCLKREQ3F 186
	262	#define AB8540_INT_SYSCLKREQ3R 187
	263	#define AB8540_INT_SYSCLKREQ4F 188
	264	#define AB8540_INT_SYSCLKREQ4R 189
	265	#define AB8540_INT_SYSCLKREQ5F 190
	266	#define AB8540_INT_SYSCLKREQ5R 191
	267	/* ab8540_irq_regoffset[24] -> IT[Source\|Latch\|Mask]30 */
	268	#define AB8540_INT_PWMOUT1F 192
	269	#define AB8540_INT_PWMOUT1R 193
	270	#define AB8540_INT_PWMCTRL0F 194
	271	#define AB8540_INT_PWMCTRL0R 195
	272	#define AB8540_INT_PWMCTRL1F 196
	273	#define AB8540_INT_PWMCTRL1R 197
	274	#define AB8540_INT_SYSCLKREQ6F 198
	275	#define AB8540_INT_SYSCLKREQ6R 199
	276	/* ab8540_irq_regoffset[25] -> IT[Source\|Latch\|Mask]31 */
277	#define AB8540_INT_PWMEXTVIBRA1F 200
278	#define AB8540_INT_PWMEXTVIBRA1R 201
279	#define AB8540_INT_PWMEXTVIBRA2F 202
280	#define AB8540_INT_PWMEXTVIBRA2R 203
281	#define AB8540_INT_PWMOUT2F 204
282	#define AB8540_INT_PWMOUT2R 205
283	#define AB8540_INT_PWMOUT3F 206
284	#define AB8540_INT_PWMOUT3R 207
285	/* ab8540_irq_regoffset[26] -> IT[Source\|Latch\|Mask]32 */
286	#define AB8540_INT_ADDATA2F 208
287	#define AB8540_INT_ADDATA2R 209
288	#define AB8540_INT_DADATA2F 210
289	#define AB8540_INT_DADATA2R 211
290	#define AB8540_INT_FSYNC2F 212
291	#define AB8540_INT_FSYNC2R 213
292	#define AB8540_INT_BITCLK2F 214
293	#define AB8540_INT_BITCLK2R 215
9c717cf3 AT	294	/* ab8540_irq_regoffset[27] -> IT[Source\|Latch\|Mask]33 */
9c717cf3 AT	295	#define AB8540_INT_RTC_1S 216
62579266	296
d6255529 LW	297	/*
	298	* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
	299	* entire platform. This is a "compile time" constant so this must be set to
	300	* the largest possible value that may be encountered with different AB SOCs.
	301	* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
	302	* which is larger.
	303	*/
92d50a41	304	#define AB8500_NR_IRQS 112
56813f79 LW	305	#define AB8505_NR_IRQS 153
	306	#define AB9540_NR_IRQS 153
	307	#define AB8540_NR_IRQS 216
d6255529	308	/* This is set to the roof of any AB8500 chip variant IRQ counts */
56813f79	309	#define AB8500_MAX_NR_IRQS AB8540_NR_IRQS
d6255529	310
92d50a41	311	#define AB8500_NUM_IRQ_REGS 14
56813f79 LW	312	#define AB9540_NUM_IRQ_REGS 20
	313	#define AB8540_NUM_IRQ_REGS 27
	314
	315	/* Turn On Status Event */
	316	#define AB8500_POR_ON_VBAT 0x01
	317	#define AB8500_POW_KEY_1_ON 0x02
	318	#define AB8500_POW_KEY_2_ON 0x04
	319	#define AB8500_RTC_ALARM 0x08
	320	#define AB8500_MAIN_CH_DET 0x10
	321	#define AB8500_VBUS_DET 0x20
	322	#define AB8500_USB_ID_DET 0x40
62579266 RV	323
	324	/**
	325	* struct ab8500 - ab8500 internal structure
	326	* @dev: parent device
	327	* @lock: read/write operations lock
	328	* @irq_lock: genirq bus lock
112a80d2	329	* @transfer_ongoing: 0 if no transfer ongoing
62579266	330	* @irq: irq line
06e589ef	331	* @irq_domain: irq domain
0f620837	332	* @version: chip version id (e.g. ab8500 or ab9540)
adceed62	333	* @chip_id: chip revision id
62579266	334	* @write: register write
bc628fd1	335	* @write_masked: masked register write
62579266 RV	336	* @read: register read
	337	* @rx_buf: rx buf for SPI
	338	* @tx_buf: tx buf for SPI
	339	* @mask: cache of IRQ regs for bus lock
	340	* @oldmask: cache of previous IRQ regs for bus lock
2ced445e LW	341	* @mask_size: Actual number of valid entries in mask[], oldmask[] and
	342	* irq_reg_offset
	343	* @irq_reg_offset: Array of offsets into IRQ registers
62579266 RV	344	*/
	345	struct ab8500 {
	346	struct device *dev;
	347	struct mutex lock;
	348	struct mutex irq_lock;
112a80d2	349	atomic_t transfer_ongoing;
62579266 RV	350	int irq_base;
62579266 RV	351	int irq;
06e589ef	352	struct irq_domain *domain;
0f620837	353	enum ab8500_version version;
47c16975	354	u8 chip_id;
62579266	355
bc628fd1 MN	356	int (write)(struct ab8500 ab8500, u16 addr, u8 data);
	357	int (write_masked)(struct ab8500 ab8500, u16 addr, u8 mask, u8 data);
	358	int (read)(struct ab8500 ab8500, u16 addr);
62579266 RV	359
	360	unsigned long tx_buf[4];
	361	unsigned long rx_buf[4];
	362
2ced445e LW	363	u8 *mask;
	364	u8 *oldmask;
	365	int mask_size;
	366	const int *irq_reg_offset;
3e1a498f	367	int it_latchhier_num;
62579266 RV	368	};
62579266 RV	369
c4e67bbc	370	struct ab8500_regulator_platform_data;
0cb3fcd7	371	struct ab8500_gpio_platform_data;
f242e50e	372	struct ab8500_codec_platform_data;
1abf063f	373	struct ab8500_sysctrl_platform_data;
549931f9	374
62579266 RV	375	/**
	376	* struct ab8500_platform_data - AB8500 platform data
	377	* @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
	378	* @init: board-specific initialization after detection of ab8500
549931f9	379	* @regulator: machine-specific constraints for regulators
62579266 RV	380	*/
	381	struct ab8500_platform_data {
	382	int irq_base;
	383	void (init) (struct ab8500 );
c4e67bbc	384	struct ab8500_regulator_platform_data *regulator;
0493e649	385	struct abx500_gpio_platform_data *gpio;
f242e50e	386	struct ab8500_codec_platform_data *codec;
1abf063f	387	struct ab8500_sysctrl_platform_data *sysctrl;
62579266 RV	388	};
62579266 RV	389
f791be49	390	extern int ab8500_init(struct ab8500 *ab8500,
0f620837	391	enum ab8500_version version);
4740f73f	392	extern int ab8500_exit(struct ab8500 *ab8500);
62579266	393
112a80d2 JA	394	extern int ab8500_suspend(struct ab8500 *ab8500);
112a80d2 JA	395
0f620837 LW	396	static inline int is_ab8500(struct ab8500 *ab)
	397	{
	398	return ab->version == AB8500_VERSION_AB8500;
	399	}
	400
	401	static inline int is_ab8505(struct ab8500 *ab)
	402	{
	403	return ab->version == AB8500_VERSION_AB8505;
	404	}
	405
	406	static inline int is_ab9540(struct ab8500 *ab)
	407	{
	408	return ab->version == AB8500_VERSION_AB9540;
	409	}
	410
	411	static inline int is_ab8540(struct ab8500 *ab)
	412	{
	413	return ab->version == AB8500_VERSION_AB8540;
	414	}
	415
a982362c BJ	416	/* exclude also ab8505, ab9540... */
	417	static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
	418	{
	419	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
	420	}
	421
	422	/* exclude also ab8505, ab9540... */
0f620837 LW	423	static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
	424	{
	425	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
	426	}
	427
a982362c	428	/* exclude also ab8505, ab9540... */
0f620837 LW	429	static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
	430	{
	431	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
	432	}
	433
56813f79 LW	434	static inline int is_ab8500_3p3_or_earlier(struct ab8500 *ab)
	435	{
	436	return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT3P3));
	437	}
	438
a982362c BJ	439	/* exclude also ab8505, ab9540... */
	440	static inline int is_ab8500_2p0(struct ab8500 *ab)
	441	{
	442	return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
	443	}
	444
56813f79 LW	445	static inline int is_ab8505_1p0_or_earlier(struct ab8500 *ab)
	446	{
	447	return (is_ab8505(ab) && (ab->chip_id <= AB8500_CUT1P0));
	448	}
	449
	450	static inline int is_ab8505_2p0(struct ab8500 *ab)
	451	{
	452	return (is_ab8505(ab) && (ab->chip_id == AB8500_CUT2P0));
	453	}
	454
	455	static inline int is_ab9540_1p0_or_earlier(struct ab8500 *ab)
	456	{
	457	return (is_ab9540(ab) && (ab->chip_id <= AB8500_CUT1P0));
	458	}
	459
	460	static inline int is_ab9540_2p0(struct ab8500 *ab)
	461	{
	462	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT2P0));
	463	}
	464
	465	/*
	466	* Be careful, the marketing name for this chip is 2.1
	467	* but the value read from the chip is 3.0 (0x30)
	468	*/
	469	static inline int is_ab9540_3p0(struct ab8500 *ab)
	470	{
	471	return (is_ab9540(ab) && (ab->chip_id == AB8500_CUT3P0));
	472	}
	473
	474	static inline int is_ab8540_1p0_or_earlier(struct ab8500 *ab)
	475	{
	476	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P0);
	477	}
	478
	479	static inline int is_ab8540_1p1_or_earlier(struct ab8500 *ab)
	480	{
	481	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P1);
	482	}
	483
	484	static inline int is_ab8540_1p2_or_earlier(struct ab8500 *ab)
	485	{
	486	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT1P2);
	487	}
	488
	489	static inline int is_ab8540_2p0_or_earlier(struct ab8500 *ab)
	490	{
	491	return is_ab8540(ab) && (ab->chip_id <= AB8500_CUT2P0);
	492	}
	493
	494	static inline int is_ab8540_2p0(struct ab8500 *ab)
	495	{
	496	return is_ab8540(ab) && (ab->chip_id == AB8500_CUT2P0);
	497	}
	498
	499	static inline int is_ab8505_2p0_earlier(struct ab8500 *ab)
	500	{
	501	return (is_ab8505(ab) && (ab->chip_id < AB8500_CUT2P0));
	502	}
	503
	504	static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
	505	{
	506	return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
	507	}
	508
f04a9d8a RK	509	void ab8500_override_turn_on_stat(u8 mask, u8 set);
f04a9d8a RK	510
1d843a6c MYK	511	#ifdef CONFIG_AB8500_DEBUG
1d843a6c MYK	512	void ab8500_dump_all_banks(struct device *dev);
8f0eb43b	513	void ab8500_debug_register_interrupt(int line);
1d843a6c MYK	514	#else
1d843a6c MYK	515	static inline void ab8500_dump_all_banks(struct device *dev) {}
8f0eb43b	516	static inline void ab8500_debug_register_interrupt(int line) {}
1d843a6c MYK	517	#endif
1d843a6c MYK	518
62579266	519	#endif /* MFD_AB8500_H */