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70c6cce0 QZ |
1 | /* |
2 | * Marvell 88PM80x Interface | |
3 | * | |
4 | * Copyright (C) 2012 Marvell International Ltd. | |
5 | * Qiao Zhou <zhouqiao@marvell.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __LINUX_MFD_88PM80X_H | |
13 | #define __LINUX_MFD_88PM80X_H | |
14 | ||
15 | #include <linux/platform_device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/regmap.h> | |
18 | #include <linux/atomic.h> | |
19 | ||
70c6cce0 QZ |
20 | enum { |
21 | CHIP_INVALID = 0, | |
22 | CHIP_PM800, | |
23 | CHIP_PM805, | |
62a2e633 | 24 | CHIP_PM860, |
70c6cce0 QZ |
25 | CHIP_MAX, |
26 | }; | |
27 | ||
28 | enum { | |
29 | PM800_ID_BUCK1 = 0, | |
30 | PM800_ID_BUCK2, | |
31 | PM800_ID_BUCK3, | |
32 | PM800_ID_BUCK4, | |
33 | PM800_ID_BUCK5, | |
34 | ||
35 | PM800_ID_LDO1, | |
36 | PM800_ID_LDO2, | |
37 | PM800_ID_LDO3, | |
38 | PM800_ID_LDO4, | |
39 | PM800_ID_LDO5, | |
40 | PM800_ID_LDO6, | |
41 | PM800_ID_LDO7, | |
42 | PM800_ID_LDO8, | |
43 | PM800_ID_LDO9, | |
44 | PM800_ID_LDO10, | |
45 | PM800_ID_LDO11, | |
46 | PM800_ID_LDO12, | |
47 | PM800_ID_LDO13, | |
48 | PM800_ID_LDO14, | |
49 | PM800_ID_LDO15, | |
50 | PM800_ID_LDO16, | |
51 | PM800_ID_LDO17, | |
52 | PM800_ID_LDO18, | |
53 | PM800_ID_LDO19, | |
54 | ||
55 | PM800_ID_RG_MAX, | |
56 | }; | |
57 | #define PM800_MAX_REGULATOR PM800_ID_RG_MAX /* 5 Bucks, 19 LDOs */ | |
58 | #define PM800_NUM_BUCK (5) /*5 Bucks */ | |
59 | #define PM800_NUM_LDO (19) /*19 Bucks */ | |
60 | ||
61 | /* page 0 basic: slave adder 0x60 */ | |
62 | ||
63 | #define PM800_STATUS_1 (0x01) | |
bc00d68f VH |
64 | #define PM800_ONKEY_STS1 BIT(0) |
65 | #define PM800_EXTON_STS1 BIT(1) | |
66 | #define PM800_CHG_STS1 BIT(2) | |
67 | #define PM800_BAT_STS1 BIT(3) | |
68 | #define PM800_VBUS_STS1 BIT(4) | |
69 | #define PM800_LDO_PGOOD_STS1 BIT(5) | |
70 | #define PM800_BUCK_PGOOD_STS1 BIT(6) | |
70c6cce0 QZ |
71 | |
72 | #define PM800_STATUS_2 (0x02) | |
bc00d68f | 73 | #define PM800_RTC_ALARM_STS2 BIT(0) |
70c6cce0 QZ |
74 | |
75 | /* Wakeup Registers */ | |
bc00d68f | 76 | #define PM800_WAKEUP1 (0x0D) |
70c6cce0 | 77 | |
bc00d68f VH |
78 | #define PM800_WAKEUP2 (0x0E) |
79 | #define PM800_WAKEUP2_INV_INT BIT(0) | |
80 | #define PM800_WAKEUP2_INT_CLEAR BIT(1) | |
81 | #define PM800_WAKEUP2_INT_MASK BIT(2) | |
70c6cce0 | 82 | |
bc00d68f | 83 | #define PM800_POWER_UP_LOG (0x10) |
70c6cce0 QZ |
84 | |
85 | /* Referance and low power registers */ | |
86 | #define PM800_LOW_POWER1 (0x20) | |
87 | #define PM800_LOW_POWER2 (0x21) | |
bc00d68f VH |
88 | #define PM800_LOW_POWER_CONFIG3 (0x22) |
89 | #define PM800_LOW_POWER_CONFIG4 (0x23) | |
70c6cce0 QZ |
90 | |
91 | /* GPIO register */ | |
92 | #define PM800_GPIO_0_1_CNTRL (0x30) | |
bc00d68f | 93 | #define PM800_GPIO0_VAL BIT(0) |
70c6cce0 | 94 | #define PM800_GPIO0_GPIO_MODE(x) (x << 1) |
bc00d68f | 95 | #define PM800_GPIO1_VAL BIT(4) |
70c6cce0 QZ |
96 | #define PM800_GPIO1_GPIO_MODE(x) (x << 5) |
97 | ||
98 | #define PM800_GPIO_2_3_CNTRL (0x31) | |
bc00d68f | 99 | #define PM800_GPIO2_VAL BIT(0) |
70c6cce0 | 100 | #define PM800_GPIO2_GPIO_MODE(x) (x << 1) |
bc00d68f | 101 | #define PM800_GPIO3_VAL BIT(4) |
70c6cce0 QZ |
102 | #define PM800_GPIO3_GPIO_MODE(x) (x << 5) |
103 | #define PM800_GPIO3_MODE_MASK 0x1F | |
104 | #define PM800_GPIO3_HEADSET_MODE PM800_GPIO3_GPIO_MODE(6) | |
105 | ||
bc00d68f VH |
106 | #define PM800_GPIO_4_CNTRL (0x32) |
107 | #define PM800_GPIO4_VAL BIT(0) | |
70c6cce0 QZ |
108 | #define PM800_GPIO4_GPIO_MODE(x) (x << 1) |
109 | ||
110 | #define PM800_HEADSET_CNTRL (0x38) | |
bc00d68f VH |
111 | #define PM800_HEADSET_DET_EN BIT(7) |
112 | #define PM800_HSDET_SLP BIT(1) | |
70c6cce0 | 113 | /* PWM register */ |
bc00d68f VH |
114 | #define PM800_PWM1 (0x40) |
115 | #define PM800_PWM2 (0x41) | |
116 | #define PM800_PWM3 (0x42) | |
117 | #define PM800_PWM4 (0x43) | |
70c6cce0 QZ |
118 | |
119 | /* RTC Registers */ | |
120 | #define PM800_RTC_CONTROL (0xD0) | |
121 | #define PM800_RTC_MISC1 (0xE1) | |
122 | #define PM800_RTC_MISC2 (0xE2) | |
123 | #define PM800_RTC_MISC3 (0xE3) | |
124 | #define PM800_RTC_MISC4 (0xE4) | |
125 | #define PM800_RTC_MISC5 (0xE7) | |
126 | /* bit definitions of RTC Register 1 (0xD0) */ | |
bc00d68f VH |
127 | #define PM800_ALARM1_EN BIT(0) |
128 | #define PM800_ALARM_WAKEUP BIT(4) | |
129 | #define PM800_ALARM BIT(5) | |
130 | #define PM800_RTC1_USE_XO BIT(7) | |
70c6cce0 QZ |
131 | |
132 | /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */ | |
133 | ||
134 | /* buck registers */ | |
bc00d68f | 135 | #define PM800_SLEEP_BUCK1 (0x30) |
70c6cce0 QZ |
136 | |
137 | /* BUCK Sleep Mode Register 1: BUCK[1..4] */ | |
bc00d68f VH |
138 | #define PM800_BUCK_SLP1 (0x5A) |
139 | #define PM800_BUCK1_SLP1_SHIFT 0 | |
140 | #define PM800_BUCK1_SLP1_MASK (0x3 << PM800_BUCK1_SLP1_SHIFT) | |
70c6cce0 QZ |
141 | |
142 | /* page 2 GPADC: slave adder 0x02 */ | |
143 | #define PM800_GPADC_MEAS_EN1 (0x01) | |
bc00d68f | 144 | #define PM800_MEAS_EN1_VBAT BIT(2) |
70c6cce0 | 145 | #define PM800_GPADC_MEAS_EN2 (0x02) |
bc00d68f VH |
146 | #define PM800_MEAS_EN2_RFTMP BIT(0) |
147 | #define PM800_MEAS_GP0_EN BIT(2) | |
148 | #define PM800_MEAS_GP1_EN BIT(3) | |
149 | #define PM800_MEAS_GP2_EN BIT(4) | |
150 | #define PM800_MEAS_GP3_EN BIT(5) | |
151 | #define PM800_MEAS_GP4_EN BIT(6) | |
70c6cce0 QZ |
152 | |
153 | #define PM800_GPADC_MISC_CONFIG1 (0x05) | |
154 | #define PM800_GPADC_MISC_CONFIG2 (0x06) | |
bc00d68f | 155 | #define PM800_GPADC_MISC_GPFSM_EN BIT(0) |
70c6cce0 QZ |
156 | #define PM800_GPADC_SLOW_MODE(x) (x << 3) |
157 | ||
bc00d68f VH |
158 | #define PM800_GPADC_MISC_CONFIG3 (0x09) |
159 | #define PM800_GPADC_MISC_CONFIG4 (0x0A) | |
70c6cce0 | 160 | |
bc00d68f | 161 | #define PM800_GPADC_PREBIAS1 (0x0F) |
70c6cce0 | 162 | #define PM800_GPADC0_GP_PREBIAS_TIME(x) (x << 0) |
bc00d68f | 163 | #define PM800_GPADC_PREBIAS2 (0x10) |
70c6cce0 | 164 | |
bc00d68f VH |
165 | #define PM800_GP_BIAS_ENA1 (0x14) |
166 | #define PM800_GPADC_GP_BIAS_EN0 BIT(0) | |
167 | #define PM800_GPADC_GP_BIAS_EN1 BIT(1) | |
168 | #define PM800_GPADC_GP_BIAS_EN2 BIT(2) | |
169 | #define PM800_GPADC_GP_BIAS_EN3 BIT(3) | |
70c6cce0 QZ |
170 | |
171 | #define PM800_GP_BIAS_OUT1 (0x15) | |
bc00d68f VH |
172 | #define PM800_BIAS_OUT_GP0 BIT(0) |
173 | #define PM800_BIAS_OUT_GP1 BIT(1) | |
174 | #define PM800_BIAS_OUT_GP2 BIT(2) | |
175 | #define PM800_BIAS_OUT_GP3 BIT(3) | |
70c6cce0 QZ |
176 | |
177 | #define PM800_GPADC0_LOW_TH 0x20 | |
178 | #define PM800_GPADC1_LOW_TH 0x21 | |
179 | #define PM800_GPADC2_LOW_TH 0x22 | |
180 | #define PM800_GPADC3_LOW_TH 0x23 | |
181 | #define PM800_GPADC4_LOW_TH 0x24 | |
182 | ||
183 | #define PM800_GPADC0_UPP_TH 0x30 | |
184 | #define PM800_GPADC1_UPP_TH 0x31 | |
185 | #define PM800_GPADC2_UPP_TH 0x32 | |
186 | #define PM800_GPADC3_UPP_TH 0x33 | |
187 | #define PM800_GPADC4_UPP_TH 0x34 | |
188 | ||
189 | #define PM800_VBBAT_MEAS1 0x40 | |
190 | #define PM800_VBBAT_MEAS2 0x41 | |
191 | #define PM800_VBAT_MEAS1 0x42 | |
192 | #define PM800_VBAT_MEAS2 0x43 | |
193 | #define PM800_VSYS_MEAS1 0x44 | |
194 | #define PM800_VSYS_MEAS2 0x45 | |
195 | #define PM800_VCHG_MEAS1 0x46 | |
196 | #define PM800_VCHG_MEAS2 0x47 | |
197 | #define PM800_TINT_MEAS1 0x50 | |
198 | #define PM800_TINT_MEAS2 0x51 | |
199 | #define PM800_PMOD_MEAS1 0x52 | |
200 | #define PM800_PMOD_MEAS2 0x53 | |
201 | ||
202 | #define PM800_GPADC0_MEAS1 0x54 | |
203 | #define PM800_GPADC0_MEAS2 0x55 | |
204 | #define PM800_GPADC1_MEAS1 0x56 | |
205 | #define PM800_GPADC1_MEAS2 0x57 | |
206 | #define PM800_GPADC2_MEAS1 0x58 | |
207 | #define PM800_GPADC2_MEAS2 0x59 | |
208 | #define PM800_GPADC3_MEAS1 0x5A | |
209 | #define PM800_GPADC3_MEAS2 0x5B | |
210 | #define PM800_GPADC4_MEAS1 0x5C | |
211 | #define PM800_GPADC4_MEAS2 0x5D | |
212 | ||
213 | #define PM800_GPADC4_AVG1 0xA8 | |
214 | #define PM800_GPADC4_AVG2 0xA9 | |
215 | ||
216 | /* 88PM805 Registers */ | |
217 | #define PM805_MAIN_POWERUP (0x01) | |
218 | #define PM805_INT_STATUS0 (0x02) /* for ena/dis all interrupts */ | |
219 | ||
220 | #define PM805_STATUS0_INT_CLEAR (1 << 0) | |
221 | #define PM805_STATUS0_INV_INT (1 << 1) | |
222 | #define PM800_STATUS0_INT_MASK (1 << 2) | |
223 | ||
224 | #define PM805_INT_STATUS1 (0x03) | |
225 | ||
bc00d68f VH |
226 | #define PM805_INT1_HP1_SHRT BIT(0) |
227 | #define PM805_INT1_HP2_SHRT BIT(1) | |
228 | #define PM805_INT1_MIC_CONFLICT BIT(2) | |
229 | #define PM805_INT1_CLIP_FAULT BIT(3) | |
230 | #define PM805_INT1_LDO_OFF BIT(4) | |
231 | #define PM805_INT1_SRC_DPLL_LOCK BIT(5) | |
70c6cce0 QZ |
232 | |
233 | #define PM805_INT_STATUS2 (0x04) | |
234 | ||
bc00d68f VH |
235 | #define PM805_INT2_MIC_DET BIT(0) |
236 | #define PM805_INT2_SHRT_BTN_DET BIT(1) | |
237 | #define PM805_INT2_VOLM_BTN_DET BIT(2) | |
238 | #define PM805_INT2_VOLP_BTN_DET BIT(3) | |
239 | #define PM805_INT2_RAW_PLL_FAULT BIT(4) | |
240 | #define PM805_INT2_FINE_PLL_FAULT BIT(5) | |
70c6cce0 QZ |
241 | |
242 | #define PM805_INT_MASK1 (0x05) | |
243 | #define PM805_INT_MASK2 (0x06) | |
bc00d68f | 244 | #define PM805_SHRT_BTN_DET BIT(1) |
70c6cce0 QZ |
245 | |
246 | /* number of status and int reg in a row */ | |
247 | #define PM805_INT_REG_NUM (2) | |
248 | ||
249 | #define PM805_MIC_DET1 (0x07) | |
bc00d68f | 250 | #define PM805_MIC_DET_EN_MIC_DET BIT(0) |
70c6cce0 | 251 | #define PM805_MIC_DET2 (0x08) |
bc00d68f | 252 | #define PM805_MIC_DET_STATUS1 (0x09) |
70c6cce0 | 253 | |
bc00d68f VH |
254 | #define PM805_MIC_DET_STATUS3 (0x0A) |
255 | #define PM805_AUTO_SEQ_STATUS1 (0x0B) | |
256 | #define PM805_AUTO_SEQ_STATUS2 (0x0C) | |
70c6cce0 QZ |
257 | |
258 | #define PM805_ADC_SETTING1 (0x10) | |
259 | #define PM805_ADC_SETTING2 (0x11) | |
260 | #define PM805_ADC_SETTING3 (0x11) | |
261 | #define PM805_ADC_GAIN1 (0x12) | |
262 | #define PM805_ADC_GAIN2 (0x13) | |
263 | #define PM805_DMIC_SETTING (0x15) | |
264 | #define PM805_DWS_SETTING (0x16) | |
bc00d68f | 265 | #define PM805_MIC_CONFLICT_STS (0x17) |
70c6cce0 QZ |
266 | |
267 | #define PM805_PDM_SETTING1 (0x20) | |
268 | #define PM805_PDM_SETTING2 (0x21) | |
269 | #define PM805_PDM_SETTING3 (0x22) | |
270 | #define PM805_PDM_CONTROL1 (0x23) | |
271 | #define PM805_PDM_CONTROL2 (0x24) | |
272 | #define PM805_PDM_CONTROL3 (0x25) | |
273 | ||
bc00d68f VH |
274 | #define PM805_HEADPHONE_SETTING (0x26) |
275 | #define PM805_HEADPHONE_GAIN_A2A (0x27) | |
276 | #define PM805_HEADPHONE_SHORT_STATE (0x28) | |
277 | #define PM805_EARPHONE_SETTING (0x29) | |
278 | #define PM805_AUTO_SEQ_SETTING (0x2A) | |
70c6cce0 QZ |
279 | |
280 | struct pm80x_rtc_pdata { | |
281 | int vrtc; | |
282 | int rtc_wakeup; | |
283 | }; | |
284 | ||
285 | struct pm80x_subchip { | |
286 | struct i2c_client *power_page; /* chip client for power page */ | |
287 | struct i2c_client *gpadc_page; /* chip client for gpadc page */ | |
288 | struct regmap *regmap_power; | |
289 | struct regmap *regmap_gpadc; | |
290 | unsigned short power_page_addr; /* power page I2C address */ | |
291 | unsigned short gpadc_page_addr; /* gpadc page I2C address */ | |
292 | }; | |
293 | ||
294 | struct pm80x_chip { | |
295 | struct pm80x_subchip *subchip; | |
296 | struct device *dev; | |
297 | struct i2c_client *client; | |
5500e396 | 298 | struct i2c_client *companion; |
70c6cce0 QZ |
299 | struct regmap *regmap; |
300 | struct regmap_irq_chip *regmap_irq_chip; | |
301 | struct regmap_irq_chip_data *irq_data; | |
03dcc544 | 302 | int type; |
70c6cce0 QZ |
303 | int irq; |
304 | int irq_mode; | |
305 | unsigned long wu_flag; | |
306 | spinlock_t lock; | |
307 | }; | |
308 | ||
309 | struct pm80x_platform_data { | |
310 | struct pm80x_rtc_pdata *rtc; | |
2d3aa056 CX |
311 | /* |
312 | * For the regulator not defined, set regulators[not_defined] to be | |
313 | * NULL. num_regulators are the number of regulators supposed to be | |
314 | * initialized. If all regulators are not defined, set num_regulators | |
315 | * to be 0. | |
316 | */ | |
317 | struct regulator_init_data *regulators[PM800_ID_RG_MAX]; | |
318 | unsigned int num_regulators; | |
70c6cce0 QZ |
319 | int irq_mode; /* Clear interrupt by read/write(0/1) */ |
320 | int batt_det; /* enable/disable */ | |
321 | int (*plat_config)(struct pm80x_chip *chip, | |
322 | struct pm80x_platform_data *pdata); | |
323 | }; | |
324 | ||
325 | extern const struct dev_pm_ops pm80x_pm_ops; | |
326 | extern const struct regmap_config pm80x_regmap_config; | |
327 | ||
328 | static inline int pm80x_request_irq(struct pm80x_chip *pm80x, int irq, | |
329 | irq_handler_t handler, unsigned long flags, | |
330 | const char *name, void *data) | |
331 | { | |
332 | if (!pm80x->irq_data) | |
333 | return -EINVAL; | |
334 | return request_threaded_irq(regmap_irq_get_virq(pm80x->irq_data, irq), | |
335 | NULL, handler, flags, name, data); | |
336 | } | |
337 | ||
338 | static inline void pm80x_free_irq(struct pm80x_chip *pm80x, int irq, void *data) | |
339 | { | |
340 | if (!pm80x->irq_data) | |
341 | return; | |
342 | free_irq(regmap_irq_get_virq(pm80x->irq_data, irq), data); | |
343 | } | |
344 | ||
345 | #ifdef CONFIG_PM | |
346 | static inline int pm80x_dev_suspend(struct device *dev) | |
347 | { | |
348 | struct platform_device *pdev = to_platform_device(dev); | |
349 | struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent); | |
350 | int irq = platform_get_irq(pdev, 0); | |
351 | ||
352 | if (device_may_wakeup(dev)) | |
353 | set_bit((1 << irq), &chip->wu_flag); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static inline int pm80x_dev_resume(struct device *dev) | |
359 | { | |
360 | struct platform_device *pdev = to_platform_device(dev); | |
361 | struct pm80x_chip *chip = dev_get_drvdata(pdev->dev.parent); | |
362 | int irq = platform_get_irq(pdev, 0); | |
363 | ||
364 | if (device_may_wakeup(dev)) | |
365 | clear_bit((1 << irq), &chip->wu_flag); | |
366 | ||
367 | return 0; | |
368 | } | |
369 | #endif | |
370 | ||
03dcc544 | 371 | extern int pm80x_init(struct i2c_client *client); |
306df798 | 372 | extern int pm80x_deinit(void); |
70c6cce0 | 373 | #endif /* __LINUX_MFD_88PM80X_H */ |