[linux-2.6-block.git] / include / linux / lightnvm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef NVM_H
#define NVM_H

#include <linux/blkdev.h>
#include <linux/types.h>
#include <uapi/linux/lightnvm.h>

enum {
	NVM_IO_OK = 0,
	NVM_IO_REQUEUE = 1,
	NVM_IO_DONE = 2,
	NVM_IO_ERR = 3,

	NVM_IOTYPE_NONE = 0,
	NVM_IOTYPE_GC = 1,
};

#define NVM_BLK_BITS (16)
#define NVM_PG_BITS  (16)
#define NVM_SEC_BITS (8)
#define NVM_PL_BITS  (8)
#define NVM_LUN_BITS (8)
#define NVM_CH_BITS  (7)

struct ppa_addr {
	/* Generic structure for all addresses */
	union {
		struct {
			u64 blk		: NVM_BLK_BITS;
			u64 pg		: NVM_PG_BITS;
			u64 sec		: NVM_SEC_BITS;
			u64 pl		: NVM_PL_BITS;
			u64 lun		: NVM_LUN_BITS;
			u64 ch		: NVM_CH_BITS;
			u64 reserved	: 1;
		} g;

		struct {
			u64 line	: 63;
			u64 is_cached	: 1;
		} c;

		u64 ppa;
	};
};

struct nvm_rq;
struct nvm_id;
struct nvm_dev;
struct nvm_tgt_dev;

typedef int (nvm_id_fn)(struct nvm_dev *, struct nvm_id *);
typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *);
typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *);
typedef void (nvm_destroy_dma_pool_fn)(void *);
typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
								dma_addr_t *);
typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);

struct nvm_dev_ops {
	nvm_id_fn		*identity;
	nvm_op_bb_tbl_fn	*get_bb_tbl;
	nvm_op_set_bb_fn	*set_bb_tbl;

	nvm_submit_io_fn	*submit_io;
	nvm_submit_io_sync_fn	*submit_io_sync;

	nvm_create_dma_pool_fn	*create_dma_pool;
	nvm_destroy_dma_pool_fn	*destroy_dma_pool;
	nvm_dev_dma_alloc_fn	*dev_dma_alloc;
	nvm_dev_dma_free_fn	*dev_dma_free;

	unsigned int		max_phys_sect;
};

#ifdef CONFIG_NVM

#include <linux/blkdev.h>
#include <linux/file.h>
#include <linux/dmapool.h>
#include <uapi/linux/lightnvm.h>

enum {
	/* HW Responsibilities */
	NVM_RSP_L2P	= 1 << 0,
	NVM_RSP_ECC	= 1 << 1,

	/* Physical Adressing Mode */
	NVM_ADDRMODE_LINEAR	= 0,
	NVM_ADDRMODE_CHANNEL	= 1,

	/* Plane programming mode for LUN */
	NVM_PLANE_SINGLE	= 1,
	NVM_PLANE_DOUBLE	= 2,
	NVM_PLANE_QUAD		= 4,

	/* Status codes */
	NVM_RSP_SUCCESS		= 0x0,
	NVM_RSP_NOT_CHANGEABLE	= 0x1,
	NVM_RSP_ERR_FAILWRITE	= 0x40ff,
	NVM_RSP_ERR_EMPTYPAGE	= 0x42ff,
	NVM_RSP_ERR_FAILECC	= 0x4281,
	NVM_RSP_ERR_FAILCRC	= 0x4004,
	NVM_RSP_WARN_HIGHECC	= 0x4700,

	/* Device opcodes */
	NVM_OP_PWRITE		= 0x91,
	NVM_OP_PREAD		= 0x92,
	NVM_OP_ERASE		= 0x90,

	/* PPA Command Flags */
	NVM_IO_SNGL_ACCESS	= 0x0,
	NVM_IO_DUAL_ACCESS	= 0x1,
	NVM_IO_QUAD_ACCESS	= 0x2,

	/* NAND Access Modes */
	NVM_IO_SUSPEND		= 0x80,
	NVM_IO_SLC_MODE		= 0x100,
	NVM_IO_SCRAMBLE_ENABLE	= 0x200,

	/* Block Types */
	NVM_BLK_T_FREE		= 0x0,
	NVM_BLK_T_BAD		= 0x1,
	NVM_BLK_T_GRWN_BAD	= 0x2,
	NVM_BLK_T_DEV		= 0x4,
	NVM_BLK_T_HOST		= 0x8,

	/* Memory capabilities */
	NVM_ID_CAP_SLC		= 0x1,
	NVM_ID_CAP_CMD_SUSPEND	= 0x2,
	NVM_ID_CAP_SCRAMBLE	= 0x4,
	NVM_ID_CAP_ENCRYPT	= 0x8,

	/* Memory types */
	NVM_ID_FMTYPE_SLC	= 0,
	NVM_ID_FMTYPE_MLC	= 1,

	/* Device capabilities */
	NVM_ID_DCAP_BBLKMGMT	= 0x1,
	NVM_UD_DCAP_ECC		= 0x2,
};

struct nvm_id_lp_mlc {
	u16	num_pairs;
	u8	pairs[886];
};

struct nvm_id_lp_tbl {
	__u8	id[8];
	struct nvm_id_lp_mlc mlc;
};

struct nvm_id_group {
	u8	mtype;
	u8	fmtype;
	u8	num_ch;
	u8	num_lun;
	u16	num_chk;
	u16	clba;
	u16	csecs;
	u16	sos;

	u16	ws_min;
	u16	ws_opt;
	u16	ws_seq;
	u16	ws_per_chk;

	u32	trdt;
	u32	trdm;
	u32	tprt;
	u32	tprm;
	u32	tbet;
	u32	tbem;
	u32	mpos;
	u32	mccap;
	u16	cpar;

	/* 1.2 compatibility */
	u8	num_pln;
	u16	num_pg;
	u16	fpg_sz;
};

struct nvm_addr_format {
	u8	ch_offset;
	u8	ch_len;
	u8	lun_offset;
	u8	lun_len;
	u8	pln_offset;
	u8	pln_len;
	u8	blk_offset;
	u8	blk_len;
	u8	pg_offset;
	u8	pg_len;
	u8	sect_offset;
	u8	sect_len;
};

struct nvm_id {
	u8	ver_id;
	u8	vmnt;
	u32	cap;
	u32	dom;
	struct nvm_addr_format ppaf;
	struct nvm_id_group grp;
} __packed;

struct nvm_target {
	struct list_head list;
	struct nvm_tgt_dev *dev;
	struct nvm_tgt_type *type;
	struct gendisk *disk;
};

#define ADDR_EMPTY (~0ULL)

#define NVM_TARGET_DEFAULT_OP (101)
#define NVM_TARGET_MIN_OP (3)
#define NVM_TARGET_MAX_OP (80)

#define NVM_VERSION_MAJOR 1
#define NVM_VERSION_MINOR 0
#define NVM_VERSION_PATCH 0

struct nvm_rq;
typedef void (nvm_end_io_fn)(struct nvm_rq *);

struct nvm_rq {
	struct nvm_tgt_dev *dev;

	struct bio *bio;

	union {
		struct ppa_addr ppa_addr;
		dma_addr_t dma_ppa_list;
	};

	struct ppa_addr *ppa_list;

	void *meta_list;
	dma_addr_t dma_meta_list;

	nvm_end_io_fn *end_io;

	uint8_t opcode;
	uint16_t nr_ppas;
	uint16_t flags;

	u64 ppa_status; /* ppa media status */
	int error;

	void *private;
};

static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
{
	return pdu - sizeof(struct nvm_rq);
}

static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
{
	return rqdata + 1;
}

enum {
	NVM_BLK_ST_FREE =	0x1,	/* Free block */
	NVM_BLK_ST_TGT =	0x2,	/* Block in use by target */
	NVM_BLK_ST_BAD =	0x8,	/* Bad block */
};


/* Device generic information */
struct nvm_geo {
	/* generic geometry */
	int nr_chnls;
	int all_luns; /* across channels */
	int nr_luns; /* per channel */
	int nr_chks; /* per lun */

	int sec_size;
	int oob_size;
	int mccap;

	int sec_per_chk;
	int sec_per_lun;

	int ws_min;
	int ws_opt;
	int ws_seq;
	int ws_per_chk;

	int max_rq_size;

	int op;

	struct nvm_addr_format ppaf;

	/* Legacy 1.2 specific geometry */
	int plane_mode; /* drive device in single, double or quad mode */
	int nr_planes;
	int sec_per_pg; /* only sectors for a single page */
	int sec_per_pl; /* all sectors across planes */
};

/* sub-device structure */
struct nvm_tgt_dev {
	/* Device information */
	struct nvm_geo geo;

	/* Base ppas for target LUNs */
	struct ppa_addr *luns;

	sector_t total_secs;

	struct nvm_id identity;
	struct request_queue *q;

	struct nvm_dev *parent;
	void *map;
};

struct nvm_dev {
	struct nvm_dev_ops *ops;

	struct list_head devices;

	/* Device information */
	struct nvm_geo geo;

	unsigned long total_secs;

	unsigned long *lun_map;
	void *dma_pool;

	struct nvm_id identity;

	/* Backend device */
	struct request_queue *q;
	char name[DISK_NAME_LEN];
	void *private_data;

	void *rmap;

	struct mutex mlock;
	spinlock_t lock;

	/* target management */
	struct list_head area_list;
	struct list_head targets;
};

static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &tgt_dev->geo;
	struct ppa_addr l;

	l.ppa = ((u64)r.g.blk) << geo->ppaf.blk_offset;
	l.ppa |= ((u64)r.g.pg) << geo->ppaf.pg_offset;
	l.ppa |= ((u64)r.g.sec) << geo->ppaf.sect_offset;
	l.ppa |= ((u64)r.g.pl) << geo->ppaf.pln_offset;
	l.ppa |= ((u64)r.g.lun) << geo->ppaf.lun_offset;
	l.ppa |= ((u64)r.g.ch) << geo->ppaf.ch_offset;

	return l;
}

static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &tgt_dev->geo;
	struct ppa_addr l;

	l.ppa = 0;
	/*
	 * (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc.
	 */
	l.g.blk = (r.ppa >> geo->ppaf.blk_offset) &
					(((1 << geo->ppaf.blk_len) - 1));
	l.g.pg |= (r.ppa >> geo->ppaf.pg_offset) &
					(((1 << geo->ppaf.pg_len) - 1));
	l.g.sec |= (r.ppa >> geo->ppaf.sect_offset) &
					(((1 << geo->ppaf.sect_len) - 1));
	l.g.pl |= (r.ppa >> geo->ppaf.pln_offset) &
					(((1 << geo->ppaf.pln_len) - 1));
	l.g.lun |= (r.ppa >> geo->ppaf.lun_offset) &
					(((1 << geo->ppaf.lun_len) - 1));
	l.g.ch |= (r.ppa >> geo->ppaf.ch_offset) &
					(((1 << geo->ppaf.ch_len) - 1));

	return l;
}

typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
typedef sector_t (nvm_tgt_capacity_fn)(void *);
typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
				int flags);
typedef void (nvm_tgt_exit_fn)(void *);
typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);

struct nvm_tgt_type {
	const char *name;
	unsigned int version[3];

	/* target entry points */
	nvm_tgt_make_rq_fn *make_rq;
	nvm_tgt_capacity_fn *capacity;

	/* module-specific init/teardown */
	nvm_tgt_init_fn *init;
	nvm_tgt_exit_fn *exit;

	/* sysfs */
	nvm_tgt_sysfs_init_fn *sysfs_init;
	nvm_tgt_sysfs_exit_fn *sysfs_exit;

	/* For internal use */
	struct list_head list;
	struct module *owner;
};

extern int nvm_register_tgt_type(struct nvm_tgt_type *);
extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);

extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);

extern struct nvm_dev *nvm_alloc_dev(int);
extern int nvm_register(struct nvm_dev *);
extern void nvm_unregister(struct nvm_dev *);

extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *,
			      int, int);
extern int nvm_max_phys_sects(struct nvm_tgt_dev *);
extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
extern void nvm_end_io(struct nvm_rq *);
extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int);
extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *);

#else /* CONFIG_NVM */
struct nvm_dev_ops;

static inline struct nvm_dev *nvm_alloc_dev(int node)
{
	return ERR_PTR(-EINVAL);
}
static inline int nvm_register(struct nvm_dev *dev)
{
	return -EINVAL;
}
static inline void nvm_unregister(struct nvm_dev *dev) {}
#endif /* CONFIG_NVM */
#endif /* LIGHTNVM.H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
cd9e9808 MB	2	#ifndef NVM_H
	3	#define NVM_H
	4
b76eb20b	5	#include <linux/blkdev.h>
a7fd9a4f	6	#include <linux/types.h>
b76eb20b	7	#include <uapi/linux/lightnvm.h>
a7fd9a4f	8
cd9e9808 MB	9	enum {
	10	NVM_IO_OK = 0,
	11	NVM_IO_REQUEUE = 1,
	12	NVM_IO_DONE = 2,
	13	NVM_IO_ERR = 3,
	14
	15	NVM_IOTYPE_NONE = 0,
	16	NVM_IOTYPE_GC = 1,
	17	};
	18
a7fd9a4f JA	19	#define NVM_BLK_BITS (16)
	20	#define NVM_PG_BITS (16)
	21	#define NVM_SEC_BITS (8)
	22	#define NVM_PL_BITS (8)
	23	#define NVM_LUN_BITS (8)
df414b33	24	#define NVM_CH_BITS (7)
a7fd9a4f JA	25
	26	struct ppa_addr {
	27	/* Generic structure for all addresses */
	28	union {
	29	struct {
	30	u64 blk : NVM_BLK_BITS;
	31	u64 pg : NVM_PG_BITS;
	32	u64 sec : NVM_SEC_BITS;
	33	u64 pl : NVM_PL_BITS;
	34	u64 lun : NVM_LUN_BITS;
	35	u64 ch : NVM_CH_BITS;
df414b33	36	u64 reserved : 1;
a7fd9a4f JA	37	} g;
a7fd9a4f JA	38
df414b33 MB	39	struct {
	40	u64 line : 63;
	41	u64 is_cached : 1;
	42	} c;
	43
a7fd9a4f JA	44	u64 ppa;
	45	};
	46	};
	47
	48	struct nvm_rq;
	49	struct nvm_id;
	50	struct nvm_dev;
8e53624d	51	struct nvm_tgt_dev;
a7fd9a4f	52
a7fd9a4f	53	typedef int (nvm_id_fn)(struct nvm_dev , struct nvm_id );
e11903f5	54	typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev , struct ppa_addr, u8 );
00ee6cc3	55	typedef int (nvm_op_set_bb_fn)(struct nvm_dev , struct ppa_addr , int, int);
a7fd9a4f	56	typedef int (nvm_submit_io_fn)(struct nvm_dev , struct nvm_rq );
1a94b2d4	57	typedef int (nvm_submit_io_sync_fn)(struct nvm_dev , struct nvm_rq );
a7fd9a4f JA	58	typedef void (nvm_create_dma_pool_fn)(struct nvm_dev , char *);
	59	typedef void (nvm_destroy_dma_pool_fn)(void *);
	60	typedef void (nvm_dev_dma_alloc_fn)(struct nvm_dev , void *, gfp_t,
	61	dma_addr_t *);
	62	typedef void (nvm_dev_dma_free_fn)(void , void, dma_addr_t);
	63
	64	struct nvm_dev_ops {
	65	nvm_id_fn *identity;
a7fd9a4f JA	66	nvm_op_bb_tbl_fn *get_bb_tbl;
	67	nvm_op_set_bb_fn *set_bb_tbl;
	68
	69	nvm_submit_io_fn *submit_io;
1a94b2d4	70	nvm_submit_io_sync_fn *submit_io_sync;
a7fd9a4f JA	71
	72	nvm_create_dma_pool_fn *create_dma_pool;
	73	nvm_destroy_dma_pool_fn *destroy_dma_pool;
	74	nvm_dev_dma_alloc_fn *dev_dma_alloc;
	75	nvm_dev_dma_free_fn *dev_dma_free;
	76
	77	unsigned int max_phys_sect;
	78	};
	79
cd9e9808 MB	80	#ifdef CONFIG_NVM
	81
	82	#include <linux/blkdev.h>
cd9e9808 MB	83	#include <linux/file.h>
cd9e9808 MB	84	#include <linux/dmapool.h>
e3eb3799	85	#include <uapi/linux/lightnvm.h>
cd9e9808 MB	86
	87	enum {
	88	/* HW Responsibilities */
	89	NVM_RSP_L2P = 1 << 0,
	90	NVM_RSP_ECC = 1 << 1,
	91
	92	/* Physical Adressing Mode */
	93	NVM_ADDRMODE_LINEAR = 0,
	94	NVM_ADDRMODE_CHANNEL = 1,
	95
	96	/* Plane programming mode for LUN */
d5bdec8d MB	97	NVM_PLANE_SINGLE = 1,
	98	NVM_PLANE_DOUBLE = 2,
	99	NVM_PLANE_QUAD = 4,
cd9e9808 MB	100
	101	/* Status codes */
	102	NVM_RSP_SUCCESS = 0x0,
	103	NVM_RSP_NOT_CHANGEABLE = 0x1,
	104	NVM_RSP_ERR_FAILWRITE = 0x40ff,
	105	NVM_RSP_ERR_EMPTYPAGE = 0x42ff,
402ab9a8	106	NVM_RSP_ERR_FAILECC = 0x4281,
38ea2f76	107	NVM_RSP_ERR_FAILCRC = 0x4004,
402ab9a8	108	NVM_RSP_WARN_HIGHECC = 0x4700,
cd9e9808 MB	109
cd9e9808 MB	110	/* Device opcodes */
cd9e9808 MB	111	NVM_OP_PWRITE = 0x91,
	112	NVM_OP_PREAD = 0x92,
	113	NVM_OP_ERASE = 0x90,
	114
	115	/* PPA Command Flags */
	116	NVM_IO_SNGL_ACCESS = 0x0,
	117	NVM_IO_DUAL_ACCESS = 0x1,
	118	NVM_IO_QUAD_ACCESS = 0x2,
	119
57b4bd06	120	/* NAND Access Modes */
cd9e9808 MB	121	NVM_IO_SUSPEND = 0x80,
cd9e9808 MB	122	NVM_IO_SLC_MODE = 0x100,
a7737f39	123	NVM_IO_SCRAMBLE_ENABLE = 0x200,
57b4bd06 MB	124
	125	/* Block Types */
	126	NVM_BLK_T_FREE = 0x0,
	127	NVM_BLK_T_BAD = 0x1,
b5d4acd4 MB	128	NVM_BLK_T_GRWN_BAD = 0x2,
	129	NVM_BLK_T_DEV = 0x4,
	130	NVM_BLK_T_HOST = 0x8,
f9a99950 MB	131
	132	/* Memory capabilities */
	133	NVM_ID_CAP_SLC = 0x1,
	134	NVM_ID_CAP_CMD_SUSPEND = 0x2,
	135	NVM_ID_CAP_SCRAMBLE = 0x4,
	136	NVM_ID_CAP_ENCRYPT = 0x8,
ca5927e7 MB	137
	138	/* Memory types */
	139	NVM_ID_FMTYPE_SLC = 0,
	140	NVM_ID_FMTYPE_MLC = 1,
bf643185 MB	141
	142	/* Device capabilities */
	143	NVM_ID_DCAP_BBLKMGMT = 0x1,
	144	NVM_UD_DCAP_ECC = 0x2,
ca5927e7 MB	145	};
	146
	147	struct nvm_id_lp_mlc {
	148	u16 num_pairs;
	149	u8 pairs[886];
	150	};
	151
	152	struct nvm_id_lp_tbl {
	153	__u8 id[8];
	154	struct nvm_id_lp_mlc mlc;
cd9e9808 MB	155	};
	156
	157	struct nvm_id_group {
	158	u8 mtype;
	159	u8 fmtype;
cd9e9808 MB	160	u8 num_ch;
cd9e9808 MB	161	u8 num_lun;
fae7fae4 MB	162	u16 num_chk;
fae7fae4 MB	163	u16 clba;
cd9e9808 MB	164	u16 csecs;
cd9e9808 MB	165	u16 sos;
fae7fae4 MB	166
	167	u16 ws_min;
	168	u16 ws_opt;
	169	u16 ws_seq;
	170	u16 ws_per_chk;
	171
cd9e9808 MB	172	u32 trdt;
	173	u32 trdm;
	174	u32 tprt;
	175	u32 tprm;
	176	u32 tbet;
	177	u32 tbem;
	178	u32 mpos;
12be5edf	179	u32 mccap;
cd9e9808	180	u16 cpar;
fae7fae4 MB	181
	182	/* 1.2 compatibility */
	183	u8 num_pln;
	184	u16 num_pg;
	185	u16 fpg_sz;
73387e7b	186	};
cd9e9808 MB	187
	188	struct nvm_addr_format {
	189	u8 ch_offset;
	190	u8 ch_len;
	191	u8 lun_offset;
	192	u8 lun_len;
	193	u8 pln_offset;
	194	u8 pln_len;
	195	u8 blk_offset;
	196	u8 blk_len;
	197	u8 pg_offset;
	198	u8 pg_len;
	199	u8 sect_offset;
	200	u8 sect_len;
cd9e9808 MB	201	};
	202
	203	struct nvm_id {
	204	u8 ver_id;
	205	u8 vmnt;
cd9e9808 MB	206	u32 cap;
	207	u32 dom;
	208	struct nvm_addr_format ppaf;
19bd6fe7	209	struct nvm_id_group grp;
cd9e9808 MB	210	} __packed;
	211
	212	struct nvm_target {
	213	struct list_head list;
8e79b5cb	214	struct nvm_tgt_dev *dev;
cd9e9808 MB	215	struct nvm_tgt_type *type;
	216	struct gendisk *disk;
	217	};
	218
cd9e9808 MB	219	#define ADDR_EMPTY (~0ULL)
cd9e9808 MB	220
e5392739 JG	221	#define NVM_TARGET_DEFAULT_OP (101)
	222	#define NVM_TARGET_MIN_OP (3)
	223	#define NVM_TARGET_MAX_OP (80)
	224
cd9e9808 MB	225	#define NVM_VERSION_MAJOR 1
	226	#define NVM_VERSION_MINOR 0
	227	#define NVM_VERSION_PATCH 0
	228
91276162	229	struct nvm_rq;
72d256ec	230	typedef void (nvm_end_io_fn)(struct nvm_rq *);
91276162	231
cd9e9808	232	struct nvm_rq {
8e53624d	233	struct nvm_tgt_dev *dev;
cd9e9808 MB	234
	235	struct bio *bio;
	236
	237	union {
	238	struct ppa_addr ppa_addr;
	239	dma_addr_t dma_ppa_list;
	240	};
	241
	242	struct ppa_addr *ppa_list;
	243
003fad37 JG	244	void *meta_list;
003fad37 JG	245	dma_addr_t dma_meta_list;
cd9e9808	246
91276162 MB	247	nvm_end_io_fn *end_io;
91276162 MB	248
cd9e9808	249	uint8_t opcode;
6d5be959	250	uint16_t nr_ppas;
cd9e9808	251	uint16_t flags;
72d256ec	252
9f867268	253	u64 ppa_status; /* ppa media status */
72d256ec	254	int error;
06894efe MB	255
06894efe MB	256	void *private;
cd9e9808 MB	257	};
	258
	259	static inline struct nvm_rq nvm_rq_from_pdu(void pdu)
	260	{
	261	return pdu - sizeof(struct nvm_rq);
	262	}
	263
	264	static inline void nvm_rq_to_pdu(struct nvm_rq rqdata)
	265	{
	266	return rqdata + 1;
	267	}
	268
ff0e498b JG	269	enum {
ff0e498b JG	270	NVM_BLK_ST_FREE = 0x1, /* Free block */
077d2389	271	NVM_BLK_ST_TGT = 0x2, /* Block in use by target */
ff0e498b	272	NVM_BLK_ST_BAD = 0x8, /* Bad block */
cd9e9808 MB	273	};
cd9e9808 MB	274
fae7fae4	275
8e79b5cb JG	276	/* Device generic information */
8e79b5cb JG	277	struct nvm_geo {
fae7fae4	278	/* generic geometry */
cd9e9808	279	int nr_chnls;
fae7fae4 MB	280	int all_luns; /* across channels */
	281	int nr_luns; /* per channel */
	282	int nr_chks; /* per lun */
	283
cd9e9808 MB	284	int sec_size;
cd9e9808 MB	285	int oob_size;
f9a99950	286	int mccap;
cd9e9808	287
fae7fae4 MB	288	int sec_per_chk;
	289	int sec_per_lun;
	290
	291	int ws_min;
	292	int ws_opt;
	293	int ws_seq;
	294	int ws_per_chk;
	295
cd9e9808	296	int max_rq_size;
cd9e9808	297
e5392739 JG	298	int op;
e5392739 JG	299
fae7fae4 MB	300	struct nvm_addr_format ppaf;
	301
	302	/* Legacy 1.2 specific geometry */
	303	int plane_mode; /* drive device in single, double or quad mode */
	304	int nr_planes;
	305	int sec_per_pg; /* only sectors for a single page */
cd9e9808	306	int sec_per_pl; /* all sectors across planes */
8e79b5cb JG	307	};
8e79b5cb JG	308
ade69e24	309	/* sub-device structure */
8e79b5cb JG	310	struct nvm_tgt_dev {
	311	/* Device information */
	312	struct nvm_geo geo;
	313
8e53624d JG	314	/* Base ppas for target LUNs */
	315	struct ppa_addr *luns;
	316
8e79b5cb JG	317	sector_t total_secs;
	318
	319	struct nvm_id identity;
	320	struct request_queue *q;
	321
959e911b	322	struct nvm_dev *parent;
8e53624d	323	void *map;
8e79b5cb JG	324	};
	325
	326	struct nvm_dev {
	327	struct nvm_dev_ops *ops;
	328
	329	struct list_head devices;
	330
8e79b5cb JG	331	/* Device information */
8e79b5cb JG	332	struct nvm_geo geo;
cd9e9808	333
4ece44af	334	unsigned long total_secs;
cd9e9808	335
da1e2849	336	unsigned long *lun_map;
75b85649	337	void *dma_pool;
cd9e9808 MB	338
	339	struct nvm_id identity;
	340
	341	/* Backend device */
	342	struct request_queue *q;
	343	char name[DISK_NAME_LEN];
40267efd	344	void *private_data;
e3eb3799	345
8e53624d JG	346	void *rmap;
8e53624d JG	347
e3eb3799	348	struct mutex mlock;
4c9dacb8	349	spinlock_t lock;
ade69e24 MB	350
	351	/* target management */
	352	struct list_head area_list;
	353	struct list_head targets;
cd9e9808 MB	354	};
cd9e9808 MB	355
dab8ee9e MB	356	static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev,
dab8ee9e MB	357	struct ppa_addr r)
cd9e9808	358	{
dab8ee9e	359	struct nvm_geo *geo = &tgt_dev->geo;
cd9e9808 MB	360	struct ppa_addr l;
cd9e9808 MB	361
8e79b5cb JG	362	l.ppa = ((u64)r.g.blk) << geo->ppaf.blk_offset;
	363	l.ppa \|= ((u64)r.g.pg) << geo->ppaf.pg_offset;
	364	l.ppa \|= ((u64)r.g.sec) << geo->ppaf.sect_offset;
	365	l.ppa \|= ((u64)r.g.pl) << geo->ppaf.pln_offset;
	366	l.ppa \|= ((u64)r.g.lun) << geo->ppaf.lun_offset;
	367	l.ppa \|= ((u64)r.g.ch) << geo->ppaf.ch_offset;
cd9e9808 MB	368
	369	return l;
	370	}
	371
dab8ee9e MB	372	static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev,
dab8ee9e MB	373	struct ppa_addr r)
cd9e9808	374	{
dab8ee9e	375	struct nvm_geo *geo = &tgt_dev->geo;
cd9e9808 MB	376	struct ppa_addr l;
cd9e9808 MB	377
5389a1df	378	l.ppa = 0;
7386af27 MB	379	/*
	380	* (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc.
	381	*/
8e79b5cb JG	382	l.g.blk = (r.ppa >> geo->ppaf.blk_offset) &
	383	(((1 << geo->ppaf.blk_len) - 1));
	384	l.g.pg \|= (r.ppa >> geo->ppaf.pg_offset) &
	385	(((1 << geo->ppaf.pg_len) - 1));
	386	l.g.sec \|= (r.ppa >> geo->ppaf.sect_offset) &
	387	(((1 << geo->ppaf.sect_len) - 1));
	388	l.g.pl \|= (r.ppa >> geo->ppaf.pln_offset) &
	389	(((1 << geo->ppaf.pln_len) - 1));
	390	l.g.lun \|= (r.ppa >> geo->ppaf.lun_offset) &
	391	(((1 << geo->ppaf.lun_len) - 1));
	392	l.g.ch \|= (r.ppa >> geo->ppaf.ch_offset) &
	393	(((1 << geo->ppaf.ch_len) - 1));
cd9e9808 MB	394
	395	return l;
	396	}
	397
dece1635	398	typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue , struct bio );
cd9e9808	399	typedef sector_t (nvm_tgt_capacity_fn)(void *);
4af3f75d JG	400	typedef void (nvm_tgt_init_fn)(struct nvm_tgt_dev , struct gendisk *,
4af3f75d JG	401	int flags);
cd9e9808	402	typedef void (nvm_tgt_exit_fn)(void *);
9a69b0ed JG	403	typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
9a69b0ed JG	404	typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
cd9e9808 MB	405
	406	struct nvm_tgt_type {
	407	const char *name;
	408	unsigned int version[3];
	409
	410	/* target entry points */
	411	nvm_tgt_make_rq_fn *make_rq;
	412	nvm_tgt_capacity_fn *capacity;
cd9e9808 MB	413
	414	/* module-specific init/teardown */
	415	nvm_tgt_init_fn *init;
	416	nvm_tgt_exit_fn *exit;
	417
9a69b0ed JG	418	/* sysfs */
	419	nvm_tgt_sysfs_init_fn *sysfs_init;
	420	nvm_tgt_sysfs_exit_fn *sysfs_exit;
	421
cd9e9808 MB	422	/* For internal use */
cd9e9808 MB	423	struct list_head list;
90014829	424	struct module *owner;
cd9e9808 MB	425	};
cd9e9808 MB	426
6063fe39 SL	427	extern int nvm_register_tgt_type(struct nvm_tgt_type *);
6063fe39 SL	428	extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
cd9e9808 MB	429
	430	extern void nvm_dev_dma_alloc(struct nvm_dev , gfp_t, dma_addr_t *);
	431	extern void nvm_dev_dma_free(struct nvm_dev , void , dma_addr_t);
	432
b0b4e09c MB	433	extern struct nvm_dev *nvm_alloc_dev(int);
	434	extern int nvm_register(struct nvm_dev *);
	435	extern void nvm_unregister(struct nvm_dev *);
cd9e9808	436
333ba053 JG	437	extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr ,
333ba053 JG	438	int, int);
a279006a	439	extern int nvm_max_phys_sects(struct nvm_tgt_dev *);
8e53624d	440	extern int nvm_submit_io(struct nvm_tgt_dev , struct nvm_rq );
1a94b2d4	441	extern int nvm_submit_io_sync(struct nvm_tgt_dev , struct nvm_rq );
06894efe	442	extern void nvm_end_io(struct nvm_rq *);
22e8c976	443	extern int nvm_bb_tbl_fold(struct nvm_dev , u8 , int);
333ba053	444	extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr, u8 );
e3eb3799	445
cd9e9808 MB	446	#else /* CONFIG_NVM */
	447	struct nvm_dev_ops;
	448
b0b4e09c MB	449	static inline struct nvm_dev *nvm_alloc_dev(int node)
	450	{
	451	return ERR_PTR(-EINVAL);
	452	}
	453	static inline int nvm_register(struct nvm_dev *dev)
cd9e9808 MB	454	{
	455	return -EINVAL;
	456	}
b0b4e09c	457	static inline void nvm_unregister(struct nvm_dev *dev) {}
cd9e9808 MB	458	#endif /* CONFIG_NVM */
cd9e9808 MB	459	#endif /* LIGHTNVM.H */