Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
cd9e9808 MB |
2 | #ifndef NVM_H |
3 | #define NVM_H | |
4 | ||
b76eb20b | 5 | #include <linux/blkdev.h> |
a7fd9a4f | 6 | #include <linux/types.h> |
b76eb20b | 7 | #include <uapi/linux/lightnvm.h> |
a7fd9a4f | 8 | |
cd9e9808 MB |
9 | enum { |
10 | NVM_IO_OK = 0, | |
11 | NVM_IO_REQUEUE = 1, | |
12 | NVM_IO_DONE = 2, | |
13 | NVM_IO_ERR = 3, | |
14 | ||
15 | NVM_IOTYPE_NONE = 0, | |
16 | NVM_IOTYPE_GC = 1, | |
17 | }; | |
18 | ||
a7fd9a4f JA |
19 | #define NVM_BLK_BITS (16) |
20 | #define NVM_PG_BITS (16) | |
21 | #define NVM_SEC_BITS (8) | |
22 | #define NVM_PL_BITS (8) | |
23 | #define NVM_LUN_BITS (8) | |
df414b33 | 24 | #define NVM_CH_BITS (7) |
a7fd9a4f JA |
25 | |
26 | struct ppa_addr { | |
27 | /* Generic structure for all addresses */ | |
28 | union { | |
29 | struct { | |
30 | u64 blk : NVM_BLK_BITS; | |
31 | u64 pg : NVM_PG_BITS; | |
32 | u64 sec : NVM_SEC_BITS; | |
33 | u64 pl : NVM_PL_BITS; | |
34 | u64 lun : NVM_LUN_BITS; | |
35 | u64 ch : NVM_CH_BITS; | |
df414b33 | 36 | u64 reserved : 1; |
a7fd9a4f JA |
37 | } g; |
38 | ||
df414b33 MB |
39 | struct { |
40 | u64 line : 63; | |
41 | u64 is_cached : 1; | |
42 | } c; | |
43 | ||
a7fd9a4f JA |
44 | u64 ppa; |
45 | }; | |
46 | }; | |
47 | ||
48 | struct nvm_rq; | |
49 | struct nvm_id; | |
50 | struct nvm_dev; | |
8e53624d | 51 | struct nvm_tgt_dev; |
a7fd9a4f JA |
52 | |
53 | typedef int (nvm_l2p_update_fn)(u64, u32, __le64 *, void *); | |
a7fd9a4f JA |
54 | typedef int (nvm_id_fn)(struct nvm_dev *, struct nvm_id *); |
55 | typedef int (nvm_get_l2p_tbl_fn)(struct nvm_dev *, u64, u32, | |
56 | nvm_l2p_update_fn *, void *); | |
e11903f5 | 57 | typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *); |
00ee6cc3 | 58 | typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int); |
a7fd9a4f | 59 | typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *); |
1a94b2d4 | 60 | typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *); |
a7fd9a4f JA |
61 | typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *); |
62 | typedef void (nvm_destroy_dma_pool_fn)(void *); | |
63 | typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t, | |
64 | dma_addr_t *); | |
65 | typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t); | |
66 | ||
67 | struct nvm_dev_ops { | |
68 | nvm_id_fn *identity; | |
69 | nvm_get_l2p_tbl_fn *get_l2p_tbl; | |
70 | nvm_op_bb_tbl_fn *get_bb_tbl; | |
71 | nvm_op_set_bb_fn *set_bb_tbl; | |
72 | ||
73 | nvm_submit_io_fn *submit_io; | |
1a94b2d4 | 74 | nvm_submit_io_sync_fn *submit_io_sync; |
a7fd9a4f JA |
75 | |
76 | nvm_create_dma_pool_fn *create_dma_pool; | |
77 | nvm_destroy_dma_pool_fn *destroy_dma_pool; | |
78 | nvm_dev_dma_alloc_fn *dev_dma_alloc; | |
79 | nvm_dev_dma_free_fn *dev_dma_free; | |
80 | ||
81 | unsigned int max_phys_sect; | |
82 | }; | |
83 | ||
cd9e9808 MB |
84 | #ifdef CONFIG_NVM |
85 | ||
86 | #include <linux/blkdev.h> | |
cd9e9808 MB |
87 | #include <linux/file.h> |
88 | #include <linux/dmapool.h> | |
e3eb3799 | 89 | #include <uapi/linux/lightnvm.h> |
cd9e9808 MB |
90 | |
91 | enum { | |
92 | /* HW Responsibilities */ | |
93 | NVM_RSP_L2P = 1 << 0, | |
94 | NVM_RSP_ECC = 1 << 1, | |
95 | ||
96 | /* Physical Adressing Mode */ | |
97 | NVM_ADDRMODE_LINEAR = 0, | |
98 | NVM_ADDRMODE_CHANNEL = 1, | |
99 | ||
100 | /* Plane programming mode for LUN */ | |
d5bdec8d MB |
101 | NVM_PLANE_SINGLE = 1, |
102 | NVM_PLANE_DOUBLE = 2, | |
103 | NVM_PLANE_QUAD = 4, | |
cd9e9808 MB |
104 | |
105 | /* Status codes */ | |
106 | NVM_RSP_SUCCESS = 0x0, | |
107 | NVM_RSP_NOT_CHANGEABLE = 0x1, | |
108 | NVM_RSP_ERR_FAILWRITE = 0x40ff, | |
109 | NVM_RSP_ERR_EMPTYPAGE = 0x42ff, | |
402ab9a8 | 110 | NVM_RSP_ERR_FAILECC = 0x4281, |
38ea2f76 | 111 | NVM_RSP_ERR_FAILCRC = 0x4004, |
402ab9a8 | 112 | NVM_RSP_WARN_HIGHECC = 0x4700, |
cd9e9808 MB |
113 | |
114 | /* Device opcodes */ | |
115 | NVM_OP_HBREAD = 0x02, | |
116 | NVM_OP_HBWRITE = 0x81, | |
117 | NVM_OP_PWRITE = 0x91, | |
118 | NVM_OP_PREAD = 0x92, | |
119 | NVM_OP_ERASE = 0x90, | |
120 | ||
121 | /* PPA Command Flags */ | |
122 | NVM_IO_SNGL_ACCESS = 0x0, | |
123 | NVM_IO_DUAL_ACCESS = 0x1, | |
124 | NVM_IO_QUAD_ACCESS = 0x2, | |
125 | ||
57b4bd06 | 126 | /* NAND Access Modes */ |
cd9e9808 MB |
127 | NVM_IO_SUSPEND = 0x80, |
128 | NVM_IO_SLC_MODE = 0x100, | |
a7737f39 | 129 | NVM_IO_SCRAMBLE_ENABLE = 0x200, |
57b4bd06 MB |
130 | |
131 | /* Block Types */ | |
132 | NVM_BLK_T_FREE = 0x0, | |
133 | NVM_BLK_T_BAD = 0x1, | |
b5d4acd4 MB |
134 | NVM_BLK_T_GRWN_BAD = 0x2, |
135 | NVM_BLK_T_DEV = 0x4, | |
136 | NVM_BLK_T_HOST = 0x8, | |
f9a99950 MB |
137 | |
138 | /* Memory capabilities */ | |
139 | NVM_ID_CAP_SLC = 0x1, | |
140 | NVM_ID_CAP_CMD_SUSPEND = 0x2, | |
141 | NVM_ID_CAP_SCRAMBLE = 0x4, | |
142 | NVM_ID_CAP_ENCRYPT = 0x8, | |
ca5927e7 MB |
143 | |
144 | /* Memory types */ | |
145 | NVM_ID_FMTYPE_SLC = 0, | |
146 | NVM_ID_FMTYPE_MLC = 1, | |
bf643185 MB |
147 | |
148 | /* Device capabilities */ | |
149 | NVM_ID_DCAP_BBLKMGMT = 0x1, | |
150 | NVM_UD_DCAP_ECC = 0x2, | |
ca5927e7 MB |
151 | }; |
152 | ||
153 | struct nvm_id_lp_mlc { | |
154 | u16 num_pairs; | |
155 | u8 pairs[886]; | |
156 | }; | |
157 | ||
158 | struct nvm_id_lp_tbl { | |
159 | __u8 id[8]; | |
160 | struct nvm_id_lp_mlc mlc; | |
cd9e9808 MB |
161 | }; |
162 | ||
163 | struct nvm_id_group { | |
164 | u8 mtype; | |
165 | u8 fmtype; | |
cd9e9808 MB |
166 | u8 num_ch; |
167 | u8 num_lun; | |
168 | u8 num_pln; | |
169 | u16 num_blk; | |
170 | u16 num_pg; | |
171 | u16 fpg_sz; | |
172 | u16 csecs; | |
173 | u16 sos; | |
174 | u32 trdt; | |
175 | u32 trdm; | |
176 | u32 tprt; | |
177 | u32 tprm; | |
178 | u32 tbet; | |
179 | u32 tbem; | |
180 | u32 mpos; | |
12be5edf | 181 | u32 mccap; |
cd9e9808 | 182 | u16 cpar; |
ca5927e7 MB |
183 | |
184 | struct nvm_id_lp_tbl lptbl; | |
73387e7b | 185 | }; |
cd9e9808 MB |
186 | |
187 | struct nvm_addr_format { | |
188 | u8 ch_offset; | |
189 | u8 ch_len; | |
190 | u8 lun_offset; | |
191 | u8 lun_len; | |
192 | u8 pln_offset; | |
193 | u8 pln_len; | |
194 | u8 blk_offset; | |
195 | u8 blk_len; | |
196 | u8 pg_offset; | |
197 | u8 pg_len; | |
198 | u8 sect_offset; | |
199 | u8 sect_len; | |
cd9e9808 MB |
200 | }; |
201 | ||
202 | struct nvm_id { | |
203 | u8 ver_id; | |
204 | u8 vmnt; | |
cd9e9808 MB |
205 | u32 cap; |
206 | u32 dom; | |
207 | struct nvm_addr_format ppaf; | |
19bd6fe7 | 208 | struct nvm_id_group grp; |
cd9e9808 MB |
209 | } __packed; |
210 | ||
211 | struct nvm_target { | |
212 | struct list_head list; | |
8e79b5cb | 213 | struct nvm_tgt_dev *dev; |
cd9e9808 MB |
214 | struct nvm_tgt_type *type; |
215 | struct gendisk *disk; | |
216 | }; | |
217 | ||
cd9e9808 MB |
218 | #define ADDR_EMPTY (~0ULL) |
219 | ||
220 | #define NVM_VERSION_MAJOR 1 | |
221 | #define NVM_VERSION_MINOR 0 | |
222 | #define NVM_VERSION_PATCH 0 | |
223 | ||
91276162 | 224 | struct nvm_rq; |
72d256ec | 225 | typedef void (nvm_end_io_fn)(struct nvm_rq *); |
91276162 | 226 | |
cd9e9808 | 227 | struct nvm_rq { |
8e53624d | 228 | struct nvm_tgt_dev *dev; |
cd9e9808 MB |
229 | |
230 | struct bio *bio; | |
231 | ||
232 | union { | |
233 | struct ppa_addr ppa_addr; | |
234 | dma_addr_t dma_ppa_list; | |
235 | }; | |
236 | ||
237 | struct ppa_addr *ppa_list; | |
238 | ||
003fad37 JG |
239 | void *meta_list; |
240 | dma_addr_t dma_meta_list; | |
cd9e9808 | 241 | |
91276162 MB |
242 | struct completion *wait; |
243 | nvm_end_io_fn *end_io; | |
244 | ||
cd9e9808 | 245 | uint8_t opcode; |
6d5be959 | 246 | uint16_t nr_ppas; |
cd9e9808 | 247 | uint16_t flags; |
72d256ec | 248 | |
9f867268 | 249 | u64 ppa_status; /* ppa media status */ |
72d256ec | 250 | int error; |
06894efe MB |
251 | |
252 | void *private; | |
cd9e9808 MB |
253 | }; |
254 | ||
255 | static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu) | |
256 | { | |
257 | return pdu - sizeof(struct nvm_rq); | |
258 | } | |
259 | ||
260 | static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata) | |
261 | { | |
262 | return rqdata + 1; | |
263 | } | |
264 | ||
ff0e498b JG |
265 | enum { |
266 | NVM_BLK_ST_FREE = 0x1, /* Free block */ | |
077d2389 | 267 | NVM_BLK_ST_TGT = 0x2, /* Block in use by target */ |
ff0e498b | 268 | NVM_BLK_ST_BAD = 0x8, /* Bad block */ |
cd9e9808 MB |
269 | }; |
270 | ||
8e79b5cb JG |
271 | /* Device generic information */ |
272 | struct nvm_geo { | |
cd9e9808 | 273 | int nr_chnls; |
8e79b5cb JG |
274 | int nr_luns; |
275 | int luns_per_chnl; /* -1 if channels are not symmetric */ | |
cd9e9808 | 276 | int nr_planes; |
cd9e9808 MB |
277 | int sec_per_pg; /* only sectors for a single page */ |
278 | int pgs_per_blk; | |
279 | int blks_per_lun; | |
4891d120 MB |
280 | int fpg_size; |
281 | int pfpg_size; /* size of buffer if all pages are to be read */ | |
cd9e9808 MB |
282 | int sec_size; |
283 | int oob_size; | |
f9a99950 | 284 | int mccap; |
7386af27 | 285 | struct nvm_addr_format ppaf; |
cd9e9808 MB |
286 | |
287 | /* Calculated/Cached values. These do not reflect the actual usable | |
288 | * blocks at run-time. | |
289 | */ | |
290 | int max_rq_size; | |
291 | int plane_mode; /* drive device in single, double or quad mode */ | |
292 | ||
293 | int sec_per_pl; /* all sectors across planes */ | |
294 | int sec_per_blk; | |
295 | int sec_per_lun; | |
8e79b5cb JG |
296 | }; |
297 | ||
ade69e24 | 298 | /* sub-device structure */ |
8e79b5cb JG |
299 | struct nvm_tgt_dev { |
300 | /* Device information */ | |
301 | struct nvm_geo geo; | |
302 | ||
8e53624d JG |
303 | /* Base ppas for target LUNs */ |
304 | struct ppa_addr *luns; | |
305 | ||
8e79b5cb JG |
306 | sector_t total_secs; |
307 | ||
308 | struct nvm_id identity; | |
309 | struct request_queue *q; | |
310 | ||
959e911b | 311 | struct nvm_dev *parent; |
8e53624d | 312 | void *map; |
8e79b5cb JG |
313 | }; |
314 | ||
315 | struct nvm_dev { | |
316 | struct nvm_dev_ops *ops; | |
317 | ||
318 | struct list_head devices; | |
319 | ||
8e79b5cb JG |
320 | /* Device information */ |
321 | struct nvm_geo geo; | |
cd9e9808 | 322 | |
ade69e24 | 323 | /* lower page table */ |
ca5927e7 MB |
324 | int lps_per_blk; |
325 | int *lptbl; | |
326 | ||
4ece44af | 327 | unsigned long total_secs; |
cd9e9808 | 328 | |
da1e2849 | 329 | unsigned long *lun_map; |
75b85649 | 330 | void *dma_pool; |
cd9e9808 MB |
331 | |
332 | struct nvm_id identity; | |
333 | ||
334 | /* Backend device */ | |
335 | struct request_queue *q; | |
336 | char name[DISK_NAME_LEN]; | |
40267efd | 337 | void *private_data; |
e3eb3799 | 338 | |
8e53624d JG |
339 | void *rmap; |
340 | ||
e3eb3799 | 341 | struct mutex mlock; |
4c9dacb8 | 342 | spinlock_t lock; |
ade69e24 MB |
343 | |
344 | /* target management */ | |
345 | struct list_head area_list; | |
346 | struct list_head targets; | |
cd9e9808 MB |
347 | }; |
348 | ||
8e79b5cb | 349 | static inline struct ppa_addr linear_to_generic_addr(struct nvm_geo *geo, |
8e53624d | 350 | u64 pba) |
0e5c3246 JG |
351 | { |
352 | struct ppa_addr l; | |
353 | int secs, pgs, blks, luns; | |
8e53624d | 354 | sector_t ppa = pba; |
0e5c3246 JG |
355 | |
356 | l.ppa = 0; | |
357 | ||
8e79b5cb | 358 | div_u64_rem(ppa, geo->sec_per_pg, &secs); |
0e5c3246 JG |
359 | l.g.sec = secs; |
360 | ||
8e79b5cb JG |
361 | sector_div(ppa, geo->sec_per_pg); |
362 | div_u64_rem(ppa, geo->pgs_per_blk, &pgs); | |
0e5c3246 JG |
363 | l.g.pg = pgs; |
364 | ||
8e79b5cb JG |
365 | sector_div(ppa, geo->pgs_per_blk); |
366 | div_u64_rem(ppa, geo->blks_per_lun, &blks); | |
0e5c3246 JG |
367 | l.g.blk = blks; |
368 | ||
8e79b5cb JG |
369 | sector_div(ppa, geo->blks_per_lun); |
370 | div_u64_rem(ppa, geo->luns_per_chnl, &luns); | |
0e5c3246 JG |
371 | l.g.lun = luns; |
372 | ||
8e79b5cb | 373 | sector_div(ppa, geo->luns_per_chnl); |
0e5c3246 JG |
374 | l.g.ch = ppa; |
375 | ||
376 | return l; | |
377 | } | |
378 | ||
dab8ee9e MB |
379 | static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev, |
380 | struct ppa_addr r) | |
cd9e9808 | 381 | { |
dab8ee9e | 382 | struct nvm_geo *geo = &tgt_dev->geo; |
cd9e9808 MB |
383 | struct ppa_addr l; |
384 | ||
8e79b5cb JG |
385 | l.ppa = ((u64)r.g.blk) << geo->ppaf.blk_offset; |
386 | l.ppa |= ((u64)r.g.pg) << geo->ppaf.pg_offset; | |
387 | l.ppa |= ((u64)r.g.sec) << geo->ppaf.sect_offset; | |
388 | l.ppa |= ((u64)r.g.pl) << geo->ppaf.pln_offset; | |
389 | l.ppa |= ((u64)r.g.lun) << geo->ppaf.lun_offset; | |
390 | l.ppa |= ((u64)r.g.ch) << geo->ppaf.ch_offset; | |
cd9e9808 MB |
391 | |
392 | return l; | |
393 | } | |
394 | ||
dab8ee9e MB |
395 | static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev, |
396 | struct ppa_addr r) | |
cd9e9808 | 397 | { |
dab8ee9e | 398 | struct nvm_geo *geo = &tgt_dev->geo; |
cd9e9808 MB |
399 | struct ppa_addr l; |
400 | ||
5389a1df | 401 | l.ppa = 0; |
7386af27 MB |
402 | /* |
403 | * (r.ppa << X offset) & X len bitmask. X eq. blk, pg, etc. | |
404 | */ | |
8e79b5cb JG |
405 | l.g.blk = (r.ppa >> geo->ppaf.blk_offset) & |
406 | (((1 << geo->ppaf.blk_len) - 1)); | |
407 | l.g.pg |= (r.ppa >> geo->ppaf.pg_offset) & | |
408 | (((1 << geo->ppaf.pg_len) - 1)); | |
409 | l.g.sec |= (r.ppa >> geo->ppaf.sect_offset) & | |
410 | (((1 << geo->ppaf.sect_len) - 1)); | |
411 | l.g.pl |= (r.ppa >> geo->ppaf.pln_offset) & | |
412 | (((1 << geo->ppaf.pln_len) - 1)); | |
413 | l.g.lun |= (r.ppa >> geo->ppaf.lun_offset) & | |
414 | (((1 << geo->ppaf.lun_len) - 1)); | |
415 | l.g.ch |= (r.ppa >> geo->ppaf.ch_offset) & | |
416 | (((1 << geo->ppaf.ch_len) - 1)); | |
cd9e9808 MB |
417 | |
418 | return l; | |
419 | } | |
420 | ||
cd9e9808 MB |
421 | static inline int ppa_empty(struct ppa_addr ppa_addr) |
422 | { | |
423 | return (ppa_addr.ppa == ADDR_EMPTY); | |
424 | } | |
425 | ||
426 | static inline void ppa_set_empty(struct ppa_addr *ppa_addr) | |
427 | { | |
428 | ppa_addr->ppa = ADDR_EMPTY; | |
429 | } | |
430 | ||
a24ba464 JG |
431 | static inline int ppa_cmp_blk(struct ppa_addr ppa1, struct ppa_addr ppa2) |
432 | { | |
433 | if (ppa_empty(ppa1) || ppa_empty(ppa2)) | |
434 | return 0; | |
435 | ||
436 | return ((ppa1.g.ch == ppa2.g.ch) && (ppa1.g.lun == ppa2.g.lun) && | |
437 | (ppa1.g.blk == ppa2.g.blk)); | |
438 | } | |
439 | ||
dece1635 | 440 | typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *); |
cd9e9808 | 441 | typedef sector_t (nvm_tgt_capacity_fn)(void *); |
4af3f75d JG |
442 | typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *, |
443 | int flags); | |
cd9e9808 | 444 | typedef void (nvm_tgt_exit_fn)(void *); |
9a69b0ed JG |
445 | typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *); |
446 | typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *); | |
cd9e9808 MB |
447 | |
448 | struct nvm_tgt_type { | |
449 | const char *name; | |
450 | unsigned int version[3]; | |
451 | ||
452 | /* target entry points */ | |
453 | nvm_tgt_make_rq_fn *make_rq; | |
454 | nvm_tgt_capacity_fn *capacity; | |
cd9e9808 MB |
455 | |
456 | /* module-specific init/teardown */ | |
457 | nvm_tgt_init_fn *init; | |
458 | nvm_tgt_exit_fn *exit; | |
459 | ||
9a69b0ed JG |
460 | /* sysfs */ |
461 | nvm_tgt_sysfs_init_fn *sysfs_init; | |
462 | nvm_tgt_sysfs_exit_fn *sysfs_exit; | |
463 | ||
cd9e9808 MB |
464 | /* For internal use */ |
465 | struct list_head list; | |
90014829 | 466 | struct module *owner; |
cd9e9808 MB |
467 | }; |
468 | ||
6063fe39 SL |
469 | extern int nvm_register_tgt_type(struct nvm_tgt_type *); |
470 | extern void nvm_unregister_tgt_type(struct nvm_tgt_type *); | |
cd9e9808 MB |
471 | |
472 | extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *); | |
473 | extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t); | |
474 | ||
b0b4e09c MB |
475 | extern struct nvm_dev *nvm_alloc_dev(int); |
476 | extern int nvm_register(struct nvm_dev *); | |
477 | extern void nvm_unregister(struct nvm_dev *); | |
cd9e9808 | 478 | |
333ba053 JG |
479 | extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *, |
480 | int, int); | |
a279006a | 481 | extern int nvm_max_phys_sects(struct nvm_tgt_dev *); |
8e53624d | 482 | extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *); |
1a94b2d4 | 483 | extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *); |
17912c49 | 484 | extern int nvm_erase_sync(struct nvm_tgt_dev *, struct ppa_addr *, int); |
da2d7cb8 | 485 | extern int nvm_get_l2p_tbl(struct nvm_tgt_dev *, u64, u32, nvm_l2p_update_fn *, |
8e53624d | 486 | void *); |
da2d7cb8 JG |
487 | extern int nvm_get_area(struct nvm_tgt_dev *, sector_t *, sector_t); |
488 | extern void nvm_put_area(struct nvm_tgt_dev *, sector_t); | |
06894efe | 489 | extern void nvm_end_io(struct nvm_rq *); |
22e8c976 | 490 | extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int); |
333ba053 | 491 | extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *); |
e3eb3799 | 492 | |
ade69e24 | 493 | extern void nvm_part_to_tgt(struct nvm_dev *, sector_t *, int); |
5136061c | 494 | |
cd9e9808 MB |
495 | #else /* CONFIG_NVM */ |
496 | struct nvm_dev_ops; | |
497 | ||
b0b4e09c MB |
498 | static inline struct nvm_dev *nvm_alloc_dev(int node) |
499 | { | |
500 | return ERR_PTR(-EINVAL); | |
501 | } | |
502 | static inline int nvm_register(struct nvm_dev *dev) | |
cd9e9808 MB |
503 | { |
504 | return -EINVAL; | |
505 | } | |
b0b4e09c | 506 | static inline void nvm_unregister(struct nvm_dev *dev) {} |
cd9e9808 MB |
507 | #endif /* CONFIG_NVM */ |
508 | #endif /* LIGHTNVM.H */ |