[linux-block.git] / include / linux / libnvdimm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * libnvdimm - Non-volatile-memory Devices Subsystem
 *
 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
 */
#ifndef __LIBNVDIMM_H__
#define __LIBNVDIMM_H__
#include <linux/kernel.h>
#include <linux/sizes.h>
#include <linux/types.h>
#include <linux/uuid.h>
#include <linux/spinlock.h>
#include <linux/bio.h>

struct badrange_entry {
	u64 start;
	u64 length;
	struct list_head list;
};

struct badrange {
	struct list_head list;
	spinlock_t lock;
};

enum {
	/* unarmed memory devices may not persist writes */
	NDD_UNARMED = 1,
	/* locked memory devices should not be accessed */
	NDD_LOCKED = 2,
	/* memory under security wipes should not be accessed */
	NDD_SECURITY_OVERWRITE = 3,
	/*  tracking whether or not there is a pending device reference */
	NDD_WORK_PENDING = 4,
	/* dimm supports namespace labels */
	NDD_LABELING = 6,

	/* need to set a limit somewhere, but yes, this is likely overkill */
	ND_IOCTL_MAX_BUFLEN = SZ_4M,
	ND_CMD_MAX_ELEM = 5,
	ND_CMD_MAX_ENVELOPE = 256,
	ND_MAX_MAPPINGS = 32,

	/* region flag indicating to direct-map persistent memory by default */
	ND_REGION_PAGEMAP = 0,
	/*
	 * Platform ensures entire CPU store data path is flushed to pmem on
	 * system power loss.
	 */
	ND_REGION_PERSIST_CACHE = 1,
	/*
	 * Platform provides mechanisms to automatically flush outstanding
	 * write data from memory controler to pmem on system power loss.
	 * (ADR)
	 */
	ND_REGION_PERSIST_MEMCTRL = 2,

	/* Platform provides asynchronous flush mechanism */
	ND_REGION_ASYNC = 3,

	/* Region was created by CXL subsystem */
	ND_REGION_CXL = 4,

	/* mark newly adjusted resources as requiring a label update */
	DPA_RESOURCE_ADJUSTED = 1 << 0,
};

struct nvdimm;
struct nvdimm_bus_descriptor;
typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc,
		struct nvdimm *nvdimm, unsigned int cmd, void *buf,
		unsigned int buf_len, int *cmd_rc);

struct device_node;
struct nvdimm_bus_descriptor {
	const struct attribute_group **attr_groups;
	unsigned long cmd_mask;
	unsigned long dimm_family_mask;
	unsigned long bus_family_mask;
	struct module *module;
	char *provider_name;
	struct device_node *of_node;
	ndctl_fn ndctl;
	int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc);
	int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc,
			struct nvdimm *nvdimm, unsigned int cmd, void *data);
	const struct nvdimm_bus_fw_ops *fw_ops;
};

struct nd_cmd_desc {
	int in_num;
	int out_num;
	u32 in_sizes[ND_CMD_MAX_ELEM];
	int out_sizes[ND_CMD_MAX_ELEM];
};

struct nd_interleave_set {
	/* v1.1 definition of the interleave-set-cookie algorithm */
	u64 cookie1;
	/* v1.2 definition of the interleave-set-cookie algorithm */
	u64 cookie2;
	/* compatibility with initial buggy Linux implementation */
	u64 altcookie;

	guid_t type_guid;
};

struct nd_mapping_desc {
	struct nvdimm *nvdimm;
	u64 start;
	u64 size;
	int position;
};

struct nd_region;
struct nd_region_desc {
	struct resource *res;
	struct nd_mapping_desc *mapping;
	u16 num_mappings;
	const struct attribute_group **attr_groups;
	struct nd_interleave_set *nd_set;
	void *provider_data;
	int num_lanes;
	int numa_node;
	int target_node;
	unsigned long flags;
	int memregion;
	struct device_node *of_node;
	int (*flush)(struct nd_region *nd_region, struct bio *bio);
};

struct device;
void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset,
		size_t size, unsigned long flags);
static inline void __iomem *devm_nvdimm_ioremap(struct device *dev,
		resource_size_t offset, size_t size)
{
	return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0);
}

struct nvdimm_bus;

/*
 * Note that separate bits for locked + unlocked are defined so that
 * 'flags == 0' corresponds to an error / not-supported state.
 */
enum nvdimm_security_bits {
	NVDIMM_SECURITY_DISABLED,
	NVDIMM_SECURITY_UNLOCKED,
	NVDIMM_SECURITY_LOCKED,
	NVDIMM_SECURITY_FROZEN,
	NVDIMM_SECURITY_OVERWRITE,
};

#define NVDIMM_PASSPHRASE_LEN		32
#define NVDIMM_KEY_DESC_LEN		22

struct nvdimm_key_data {
	u8 data[NVDIMM_PASSPHRASE_LEN];
};

enum nvdimm_passphrase_type {
	NVDIMM_USER,
	NVDIMM_MASTER,
};

struct nvdimm_security_ops {
	unsigned long (*get_flags)(struct nvdimm *nvdimm,
			enum nvdimm_passphrase_type pass_type);
	int (*freeze)(struct nvdimm *nvdimm);
	int (*change_key)(struct nvdimm *nvdimm,
			const struct nvdimm_key_data *old_data,
			const struct nvdimm_key_data *new_data,
			enum nvdimm_passphrase_type pass_type);
	int (*unlock)(struct nvdimm *nvdimm,
			const struct nvdimm_key_data *key_data);
	int (*disable)(struct nvdimm *nvdimm,
			const struct nvdimm_key_data *key_data);
	int (*erase)(struct nvdimm *nvdimm,
			const struct nvdimm_key_data *key_data,
			enum nvdimm_passphrase_type pass_type);
	int (*overwrite)(struct nvdimm *nvdimm,
			const struct nvdimm_key_data *key_data);
	int (*query_overwrite)(struct nvdimm *nvdimm);
};

enum nvdimm_fwa_state {
	NVDIMM_FWA_INVALID,
	NVDIMM_FWA_IDLE,
	NVDIMM_FWA_ARMED,
	NVDIMM_FWA_BUSY,
	NVDIMM_FWA_ARM_OVERFLOW,
};

enum nvdimm_fwa_trigger {
	NVDIMM_FWA_ARM,
	NVDIMM_FWA_DISARM,
};

enum nvdimm_fwa_capability {
	NVDIMM_FWA_CAP_INVALID,
	NVDIMM_FWA_CAP_NONE,
	NVDIMM_FWA_CAP_QUIESCE,
	NVDIMM_FWA_CAP_LIVE,
};

enum nvdimm_fwa_result {
	NVDIMM_FWA_RESULT_INVALID,
	NVDIMM_FWA_RESULT_NONE,
	NVDIMM_FWA_RESULT_SUCCESS,
	NVDIMM_FWA_RESULT_NOTSTAGED,
	NVDIMM_FWA_RESULT_NEEDRESET,
	NVDIMM_FWA_RESULT_FAIL,
};

struct nvdimm_bus_fw_ops {
	enum nvdimm_fwa_state (*activate_state)
		(struct nvdimm_bus_descriptor *nd_desc);
	enum nvdimm_fwa_capability (*capability)
		(struct nvdimm_bus_descriptor *nd_desc);
	int (*activate)(struct nvdimm_bus_descriptor *nd_desc);
};

struct nvdimm_fw_ops {
	enum nvdimm_fwa_state (*activate_state)(struct nvdimm *nvdimm);
	enum nvdimm_fwa_result (*activate_result)(struct nvdimm *nvdimm);
	int (*arm)(struct nvdimm *nvdimm, enum nvdimm_fwa_trigger arg);
};

void badrange_init(struct badrange *badrange);
int badrange_add(struct badrange *badrange, u64 addr, u64 length);
void badrange_forget(struct badrange *badrange, phys_addr_t start,
		unsigned int len);
int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr,
		u64 length);
struct nvdimm_bus *nvdimm_bus_register(struct device *parent,
		struct nvdimm_bus_descriptor *nfit_desc);
void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus);
struct nvdimm_bus *to_nvdimm_bus(struct device *dev);
struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm);
struct nvdimm *to_nvdimm(struct device *dev);
struct nd_region *to_nd_region(struct device *dev);
struct device *nd_region_dev(struct nd_region *nd_region);
struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus);
struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus);
const char *nvdimm_name(struct nvdimm *nvdimm);
struct kobject *nvdimm_kobj(struct nvdimm *nvdimm);
unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm);
void *nvdimm_provider_data(struct nvdimm *nvdimm);
struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus,
		void *provider_data, const struct attribute_group **groups,
		unsigned long flags, unsigned long cmd_mask, int num_flush,
		struct resource *flush_wpq, const char *dimm_id,
		const struct nvdimm_security_ops *sec_ops,
		const struct nvdimm_fw_ops *fw_ops);
static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus,
		void *provider_data, const struct attribute_group **groups,
		unsigned long flags, unsigned long cmd_mask, int num_flush,
		struct resource *flush_wpq)
{
	return __nvdimm_create(nvdimm_bus, provider_data, groups, flags,
			cmd_mask, num_flush, flush_wpq, NULL, NULL, NULL);
}
void nvdimm_delete(struct nvdimm *nvdimm);
void nvdimm_region_delete(struct nd_region *nd_region);

const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd);
const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd);
u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd,
		const struct nd_cmd_desc *desc, int idx, void *buf);
u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd,
		const struct nd_cmd_desc *desc, int idx, const u32 *in_field,
		const u32 *out_field, unsigned long remainder);
int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count);
struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus,
		struct nd_region_desc *ndr_desc);
struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus,
		struct nd_region_desc *ndr_desc);
struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus,
		struct nd_region_desc *ndr_desc);
void *nd_region_provider_data(struct nd_region *nd_region);
unsigned int nd_region_acquire_lane(struct nd_region *nd_region);
void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane);
u64 nd_fletcher64(void *addr, size_t len, bool le);
int nvdimm_flush(struct nd_region *nd_region, struct bio *bio);
int generic_nvdimm_flush(struct nd_region *nd_region);
int nvdimm_has_flush(struct nd_region *nd_region);
int nvdimm_has_cache(struct nd_region *nd_region);
int nvdimm_in_overwrite(struct nvdimm *nvdimm);
bool is_nvdimm_sync(struct nd_region *nd_region);

static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf,
		unsigned int buf_len, int *cmd_rc)
{
	struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm);
	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);

	return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc);
}

#ifdef CONFIG_ARCH_HAS_PMEM_API
#define ARCH_MEMREMAP_PMEM MEMREMAP_WB
void arch_wb_cache_pmem(void *addr, size_t size);
void arch_invalidate_pmem(void *addr, size_t size);
#else
#define ARCH_MEMREMAP_PMEM MEMREMAP_WT
static inline void arch_wb_cache_pmem(void *addr, size_t size)
{
}
static inline void arch_invalidate_pmem(void *addr, size_t size)
{
}
#endif

#endif /* __LIBNVDIMM_H__ */
Commit	Line	Data
5b497af4	1	/* SPDX-License-Identifier: GPL-2.0-only */
b94d5230 DW	2	/*
	3	* libnvdimm - Non-volatile-memory Devices Subsystem
	4	*
	5	* Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
b94d5230 DW	6	*/
	7	#ifndef __LIBNVDIMM_H__
	8	#define __LIBNVDIMM_H__
047fc8a1	9	#include <linux/kernel.h>
62232e45 DW	10	#include <linux/sizes.h>
62232e45 DW	11	#include <linux/types.h>
faec6f8a	12	#include <linux/uuid.h>
aa9ad44a	13	#include <linux/spinlock.h>
c5d4355d	14	#include <linux/bio.h>
aa9ad44a DJ	15
	16	struct badrange_entry {
	17	u64 start;
	18	u64 length;
	19	struct list_head list;
	20	};
	21
	22	struct badrange {
	23	struct list_head list;
	24	spinlock_t lock;
	25	};
e6dfb2de DW	26
e6dfb2de DW	27	enum {
58138820	28	/* unarmed memory devices may not persist writes */
8f078b38 DW	29	NDD_UNARMED = 1,
	30	/* locked memory devices should not be accessed */
	31	NDD_LOCKED = 2,
7d988097 DJ	32	/* memory under security wipes should not be accessed */
	33	NDD_SECURITY_OVERWRITE = 3,
	34	/* tracking whether or not there is a pending device reference */
	35	NDD_WORK_PENDING = 4,
a0e37452 DW	36	/* dimm supports namespace labels */
a0e37452 DW	37	NDD_LABELING = 6,
62232e45 DW	38
	39	/* need to set a limit somewhere, but yes, this is likely overkill */
	40	ND_IOCTL_MAX_BUFLEN = SZ_4M,
4577b066	41	ND_CMD_MAX_ELEM = 5,
40abf9be	42	ND_CMD_MAX_ENVELOPE = 256,
1f7df6f8	43	ND_MAX_MAPPINGS = 32,
1b40e09a	44
004f1afb DW	45	/* region flag indicating to direct-map persistent memory by default */
004f1afb DW	46	ND_REGION_PAGEMAP = 0,
06e8ccda DJ	47	/*
	48	* Platform ensures entire CPU store data path is flushed to pmem on
	49	* system power loss.
	50	*/
	51	ND_REGION_PERSIST_CACHE = 1,
30e6d7bf DJ	52	/*
	53	* Platform provides mechanisms to automatically flush outstanding
	54	* write data from memory controler to pmem on system power loss.
	55	* (ADR)
	56	*/
	57	ND_REGION_PERSIST_MEMCTRL = 2,
004f1afb	58
c5d4355d PG	59	/* Platform provides asynchronous flush mechanism */
	60	ND_REGION_ASYNC = 3,
	61
04ad63f0 DW	62	/* Region was created by CXL subsystem */
	63	ND_REGION_CXL = 4,
	64
1b40e09a DW	65	/* mark newly adjusted resources as requiring a label update */
1b40e09a DW	66	DPA_RESOURCE_ADJUSTED = 1 << 0,
e6dfb2de DW	67	};
e6dfb2de DW	68
b94d5230 DW	69	struct nvdimm;
	70	struct nvdimm_bus_descriptor;
	71	typedef int (ndctl_fn)(struct nvdimm_bus_descriptor nd_desc,
	72	struct nvdimm nvdimm, unsigned int cmd, void buf,
aef25338	73	unsigned int buf_len, int *cmd_rc);
b94d5230	74
1ff19f48	75	struct device_node;
b94d5230	76	struct nvdimm_bus_descriptor {
45def22c	77	const struct attribute_group **attr_groups;
e3654eca	78	unsigned long cmd_mask;
92fe2aa8 DW	79	unsigned long dimm_family_mask;
92fe2aa8 DW	80	unsigned long bus_family_mask;
bc9775d8	81	struct module *module;
b94d5230	82	char *provider_name;
1ff19f48	83	struct device_node *of_node;
b94d5230	84	ndctl_fn ndctl;
7ae0fa43	85	int (flush_probe)(struct nvdimm_bus_descriptor nd_desc);
87bf572e	86	int (clear_to_send)(struct nvdimm_bus_descriptor nd_desc,
b3ed2ce0	87	struct nvdimm nvdimm, unsigned int cmd, void data);
48001ea5	88	const struct nvdimm_bus_fw_ops *fw_ops;
b94d5230 DW	89	};
b94d5230 DW	90
62232e45 DW	91	struct nd_cmd_desc {
	92	int in_num;
	93	int out_num;
	94	u32 in_sizes[ND_CMD_MAX_ELEM];
	95	int out_sizes[ND_CMD_MAX_ELEM];
	96	};
	97
eaf96153	98	struct nd_interleave_set {
c12c48ce DW	99	/* v1.1 definition of the interleave-set-cookie algorithm */
	100	u64 cookie1;
	101	/* v1.2 definition of the interleave-set-cookie algorithm */
	102	u64 cookie2;
86ef58a4 DW	103	/* compatibility with initial buggy Linux implementation */
86ef58a4 DW	104	u64 altcookie;
faec6f8a DW	105
faec6f8a DW	106	guid_t type_guid;
eaf96153 DW	107	};
eaf96153 DW	108
44c462eb DW	109	struct nd_mapping_desc {
	110	struct nvdimm *nvdimm;
	111	u64 start;
	112	u64 size;
401c0a19	113	int position;
44c462eb DW	114	};
44c462eb DW	115
c5d4355d	116	struct nd_region;
1f7df6f8 DW	117	struct nd_region_desc {
1f7df6f8 DW	118	struct resource *res;
44c462eb	119	struct nd_mapping_desc *mapping;
1f7df6f8 DW	120	u16 num_mappings;
1f7df6f8 DW	121	const struct attribute_group **attr_groups;
eaf96153	122	struct nd_interleave_set *nd_set;
1f7df6f8	123	void *provider_data;
5212e11f	124	int num_lanes;
41d7a6d6	125	int numa_node;
8fc5c735	126	int target_node;
004f1afb	127	unsigned long flags;
04ad63f0	128	int memregion;
1ff19f48	129	struct device_node *of_node;
c5d4355d	130	int (flush)(struct nd_region nd_region, struct bio *bio);
1f7df6f8 DW	131	};
1f7df6f8 DW	132
29b9aa0a DW	133	struct device;
	134	void devm_nvdimm_memremap(struct device dev, resource_size_t offset,
	135	size_t size, unsigned long flags);
	136	static inline void __iomem devm_nvdimm_ioremap(struct device dev,
	137	resource_size_t offset, size_t size)
	138	{
	139	return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0);
	140	}
	141
62232e45	142	struct nvdimm_bus;
047fc8a1	143
d78c620a DW	144	/*
	145	* Note that separate bits for locked + unlocked are defined so that
	146	* 'flags == 0' corresponds to an error / not-supported state.
	147	*/
	148	enum nvdimm_security_bits {
f2989396 DJ	149	NVDIMM_SECURITY_DISABLED,
	150	NVDIMM_SECURITY_UNLOCKED,
	151	NVDIMM_SECURITY_LOCKED,
	152	NVDIMM_SECURITY_FROZEN,
	153	NVDIMM_SECURITY_OVERWRITE,
	154	};
	155
4c6926a2 DJ	156	#define NVDIMM_PASSPHRASE_LEN 32
	157	#define NVDIMM_KEY_DESC_LEN 22
	158
	159	struct nvdimm_key_data {
	160	u8 data[NVDIMM_PASSPHRASE_LEN];
	161	};
	162
89fa9d8e DJ	163	enum nvdimm_passphrase_type {
	164	NVDIMM_USER,
	165	NVDIMM_MASTER,
	166	};
	167
f2989396	168	struct nvdimm_security_ops {
d78c620a	169	unsigned long (get_flags)(struct nvdimm nvdimm,
89fa9d8e	170	enum nvdimm_passphrase_type pass_type);
37833fb7	171	int (freeze)(struct nvdimm nvdimm);
4c6926a2 DJ	172	int (change_key)(struct nvdimm nvdimm,
4c6926a2 DJ	173	const struct nvdimm_key_data *old_data,
89fa9d8e DJ	174	const struct nvdimm_key_data *new_data,
89fa9d8e DJ	175	enum nvdimm_passphrase_type pass_type);
4c6926a2 DJ	176	int (unlock)(struct nvdimm nvdimm,
4c6926a2 DJ	177	const struct nvdimm_key_data *key_data);
03b65b22 DJ	178	int (disable)(struct nvdimm nvdimm,
03b65b22 DJ	179	const struct nvdimm_key_data *key_data);
64e77c8c	180	int (erase)(struct nvdimm nvdimm,
89fa9d8e DJ	181	const struct nvdimm_key_data *key_data,
89fa9d8e DJ	182	enum nvdimm_passphrase_type pass_type);
7d988097 DJ	183	int (overwrite)(struct nvdimm nvdimm,
	184	const struct nvdimm_key_data *key_data);
	185	int (query_overwrite)(struct nvdimm nvdimm);
f2989396 DJ	186	};
f2989396 DJ	187
48001ea5 DW	188	enum nvdimm_fwa_state {
	189	NVDIMM_FWA_INVALID,
	190	NVDIMM_FWA_IDLE,
	191	NVDIMM_FWA_ARMED,
	192	NVDIMM_FWA_BUSY,
	193	NVDIMM_FWA_ARM_OVERFLOW,
	194	};
	195
	196	enum nvdimm_fwa_trigger {
	197	NVDIMM_FWA_ARM,
	198	NVDIMM_FWA_DISARM,
	199	};
	200
	201	enum nvdimm_fwa_capability {
	202	NVDIMM_FWA_CAP_INVALID,
	203	NVDIMM_FWA_CAP_NONE,
	204	NVDIMM_FWA_CAP_QUIESCE,
	205	NVDIMM_FWA_CAP_LIVE,
	206	};
	207
	208	enum nvdimm_fwa_result {
	209	NVDIMM_FWA_RESULT_INVALID,
	210	NVDIMM_FWA_RESULT_NONE,
	211	NVDIMM_FWA_RESULT_SUCCESS,
	212	NVDIMM_FWA_RESULT_NOTSTAGED,
	213	NVDIMM_FWA_RESULT_NEEDRESET,
	214	NVDIMM_FWA_RESULT_FAIL,
	215	};
	216
	217	struct nvdimm_bus_fw_ops {
	218	enum nvdimm_fwa_state (*activate_state)
	219	(struct nvdimm_bus_descriptor *nd_desc);
	220	enum nvdimm_fwa_capability (*capability)
	221	(struct nvdimm_bus_descriptor *nd_desc);
	222	int (activate)(struct nvdimm_bus_descriptor nd_desc);
	223	};
	224
	225	struct nvdimm_fw_ops {
	226	enum nvdimm_fwa_state (activate_state)(struct nvdimm nvdimm);
	227	enum nvdimm_fwa_result (activate_result)(struct nvdimm nvdimm);
	228	int (arm)(struct nvdimm nvdimm, enum nvdimm_fwa_trigger arg);
	229	};
	230
aa9ad44a DJ	231	void badrange_init(struct badrange *badrange);
	232	int badrange_add(struct badrange *badrange, u64 addr, u64 length);
	233	void badrange_forget(struct badrange *badrange, phys_addr_t start,
	234	unsigned int len);
	235	int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr,
	236	u64 length);
bc9775d8 DW	237	struct nvdimm_bus nvdimm_bus_register(struct device parent,
bc9775d8 DW	238	struct nvdimm_bus_descriptor *nfit_desc);
b94d5230	239	void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus);
45def22c	240	struct nvdimm_bus to_nvdimm_bus(struct device dev);
f2989396	241	struct nvdimm_bus nvdimm_to_bus(struct nvdimm nvdimm);
e6dfb2de	242	struct nvdimm to_nvdimm(struct device dev);
1f7df6f8	243	struct nd_region to_nd_region(struct device dev);
243f29fe	244	struct device nd_region_dev(struct nd_region nd_region);
45def22c	245	struct nvdimm_bus_descriptor to_nd_desc(struct nvdimm_bus nvdimm_bus);
37b137ff	246	struct device to_nvdimm_bus_dev(struct nvdimm_bus nvdimm_bus);
e6dfb2de	247	const char nvdimm_name(struct nvdimm nvdimm);
ba9c8dd3	248	struct kobject nvdimm_kobj(struct nvdimm nvdimm);
e3654eca	249	unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm);
e6dfb2de	250	void nvdimm_provider_data(struct nvdimm nvdimm);
d6548ae4 DJ	251	struct nvdimm __nvdimm_create(struct nvdimm_bus nvdimm_bus,
	252	void provider_data, const struct attribute_group *groups,
	253	unsigned long flags, unsigned long cmd_mask, int num_flush,
f2989396	254	struct resource flush_wpq, const char dimm_id,
a1facc1f DW	255	const struct nvdimm_security_ops *sec_ops,
a1facc1f DW	256	const struct nvdimm_fw_ops *fw_ops);
d6548ae4 DJ	257	static inline struct nvdimm nvdimm_create(struct nvdimm_bus nvdimm_bus,
	258	void provider_data, const struct attribute_group *groups,
	259	unsigned long flags, unsigned long cmd_mask, int num_flush,
	260	struct resource *flush_wpq)
	261	{
	262	return __nvdimm_create(nvdimm_bus, provider_data, groups, flags,
a1facc1f	263	cmd_mask, num_flush, flush_wpq, NULL, NULL, NULL);
d6548ae4	264	}
fd14602d	265	void nvdimm_delete(struct nvdimm *nvdimm);
04ad63f0	266	void nvdimm_region_delete(struct nd_region *nd_region);
d6548ae4	267
62232e45 DW	268	const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd);
	269	const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd);
	270	u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd,
	271	const struct nd_cmd_desc desc, int idx, void buf);
	272	u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd,
	273	const struct nd_cmd_desc desc, int idx, const u32 in_field,
efda1b5d	274	const u32 *out_field, unsigned long remainder);
4d88a97a	275	int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count);
1f7df6f8 DW	276	struct nd_region nvdimm_pmem_region_create(struct nvdimm_bus nvdimm_bus,
	277	struct nd_region_desc *ndr_desc);
	278	struct nd_region nvdimm_blk_region_create(struct nvdimm_bus nvdimm_bus,
	279	struct nd_region_desc *ndr_desc);
	280	struct nd_region nvdimm_volatile_region_create(struct nvdimm_bus nvdimm_bus,
	281	struct nd_region_desc *ndr_desc);
047fc8a1	282	void nd_region_provider_data(struct nd_region nd_region);
047fc8a1 RZ	283	unsigned int nd_region_acquire_lane(struct nd_region *nd_region);
047fc8a1 RZ	284	void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane);
eaf96153	285	u64 nd_fletcher64(void *addr, size_t len, bool le);
c5d4355d PG	286	int nvdimm_flush(struct nd_region nd_region, struct bio bio);
c5d4355d PG	287	int generic_nvdimm_flush(struct nd_region *nd_region);
f284a4f2	288	int nvdimm_has_flush(struct nd_region *nd_region);
0b277961	289	int nvdimm_has_cache(struct nd_region *nd_region);
7d988097	290	int nvdimm_in_overwrite(struct nvdimm *nvdimm);
fefc1d97	291	bool is_nvdimm_sync(struct nd_region *nd_region);
5deb67f7	292
f2989396 DJ	293	static inline int nvdimm_ctl(struct nvdimm nvdimm, unsigned int cmd, void buf,
	294	unsigned int buf_len, int *cmd_rc)
	295	{
	296	struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm);
	297	struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
	298
	299	return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc);
	300	}
	301
5deb67f7 RM	302	#ifdef CONFIG_ARCH_HAS_PMEM_API
	303	#define ARCH_MEMREMAP_PMEM MEMREMAP_WB
	304	void arch_wb_cache_pmem(void *addr, size_t size);
	305	void arch_invalidate_pmem(void *addr, size_t size);
	306	#else
	307	#define ARCH_MEMREMAP_PMEM MEMREMAP_WT
	308	static inline void arch_wb_cache_pmem(void *addr, size_t size)
	309	{
	310	}
	311	static inline void arch_invalidate_pmem(void *addr, size_t size)
	312	{
	313	}
	314	#endif
	315
b94d5230	316	#endif /* __LIBNVDIMM_H__ */