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5b497af4 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
b94d5230 DW |
2 | /* |
3 | * libnvdimm - Non-volatile-memory Devices Subsystem | |
4 | * | |
5 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
b94d5230 DW |
6 | */ |
7 | #ifndef __LIBNVDIMM_H__ | |
8 | #define __LIBNVDIMM_H__ | |
047fc8a1 | 9 | #include <linux/kernel.h> |
62232e45 DW |
10 | #include <linux/sizes.h> |
11 | #include <linux/types.h> | |
faec6f8a | 12 | #include <linux/uuid.h> |
aa9ad44a | 13 | #include <linux/spinlock.h> |
c5d4355d | 14 | #include <linux/bio.h> |
aa9ad44a DJ |
15 | |
16 | struct badrange_entry { | |
17 | u64 start; | |
18 | u64 length; | |
19 | struct list_head list; | |
20 | }; | |
21 | ||
22 | struct badrange { | |
23 | struct list_head list; | |
24 | spinlock_t lock; | |
25 | }; | |
e6dfb2de DW |
26 | |
27 | enum { | |
28 | /* when a dimm supports both PMEM and BLK access a label is required */ | |
8f078b38 | 29 | NDD_ALIASING = 0, |
58138820 | 30 | /* unarmed memory devices may not persist writes */ |
8f078b38 DW |
31 | NDD_UNARMED = 1, |
32 | /* locked memory devices should not be accessed */ | |
33 | NDD_LOCKED = 2, | |
7d988097 DJ |
34 | /* memory under security wipes should not be accessed */ |
35 | NDD_SECURITY_OVERWRITE = 3, | |
36 | /* tracking whether or not there is a pending device reference */ | |
37 | NDD_WORK_PENDING = 4, | |
d5d30d5a DW |
38 | /* ignore / filter NSLABEL_FLAG_LOCAL for this DIMM, i.e. no aliasing */ |
39 | NDD_NOBLK = 5, | |
a0e37452 DW |
40 | /* dimm supports namespace labels */ |
41 | NDD_LABELING = 6, | |
62232e45 DW |
42 | |
43 | /* need to set a limit somewhere, but yes, this is likely overkill */ | |
44 | ND_IOCTL_MAX_BUFLEN = SZ_4M, | |
4577b066 | 45 | ND_CMD_MAX_ELEM = 5, |
40abf9be | 46 | ND_CMD_MAX_ENVELOPE = 256, |
1f7df6f8 | 47 | ND_MAX_MAPPINGS = 32, |
1b40e09a | 48 | |
004f1afb DW |
49 | /* region flag indicating to direct-map persistent memory by default */ |
50 | ND_REGION_PAGEMAP = 0, | |
06e8ccda DJ |
51 | /* |
52 | * Platform ensures entire CPU store data path is flushed to pmem on | |
53 | * system power loss. | |
54 | */ | |
55 | ND_REGION_PERSIST_CACHE = 1, | |
30e6d7bf DJ |
56 | /* |
57 | * Platform provides mechanisms to automatically flush outstanding | |
58 | * write data from memory controler to pmem on system power loss. | |
59 | * (ADR) | |
60 | */ | |
61 | ND_REGION_PERSIST_MEMCTRL = 2, | |
004f1afb | 62 | |
c5d4355d PG |
63 | /* Platform provides asynchronous flush mechanism */ |
64 | ND_REGION_ASYNC = 3, | |
65 | ||
1b40e09a DW |
66 | /* mark newly adjusted resources as requiring a label update */ |
67 | DPA_RESOURCE_ADJUSTED = 1 << 0, | |
e6dfb2de DW |
68 | }; |
69 | ||
b94d5230 DW |
70 | struct nvdimm; |
71 | struct nvdimm_bus_descriptor; | |
72 | typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc, | |
73 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, | |
aef25338 | 74 | unsigned int buf_len, int *cmd_rc); |
b94d5230 | 75 | |
1ff19f48 | 76 | struct device_node; |
b94d5230 | 77 | struct nvdimm_bus_descriptor { |
45def22c | 78 | const struct attribute_group **attr_groups; |
e3654eca | 79 | unsigned long cmd_mask; |
92fe2aa8 DW |
80 | unsigned long dimm_family_mask; |
81 | unsigned long bus_family_mask; | |
bc9775d8 | 82 | struct module *module; |
b94d5230 | 83 | char *provider_name; |
1ff19f48 | 84 | struct device_node *of_node; |
b94d5230 | 85 | ndctl_fn ndctl; |
7ae0fa43 | 86 | int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc); |
87bf572e | 87 | int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc, |
b3ed2ce0 | 88 | struct nvdimm *nvdimm, unsigned int cmd, void *data); |
48001ea5 | 89 | const struct nvdimm_bus_fw_ops *fw_ops; |
b94d5230 DW |
90 | }; |
91 | ||
62232e45 DW |
92 | struct nd_cmd_desc { |
93 | int in_num; | |
94 | int out_num; | |
95 | u32 in_sizes[ND_CMD_MAX_ELEM]; | |
96 | int out_sizes[ND_CMD_MAX_ELEM]; | |
97 | }; | |
98 | ||
eaf96153 | 99 | struct nd_interleave_set { |
c12c48ce DW |
100 | /* v1.1 definition of the interleave-set-cookie algorithm */ |
101 | u64 cookie1; | |
102 | /* v1.2 definition of the interleave-set-cookie algorithm */ | |
103 | u64 cookie2; | |
86ef58a4 DW |
104 | /* compatibility with initial buggy Linux implementation */ |
105 | u64 altcookie; | |
faec6f8a DW |
106 | |
107 | guid_t type_guid; | |
eaf96153 DW |
108 | }; |
109 | ||
44c462eb DW |
110 | struct nd_mapping_desc { |
111 | struct nvdimm *nvdimm; | |
112 | u64 start; | |
113 | u64 size; | |
401c0a19 | 114 | int position; |
44c462eb DW |
115 | }; |
116 | ||
c5d4355d | 117 | struct nd_region; |
1f7df6f8 DW |
118 | struct nd_region_desc { |
119 | struct resource *res; | |
44c462eb | 120 | struct nd_mapping_desc *mapping; |
1f7df6f8 DW |
121 | u16 num_mappings; |
122 | const struct attribute_group **attr_groups; | |
eaf96153 | 123 | struct nd_interleave_set *nd_set; |
1f7df6f8 | 124 | void *provider_data; |
5212e11f | 125 | int num_lanes; |
41d7a6d6 | 126 | int numa_node; |
8fc5c735 | 127 | int target_node; |
004f1afb | 128 | unsigned long flags; |
1ff19f48 | 129 | struct device_node *of_node; |
c5d4355d | 130 | int (*flush)(struct nd_region *nd_region, struct bio *bio); |
1f7df6f8 DW |
131 | }; |
132 | ||
29b9aa0a DW |
133 | struct device; |
134 | void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset, | |
135 | size_t size, unsigned long flags); | |
136 | static inline void __iomem *devm_nvdimm_ioremap(struct device *dev, | |
137 | resource_size_t offset, size_t size) | |
138 | { | |
139 | return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0); | |
140 | } | |
141 | ||
62232e45 | 142 | struct nvdimm_bus; |
3d88002e | 143 | struct module; |
047fc8a1 RZ |
144 | struct nd_blk_region; |
145 | struct nd_blk_region_desc { | |
146 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); | |
047fc8a1 RZ |
147 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
148 | void *iobuf, u64 len, int rw); | |
149 | struct nd_region_desc ndr_desc; | |
150 | }; | |
151 | ||
152 | static inline struct nd_blk_region_desc *to_blk_region_desc( | |
153 | struct nd_region_desc *ndr_desc) | |
154 | { | |
155 | return container_of(ndr_desc, struct nd_blk_region_desc, ndr_desc); | |
156 | ||
157 | } | |
158 | ||
d78c620a DW |
159 | /* |
160 | * Note that separate bits for locked + unlocked are defined so that | |
161 | * 'flags == 0' corresponds to an error / not-supported state. | |
162 | */ | |
163 | enum nvdimm_security_bits { | |
f2989396 DJ |
164 | NVDIMM_SECURITY_DISABLED, |
165 | NVDIMM_SECURITY_UNLOCKED, | |
166 | NVDIMM_SECURITY_LOCKED, | |
167 | NVDIMM_SECURITY_FROZEN, | |
168 | NVDIMM_SECURITY_OVERWRITE, | |
169 | }; | |
170 | ||
4c6926a2 DJ |
171 | #define NVDIMM_PASSPHRASE_LEN 32 |
172 | #define NVDIMM_KEY_DESC_LEN 22 | |
173 | ||
174 | struct nvdimm_key_data { | |
175 | u8 data[NVDIMM_PASSPHRASE_LEN]; | |
176 | }; | |
177 | ||
89fa9d8e DJ |
178 | enum nvdimm_passphrase_type { |
179 | NVDIMM_USER, | |
180 | NVDIMM_MASTER, | |
181 | }; | |
182 | ||
f2989396 | 183 | struct nvdimm_security_ops { |
d78c620a | 184 | unsigned long (*get_flags)(struct nvdimm *nvdimm, |
89fa9d8e | 185 | enum nvdimm_passphrase_type pass_type); |
37833fb7 | 186 | int (*freeze)(struct nvdimm *nvdimm); |
4c6926a2 DJ |
187 | int (*change_key)(struct nvdimm *nvdimm, |
188 | const struct nvdimm_key_data *old_data, | |
89fa9d8e DJ |
189 | const struct nvdimm_key_data *new_data, |
190 | enum nvdimm_passphrase_type pass_type); | |
4c6926a2 DJ |
191 | int (*unlock)(struct nvdimm *nvdimm, |
192 | const struct nvdimm_key_data *key_data); | |
03b65b22 DJ |
193 | int (*disable)(struct nvdimm *nvdimm, |
194 | const struct nvdimm_key_data *key_data); | |
64e77c8c | 195 | int (*erase)(struct nvdimm *nvdimm, |
89fa9d8e DJ |
196 | const struct nvdimm_key_data *key_data, |
197 | enum nvdimm_passphrase_type pass_type); | |
7d988097 DJ |
198 | int (*overwrite)(struct nvdimm *nvdimm, |
199 | const struct nvdimm_key_data *key_data); | |
200 | int (*query_overwrite)(struct nvdimm *nvdimm); | |
f2989396 DJ |
201 | }; |
202 | ||
48001ea5 DW |
203 | enum nvdimm_fwa_state { |
204 | NVDIMM_FWA_INVALID, | |
205 | NVDIMM_FWA_IDLE, | |
206 | NVDIMM_FWA_ARMED, | |
207 | NVDIMM_FWA_BUSY, | |
208 | NVDIMM_FWA_ARM_OVERFLOW, | |
209 | }; | |
210 | ||
211 | enum nvdimm_fwa_trigger { | |
212 | NVDIMM_FWA_ARM, | |
213 | NVDIMM_FWA_DISARM, | |
214 | }; | |
215 | ||
216 | enum nvdimm_fwa_capability { | |
217 | NVDIMM_FWA_CAP_INVALID, | |
218 | NVDIMM_FWA_CAP_NONE, | |
219 | NVDIMM_FWA_CAP_QUIESCE, | |
220 | NVDIMM_FWA_CAP_LIVE, | |
221 | }; | |
222 | ||
223 | enum nvdimm_fwa_result { | |
224 | NVDIMM_FWA_RESULT_INVALID, | |
225 | NVDIMM_FWA_RESULT_NONE, | |
226 | NVDIMM_FWA_RESULT_SUCCESS, | |
227 | NVDIMM_FWA_RESULT_NOTSTAGED, | |
228 | NVDIMM_FWA_RESULT_NEEDRESET, | |
229 | NVDIMM_FWA_RESULT_FAIL, | |
230 | }; | |
231 | ||
232 | struct nvdimm_bus_fw_ops { | |
233 | enum nvdimm_fwa_state (*activate_state) | |
234 | (struct nvdimm_bus_descriptor *nd_desc); | |
235 | enum nvdimm_fwa_capability (*capability) | |
236 | (struct nvdimm_bus_descriptor *nd_desc); | |
237 | int (*activate)(struct nvdimm_bus_descriptor *nd_desc); | |
238 | }; | |
239 | ||
240 | struct nvdimm_fw_ops { | |
241 | enum nvdimm_fwa_state (*activate_state)(struct nvdimm *nvdimm); | |
242 | enum nvdimm_fwa_result (*activate_result)(struct nvdimm *nvdimm); | |
243 | int (*arm)(struct nvdimm *nvdimm, enum nvdimm_fwa_trigger arg); | |
244 | }; | |
245 | ||
aa9ad44a DJ |
246 | void badrange_init(struct badrange *badrange); |
247 | int badrange_add(struct badrange *badrange, u64 addr, u64 length); | |
248 | void badrange_forget(struct badrange *badrange, phys_addr_t start, | |
249 | unsigned int len); | |
250 | int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr, | |
251 | u64 length); | |
bc9775d8 DW |
252 | struct nvdimm_bus *nvdimm_bus_register(struct device *parent, |
253 | struct nvdimm_bus_descriptor *nfit_desc); | |
b94d5230 | 254 | void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus); |
45def22c | 255 | struct nvdimm_bus *to_nvdimm_bus(struct device *dev); |
f2989396 | 256 | struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm); |
e6dfb2de | 257 | struct nvdimm *to_nvdimm(struct device *dev); |
1f7df6f8 | 258 | struct nd_region *to_nd_region(struct device *dev); |
243f29fe | 259 | struct device *nd_region_dev(struct nd_region *nd_region); |
047fc8a1 | 260 | struct nd_blk_region *to_nd_blk_region(struct device *dev); |
45def22c | 261 | struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus); |
37b137ff | 262 | struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus); |
e6dfb2de | 263 | const char *nvdimm_name(struct nvdimm *nvdimm); |
ba9c8dd3 | 264 | struct kobject *nvdimm_kobj(struct nvdimm *nvdimm); |
e3654eca | 265 | unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm); |
e6dfb2de | 266 | void *nvdimm_provider_data(struct nvdimm *nvdimm); |
d6548ae4 DJ |
267 | struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
268 | void *provider_data, const struct attribute_group **groups, | |
269 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
f2989396 | 270 | struct resource *flush_wpq, const char *dimm_id, |
a1facc1f DW |
271 | const struct nvdimm_security_ops *sec_ops, |
272 | const struct nvdimm_fw_ops *fw_ops); | |
d6548ae4 DJ |
273 | static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
274 | void *provider_data, const struct attribute_group **groups, | |
275 | unsigned long flags, unsigned long cmd_mask, int num_flush, | |
276 | struct resource *flush_wpq) | |
277 | { | |
278 | return __nvdimm_create(nvdimm_bus, provider_data, groups, flags, | |
a1facc1f | 279 | cmd_mask, num_flush, flush_wpq, NULL, NULL, NULL); |
d6548ae4 | 280 | } |
fd14602d | 281 | void nvdimm_delete(struct nvdimm *nvdimm); |
d6548ae4 | 282 | |
62232e45 DW |
283 | const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd); |
284 | const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd); | |
285 | u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd, | |
286 | const struct nd_cmd_desc *desc, int idx, void *buf); | |
287 | u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd, | |
288 | const struct nd_cmd_desc *desc, int idx, const u32 *in_field, | |
efda1b5d | 289 | const u32 *out_field, unsigned long remainder); |
4d88a97a | 290 | int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count); |
1f7df6f8 DW |
291 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, |
292 | struct nd_region_desc *ndr_desc); | |
293 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, | |
294 | struct nd_region_desc *ndr_desc); | |
295 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, | |
296 | struct nd_region_desc *ndr_desc); | |
047fc8a1 RZ |
297 | void *nd_region_provider_data(struct nd_region *nd_region); |
298 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr); | |
299 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data); | |
300 | struct nvdimm *nd_blk_region_to_dimm(struct nd_blk_region *ndbr); | |
ca6a4657 | 301 | unsigned long nd_blk_memremap_flags(struct nd_blk_region *ndbr); |
047fc8a1 RZ |
302 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region); |
303 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); | |
eaf96153 | 304 | u64 nd_fletcher64(void *addr, size_t len, bool le); |
c5d4355d PG |
305 | int nvdimm_flush(struct nd_region *nd_region, struct bio *bio); |
306 | int generic_nvdimm_flush(struct nd_region *nd_region); | |
f284a4f2 | 307 | int nvdimm_has_flush(struct nd_region *nd_region); |
0b277961 | 308 | int nvdimm_has_cache(struct nd_region *nd_region); |
7d988097 | 309 | int nvdimm_in_overwrite(struct nvdimm *nvdimm); |
fefc1d97 | 310 | bool is_nvdimm_sync(struct nd_region *nd_region); |
5deb67f7 | 311 | |
f2989396 DJ |
312 | static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
313 | unsigned int buf_len, int *cmd_rc) | |
314 | { | |
315 | struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm); | |
316 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); | |
317 | ||
318 | return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); | |
319 | } | |
320 | ||
5deb67f7 RM |
321 | #ifdef CONFIG_ARCH_HAS_PMEM_API |
322 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WB | |
323 | void arch_wb_cache_pmem(void *addr, size_t size); | |
324 | void arch_invalidate_pmem(void *addr, size_t size); | |
325 | #else | |
326 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WT | |
327 | static inline void arch_wb_cache_pmem(void *addr, size_t size) | |
328 | { | |
329 | } | |
330 | static inline void arch_invalidate_pmem(void *addr, size_t size) | |
331 | { | |
332 | } | |
333 | #endif | |
334 | ||
b94d5230 | 335 | #endif /* __LIBNVDIMM_H__ */ |