Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
08a543ad GL |
2 | /* |
3 | * irq_domain - IRQ translation domains | |
4 | * | |
5 | * Translation infrastructure between hw and linux irq numbers. This is | |
6 | * helpful for interrupt controllers to implement mapping between hardware | |
7 | * irq numbers and the Linux irq number space. | |
8 | * | |
e7a46c81 MZ |
9 | * irq_domains also have hooks for translating device tree or other |
10 | * firmware interrupt representations into a hardware irq number that | |
11 | * can be mapped back to a Linux irq number without any extra platform | |
12 | * support code. | |
08a543ad | 13 | * |
7bb69bad GL |
14 | * Interrupt controller "domain" data structure. This could be defined as a |
15 | * irq domain controller. That is, it handles the mapping between hardware | |
16 | * and virtual interrupt numbers for a given interrupt domain. The domain | |
17 | * structure is generally created by the PIC code for a given PIC instance | |
18 | * (though a domain can cover more than one PIC if they have a flat number | |
19 | * model). It's the domain callbacks that are responsible for setting the | |
20 | * irq_chip on a given irq_desc after it's been mapped. | |
cc79ca69 | 21 | * |
e7a46c81 MZ |
22 | * The host code and data structures use a fwnode_handle pointer to |
23 | * identify the domain. In some cases, and in order to preserve source | |
24 | * code compatibility, this fwnode pointer is "upgraded" to a DT | |
25 | * device_node. For those firmware infrastructures that do not provide | |
26 | * a unique identifier for an interrupt controller, the irq_domain | |
27 | * code offers a fwnode allocator. | |
08a543ad | 28 | */ |
7bb69bad | 29 | |
08a543ad GL |
30 | #ifndef _LINUX_IRQDOMAIN_H |
31 | #define _LINUX_IRQDOMAIN_H | |
32 | ||
7bb69bad | 33 | #include <linux/types.h> |
aeef2052 | 34 | #include <linux/irqdomain_defs.h> |
1b537708 | 35 | #include <linux/irqhandler.h> |
f110711a | 36 | #include <linux/of.h> |
f1d78358 | 37 | #include <linux/mutex.h> |
7bb69bad | 38 | #include <linux/radix-tree.h> |
08a543ad | 39 | |
08a543ad | 40 | struct device_node; |
08219fb1 | 41 | struct fwnode_handle; |
08a543ad | 42 | struct irq_domain; |
f8264e34 JL |
43 | struct irq_chip; |
44 | struct irq_data; | |
d22558dd | 45 | struct irq_desc; |
06ee6d57 | 46 | struct cpumask; |
c3e7239a | 47 | struct seq_file; |
bec04037 | 48 | struct irq_affinity_desc; |
7bb69bad | 49 | |
11e4438e MZ |
50 | #define IRQ_DOMAIN_IRQ_SPEC_PARAMS 16 |
51 | ||
52 | /** | |
53 | * struct irq_fwspec - generic IRQ specifier structure | |
54 | * | |
55 | * @fwnode: Pointer to a firmware-specific descriptor | |
56 | * @param_count: Number of device-specific parameters | |
57 | * @param: Device-specific parameters | |
58 | * | |
59 | * This structure, directly modeled after of_phandle_args, is used to | |
60 | * pass a device-specific description of an interrupt. | |
61 | */ | |
62 | struct irq_fwspec { | |
63 | struct fwnode_handle *fwnode; | |
64 | int param_count; | |
65 | u32 param[IRQ_DOMAIN_IRQ_SPEC_PARAMS]; | |
66 | }; | |
67 | ||
0ab8d0f6 MZ |
68 | /* Conversion function from of_phandle_args fields to fwspec */ |
69 | void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, | |
70 | unsigned int count, struct irq_fwspec *fwspec); | |
71 | ||
08a543ad GL |
72 | /** |
73 | * struct irq_domain_ops - Methods for irq_domain objects | |
7bb69bad GL |
74 | * @match: Match an interrupt controller device node to a host, returns |
75 | * 1 on a match | |
76 | * @map: Create or update a mapping between a virtual irq number and a hw | |
77 | * irq number. This is called only once for a given mapping. | |
78 | * @unmap: Dispose of such a mapping | |
7bb69bad GL |
79 | * @xlate: Given a device tree node and interrupt specifier, decode |
80 | * the hardware irq number and linux irq type value. | |
81 | * | |
82 | * Functions below are provided by the driver and called whenever a new mapping | |
83 | * is created or an old mapping is disposed. The driver can then proceed to | |
84 | * whatever internal data structures management is required. It also needs | |
85 | * to setup the irq_desc when returning from map(). | |
08a543ad GL |
86 | */ |
87 | struct irq_domain_ops { | |
ad3aedfb MZ |
88 | int (*match)(struct irq_domain *d, struct device_node *node, |
89 | enum irq_domain_bus_token bus_token); | |
651e8b54 MZ |
90 | int (*select)(struct irq_domain *d, struct irq_fwspec *fwspec, |
91 | enum irq_domain_bus_token bus_token); | |
7bb69bad GL |
92 | int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw); |
93 | void (*unmap)(struct irq_domain *d, unsigned int virq); | |
7bb69bad GL |
94 | int (*xlate)(struct irq_domain *d, struct device_node *node, |
95 | const u32 *intspec, unsigned int intsize, | |
96 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 JL |
97 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
98 | /* extended V2 interfaces to support hierarchy irq_domains */ | |
99 | int (*alloc)(struct irq_domain *d, unsigned int virq, | |
100 | unsigned int nr_irqs, void *arg); | |
101 | void (*free)(struct irq_domain *d, unsigned int virq, | |
102 | unsigned int nr_irqs); | |
702cb0a0 | 103 | int (*activate)(struct irq_domain *d, struct irq_data *irqd, bool reserve); |
f8264e34 | 104 | void (*deactivate)(struct irq_domain *d, struct irq_data *irq_data); |
11e4438e MZ |
105 | int (*translate)(struct irq_domain *d, struct irq_fwspec *fwspec, |
106 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 | 107 | #endif |
c3e7239a TG |
108 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
109 | void (*debug_show)(struct seq_file *m, struct irq_domain *d, | |
110 | struct irq_data *irqd, int ind); | |
111 | #endif | |
08a543ad GL |
112 | }; |
113 | ||
4946f15e | 114 | extern const struct irq_domain_ops irq_generic_chip_ops; |
088f40b7 TG |
115 | |
116 | struct irq_domain_chip_generic; | |
117 | ||
08a543ad GL |
118 | /** |
119 | * struct irq_domain - Hardware interrupt number translation object | |
f876ea3b TG |
120 | * @link: Element in global irq_domain list. |
121 | * @name: Name of interrupt domain | |
122 | * @ops: Pointer to irq_domain methods | |
123 | * @host_data: Private data pointer for use by owner. Not touched by irq_domain | |
124 | * core code. | |
125 | * @flags: Per irq_domain flags | |
126 | * @mapcount: The number of mapped interrupts | |
1aa0dd94 | 127 | * |
f876ea3b TG |
128 | * Optional elements: |
129 | * @fwnode: Pointer to firmware node associated with the irq_domain. Pretty easy | |
130 | * to swap it for the of_node via the irq_domain_get_of_node accessor | |
131 | * @gc: Pointer to a list of generic chips. There is a helper function for | |
132 | * setting up one or more generic chips for interrupt controllers | |
133 | * drivers using the generic chip library which uses this pointer. | |
134 | * @dev: Pointer to a device that can be utilized for power management | |
135 | * purposes related to the irq domain. | |
136 | * @parent: Pointer to parent irq_domain to support hierarchy irq_domains | |
1aa0dd94 | 137 | * |
f876ea3b TG |
138 | * Revmap data, used internally by the irq domain code: |
139 | * @revmap_size: Size of the linear map table @revmap[] | |
140 | * @revmap_tree: Radix map tree for hwirqs that don't fit in the linear map | |
141 | * @revmap_mutex: Lock for the revmap | |
142 | * @revmap: Linear table of irq_data pointers | |
08a543ad GL |
143 | */ |
144 | struct irq_domain { | |
f876ea3b TG |
145 | struct list_head link; |
146 | const char *name; | |
147 | const struct irq_domain_ops *ops; | |
148 | void *host_data; | |
149 | unsigned int flags; | |
150 | unsigned int mapcount; | |
7bb69bad | 151 | |
1aa0dd94 | 152 | /* Optional data */ |
f876ea3b TG |
153 | struct fwnode_handle *fwnode; |
154 | enum irq_domain_bus_token bus_token; | |
155 | struct irq_domain_chip_generic *gc; | |
156 | struct device *dev; | |
f8264e34 | 157 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
f876ea3b | 158 | struct irq_domain *parent; |
f8264e34 | 159 | #endif |
cef5075c | 160 | |
1aa0dd94 | 161 | /* reverse map data. The linear map gets appended to the irq_domain */ |
f876ea3b TG |
162 | irq_hw_number_t hwirq_max; |
163 | unsigned int revmap_size; | |
164 | struct radix_tree_root revmap_tree; | |
165 | struct mutex revmap_mutex; | |
166 | struct irq_data __rcu *revmap[]; | |
08a543ad GL |
167 | }; |
168 | ||
f8264e34 JL |
169 | /* Irq domain flags */ |
170 | enum { | |
171 | /* Irq domain is hierarchical */ | |
172 | IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0), | |
173 | ||
6a6544e5 | 174 | /* Irq domain name was allocated in __irq_domain_add() */ |
2546287c | 175 | IRQ_DOMAIN_NAME_ALLOCATED = (1 << 1), |
36d72731 | 176 | |
0abefbaa QY |
177 | /* Irq domain is an IPI domain with virq per cpu */ |
178 | IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2), | |
179 | ||
180 | /* Irq domain is an IPI domain with single virq */ | |
181 | IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3), | |
182 | ||
631a9639 EA |
183 | /* Irq domain implements MSIs */ |
184 | IRQ_DOMAIN_FLAG_MSI = (1 << 4), | |
185 | ||
186 | /* Irq domain implements MSI remapping */ | |
187 | IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5), | |
188 | ||
4f86a06e | 189 | /* Irq domain doesn't translate anything */ |
3dad5f9a | 190 | IRQ_DOMAIN_FLAG_NO_MAP = (1 << 6), |
4f86a06e | 191 | |
f8264e34 JL |
192 | /* |
193 | * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved | |
194 | * for implementation specific purposes and ignored by the | |
195 | * core code. | |
196 | */ | |
197 | IRQ_DOMAIN_FLAG_NONCORE = (1 << 16), | |
198 | }; | |
199 | ||
10abc7df MZ |
200 | static inline struct device_node *irq_domain_get_of_node(struct irq_domain *d) |
201 | { | |
f110711a | 202 | return to_of_node(d->fwnode); |
10abc7df MZ |
203 | } |
204 | ||
1f8863bf MZ |
205 | static inline void irq_domain_set_pm_device(struct irq_domain *d, |
206 | struct device *dev) | |
207 | { | |
208 | if (d) | |
209 | d->dev = dev; | |
210 | } | |
211 | ||
7bb69bad | 212 | #ifdef CONFIG_IRQ_DOMAIN |
d59f6617 | 213 | struct fwnode_handle *__irq_domain_alloc_fwnode(unsigned int type, int id, |
b977fcf4 | 214 | const char *name, phys_addr_t *pa); |
d59f6617 TG |
215 | |
216 | enum { | |
217 | IRQCHIP_FWNODE_REAL, | |
218 | IRQCHIP_FWNODE_NAMED, | |
219 | IRQCHIP_FWNODE_NAMED_ID, | |
220 | }; | |
221 | ||
222 | static inline | |
223 | struct fwnode_handle *irq_domain_alloc_named_fwnode(const char *name) | |
224 | { | |
225 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED, 0, name, NULL); | |
226 | } | |
227 | ||
228 | static inline | |
229 | struct fwnode_handle *irq_domain_alloc_named_id_fwnode(const char *name, int id) | |
230 | { | |
231 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED_ID, id, name, | |
232 | NULL); | |
233 | } | |
234 | ||
b977fcf4 | 235 | static inline struct fwnode_handle *irq_domain_alloc_fwnode(phys_addr_t *pa) |
d59f6617 | 236 | { |
b977fcf4 | 237 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_REAL, 0, NULL, pa); |
d59f6617 TG |
238 | } |
239 | ||
b145dcc4 | 240 | void irq_domain_free_fwnode(struct fwnode_handle *fwnode); |
20c36ce2 | 241 | struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size, |
ddaf144c | 242 | irq_hw_number_t hwirq_max, int direct_max, |
fa40f377 GL |
243 | const struct irq_domain_ops *ops, |
244 | void *host_data); | |
67196fea AS |
245 | struct irq_domain *irq_domain_create_simple(struct fwnode_handle *fwnode, |
246 | unsigned int size, | |
247 | unsigned int first_irq, | |
248 | const struct irq_domain_ops *ops, | |
249 | void *host_data); | |
a8db8cf0 | 250 | struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, |
1bc04f2c GL |
251 | unsigned int size, |
252 | unsigned int first_irq, | |
253 | irq_hw_number_t first_hwirq, | |
a18dc81b | 254 | const struct irq_domain_ops *ops, |
a8db8cf0 | 255 | void *host_data); |
b6e95788 AS |
256 | struct irq_domain *irq_domain_create_legacy(struct fwnode_handle *fwnode, |
257 | unsigned int size, | |
258 | unsigned int first_irq, | |
259 | irq_hw_number_t first_hwirq, | |
260 | const struct irq_domain_ops *ops, | |
261 | void *host_data); | |
651e8b54 | 262 | extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec, |
130b8c6c | 263 | enum irq_domain_bus_token bus_token); |
c7b41f0a | 264 | extern bool irq_domain_check_msi_remap(void); |
fa40f377 | 265 | extern void irq_set_default_host(struct irq_domain *host); |
9f199dd3 | 266 | extern struct irq_domain *irq_get_default_host(void); |
ac0a0cd2 | 267 | extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, |
06ee6d57 | 268 | irq_hw_number_t hwirq, int node, |
bec04037 | 269 | const struct irq_affinity_desc *affinity); |
fa40f377 | 270 | |
1bf4ddc4 MZ |
271 | static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) |
272 | { | |
273 | return node ? &node->fwnode : NULL; | |
274 | } | |
275 | ||
db3e50f3 SA |
276 | extern const struct fwnode_operations irqchip_fwnode_ops; |
277 | ||
75aba7b0 SS |
278 | static inline bool is_fwnode_irqchip(struct fwnode_handle *fwnode) |
279 | { | |
db3e50f3 | 280 | return fwnode && fwnode->ops == &irqchip_fwnode_ops; |
75aba7b0 SS |
281 | } |
282 | ||
61d0a000 MZ |
283 | extern void irq_domain_update_bus_token(struct irq_domain *domain, |
284 | enum irq_domain_bus_token bus_token); | |
285 | ||
651e8b54 MZ |
286 | static inline |
287 | struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, | |
288 | enum irq_domain_bus_token bus_token) | |
289 | { | |
290 | struct irq_fwspec fwspec = { | |
291 | .fwnode = fwnode, | |
292 | }; | |
293 | ||
294 | return irq_find_matching_fwspec(&fwspec, bus_token); | |
295 | } | |
296 | ||
130b8c6c MZ |
297 | static inline struct irq_domain *irq_find_matching_host(struct device_node *node, |
298 | enum irq_domain_bus_token bus_token) | |
299 | { | |
1bf4ddc4 | 300 | return irq_find_matching_fwnode(of_node_to_fwnode(node), bus_token); |
130b8c6c MZ |
301 | } |
302 | ||
ad3aedfb MZ |
303 | static inline struct irq_domain *irq_find_host(struct device_node *node) |
304 | { | |
64619343 MZ |
305 | struct irq_domain *d; |
306 | ||
307 | d = irq_find_matching_host(node, DOMAIN_BUS_WIRED); | |
308 | if (!d) | |
309 | d = irq_find_matching_host(node, DOMAIN_BUS_ANY); | |
310 | ||
311 | return d; | |
ad3aedfb MZ |
312 | } |
313 | ||
67196fea AS |
314 | static inline struct irq_domain *irq_domain_add_simple(struct device_node *of_node, |
315 | unsigned int size, | |
316 | unsigned int first_irq, | |
317 | const struct irq_domain_ops *ops, | |
318 | void *host_data) | |
319 | { | |
320 | return irq_domain_create_simple(of_node_to_fwnode(of_node), size, first_irq, ops, host_data); | |
321 | } | |
322 | ||
fa40f377 GL |
323 | /** |
324 | * irq_domain_add_linear() - Allocate and register a linear revmap irq_domain. | |
325 | * @of_node: pointer to interrupt controller's device tree node. | |
326 | * @size: Number of interrupts in the domain. | |
327 | * @ops: map/unmap domain callbacks | |
328 | * @host_data: Controller private data pointer | |
329 | */ | |
330 | static inline struct irq_domain *irq_domain_add_linear(struct device_node *of_node, | |
a8db8cf0 | 331 | unsigned int size, |
a18dc81b | 332 | const struct irq_domain_ops *ops, |
fa40f377 GL |
333 | void *host_data) |
334 | { | |
1bf4ddc4 | 335 | return __irq_domain_add(of_node_to_fwnode(of_node), size, size, 0, ops, host_data); |
fa40f377 | 336 | } |
e37af801 MZ |
337 | |
338 | #ifdef CONFIG_IRQ_DOMAIN_NOMAP | |
fa40f377 | 339 | static inline struct irq_domain *irq_domain_add_nomap(struct device_node *of_node, |
6fa6c8e2 | 340 | unsigned int max_irq, |
a18dc81b | 341 | const struct irq_domain_ops *ops, |
fa40f377 GL |
342 | void *host_data) |
343 | { | |
1bf4ddc4 | 344 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, max_irq, max_irq, ops, host_data); |
fa40f377 | 345 | } |
e37af801 MZ |
346 | |
347 | extern unsigned int irq_create_direct_mapping(struct irq_domain *host); | |
348 | #endif | |
349 | ||
cef5075c GL |
350 | static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_node, |
351 | const struct irq_domain_ops *ops, | |
352 | void *host_data) | |
353 | { | |
1bf4ddc4 MZ |
354 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, ~0, 0, ops, host_data); |
355 | } | |
356 | ||
357 | static inline struct irq_domain *irq_domain_create_linear(struct fwnode_handle *fwnode, | |
358 | unsigned int size, | |
359 | const struct irq_domain_ops *ops, | |
360 | void *host_data) | |
361 | { | |
362 | return __irq_domain_add(fwnode, size, size, 0, ops, host_data); | |
363 | } | |
364 | ||
365 | static inline struct irq_domain *irq_domain_create_tree(struct fwnode_handle *fwnode, | |
366 | const struct irq_domain_ops *ops, | |
367 | void *host_data) | |
368 | { | |
369 | return __irq_domain_add(fwnode, 0, ~0, 0, ops, host_data); | |
cef5075c | 370 | } |
58ee99ad PM |
371 | |
372 | extern void irq_domain_remove(struct irq_domain *host); | |
373 | ||
ddaf144c GL |
374 | extern int irq_domain_associate(struct irq_domain *domain, unsigned int irq, |
375 | irq_hw_number_t hwirq); | |
376 | extern void irq_domain_associate_many(struct irq_domain *domain, | |
377 | unsigned int irq_base, | |
378 | irq_hw_number_t hwirq_base, int count); | |
98aa468e | 379 | |
bb4c6910 LV |
380 | extern unsigned int irq_create_mapping_affinity(struct irq_domain *host, |
381 | irq_hw_number_t hwirq, | |
382 | const struct irq_affinity_desc *affinity); | |
c0131f09 | 383 | extern unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec); |
cc79ca69 | 384 | extern void irq_dispose_mapping(unsigned int virq); |
d3dcb436 | 385 | |
bb4c6910 LV |
386 | static inline unsigned int irq_create_mapping(struct irq_domain *host, |
387 | irq_hw_number_t hwirq) | |
388 | { | |
389 | return irq_create_mapping_affinity(host, hwirq, NULL); | |
390 | } | |
391 | ||
d22558dd MZ |
392 | extern struct irq_desc *__irq_resolve_mapping(struct irq_domain *domain, |
393 | irq_hw_number_t hwirq, | |
394 | unsigned int *irq); | |
395 | ||
396 | static inline struct irq_desc *irq_resolve_mapping(struct irq_domain *domain, | |
397 | irq_hw_number_t hwirq) | |
398 | { | |
399 | return __irq_resolve_mapping(domain, hwirq, NULL); | |
400 | } | |
401 | ||
d3dcb436 | 402 | /** |
1da02736 | 403 | * irq_find_mapping() - Find a linux irq from a hw irq number. |
d3dcb436 GL |
404 | * @domain: domain owning this hardware interrupt |
405 | * @hwirq: hardware irq number in that domain space | |
d3dcb436 | 406 | */ |
d22558dd MZ |
407 | static inline unsigned int irq_find_mapping(struct irq_domain *domain, |
408 | irq_hw_number_t hwirq) | |
409 | { | |
410 | unsigned int irq; | |
411 | ||
412 | if (__irq_resolve_mapping(domain, hwirq, &irq)) | |
413 | return irq; | |
414 | ||
415 | return 0; | |
416 | } | |
1da02736 | 417 | |
d3dcb436 GL |
418 | static inline unsigned int irq_linear_revmap(struct irq_domain *domain, |
419 | irq_hw_number_t hwirq) | |
420 | { | |
1da02736 | 421 | return irq_find_mapping(domain, hwirq); |
d3dcb436 | 422 | } |
1da02736 | 423 | |
a18dc81b | 424 | extern const struct irq_domain_ops irq_domain_simple_ops; |
16b2e6e2 GL |
425 | |
426 | /* stock xlate functions */ | |
427 | int irq_domain_xlate_onecell(struct irq_domain *d, struct device_node *ctrlr, | |
428 | const u32 *intspec, unsigned int intsize, | |
429 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
430 | int irq_domain_xlate_twocell(struct irq_domain *d, struct device_node *ctrlr, | |
431 | const u32 *intspec, unsigned int intsize, | |
432 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
433 | int irq_domain_xlate_onetwocell(struct irq_domain *d, struct device_node *ctrlr, | |
434 | const u32 *intspec, unsigned int intsize, | |
435 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
436 | ||
b5c231d8 BM |
437 | int irq_domain_translate_twocell(struct irq_domain *d, |
438 | struct irq_fwspec *fwspec, | |
439 | unsigned long *out_hwirq, | |
440 | unsigned int *out_type); | |
441 | ||
b01eccea YS |
442 | int irq_domain_translate_onecell(struct irq_domain *d, |
443 | struct irq_fwspec *fwspec, | |
444 | unsigned long *out_hwirq, | |
445 | unsigned int *out_type); | |
446 | ||
d17bf24e | 447 | /* IPI functions */ |
7cec18a3 MR |
448 | int irq_reserve_ipi(struct irq_domain *domain, const struct cpumask *dest); |
449 | int irq_destroy_ipi(unsigned int irq, const struct cpumask *dest); | |
d17bf24e | 450 | |
f8264e34 JL |
451 | /* V2 interfaces to support hierarchy IRQ domains. */ |
452 | extern struct irq_data *irq_domain_get_irq_data(struct irq_domain *domain, | |
453 | unsigned int virq); | |
5f22f5c6 | 454 | extern void irq_domain_set_info(struct irq_domain *domain, unsigned int virq, |
45ec846c MZ |
455 | irq_hw_number_t hwirq, |
456 | const struct irq_chip *chip, | |
5f22f5c6 SA |
457 | void *chip_data, irq_flow_handler_t handler, |
458 | void *handler_data, const char *handler_name); | |
5c8f77a2 | 459 | extern void irq_domain_reset_irq_data(struct irq_data *irq_data); |
f8264e34 | 460 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
2a5e9a07 | 461 | extern struct irq_domain *irq_domain_create_hierarchy(struct irq_domain *parent, |
afb7da83 | 462 | unsigned int flags, unsigned int size, |
2a5e9a07 | 463 | struct fwnode_handle *fwnode, |
afb7da83 | 464 | const struct irq_domain_ops *ops, void *host_data); |
2a5e9a07 MZ |
465 | |
466 | static inline struct irq_domain *irq_domain_add_hierarchy(struct irq_domain *parent, | |
467 | unsigned int flags, | |
468 | unsigned int size, | |
469 | struct device_node *node, | |
470 | const struct irq_domain_ops *ops, | |
471 | void *host_data) | |
472 | { | |
473 | return irq_domain_create_hierarchy(parent, flags, size, | |
474 | of_node_to_fwnode(node), | |
475 | ops, host_data); | |
476 | } | |
477 | ||
f8264e34 JL |
478 | extern int __irq_domain_alloc_irqs(struct irq_domain *domain, int irq_base, |
479 | unsigned int nr_irqs, int node, void *arg, | |
bec04037 DL |
480 | bool realloc, |
481 | const struct irq_affinity_desc *affinity); | |
f8264e34 | 482 | extern void irq_domain_free_irqs(unsigned int virq, unsigned int nr_irqs); |
42e1cc2d | 483 | extern int irq_domain_activate_irq(struct irq_data *irq_data, bool early); |
f8264e34 JL |
484 | extern void irq_domain_deactivate_irq(struct irq_data *irq_data); |
485 | ||
486 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, | |
487 | unsigned int nr_irqs, int node, void *arg) | |
488 | { | |
06ee6d57 TG |
489 | return __irq_domain_alloc_irqs(domain, -1, nr_irqs, node, arg, false, |
490 | NULL); | |
f8264e34 JL |
491 | } |
492 | ||
6a6544e5 | 493 | extern int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain, |
c466595c MZ |
494 | unsigned int irq_base, |
495 | unsigned int nr_irqs, void *arg); | |
f8264e34 JL |
496 | extern int irq_domain_set_hwirq_and_chip(struct irq_domain *domain, |
497 | unsigned int virq, | |
498 | irq_hw_number_t hwirq, | |
45ec846c | 499 | const struct irq_chip *chip, |
f8264e34 | 500 | void *chip_data); |
f8264e34 JL |
501 | extern void irq_domain_free_irqs_common(struct irq_domain *domain, |
502 | unsigned int virq, | |
503 | unsigned int nr_irqs); | |
504 | extern void irq_domain_free_irqs_top(struct irq_domain *domain, | |
505 | unsigned int virq, unsigned int nr_irqs); | |
506 | ||
495c38d3 DD |
507 | extern int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg); |
508 | extern int irq_domain_pop_irq(struct irq_domain *domain, int virq); | |
509 | ||
36d72731 JL |
510 | extern int irq_domain_alloc_irqs_parent(struct irq_domain *domain, |
511 | unsigned int irq_base, | |
512 | unsigned int nr_irqs, void *arg); | |
f8264e34 | 513 | |
36d72731 JL |
514 | extern void irq_domain_free_irqs_parent(struct irq_domain *domain, |
515 | unsigned int irq_base, | |
516 | unsigned int nr_irqs); | |
f8264e34 | 517 | |
55567976 MZ |
518 | extern int irq_domain_disconnect_hierarchy(struct irq_domain *domain, |
519 | unsigned int virq); | |
520 | ||
f8264e34 JL |
521 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
522 | { | |
523 | return domain->flags & IRQ_DOMAIN_FLAG_HIERARCHY; | |
524 | } | |
0abefbaa QY |
525 | |
526 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
527 | { | |
528 | return domain->flags & | |
529 | (IRQ_DOMAIN_FLAG_IPI_PER_CPU | IRQ_DOMAIN_FLAG_IPI_SINGLE); | |
530 | } | |
531 | ||
532 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
533 | { | |
534 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_PER_CPU; | |
535 | } | |
536 | ||
537 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
538 | { | |
539 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE; | |
540 | } | |
631a9639 EA |
541 | |
542 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
543 | { | |
544 | return domain->flags & IRQ_DOMAIN_FLAG_MSI; | |
545 | } | |
546 | ||
547 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
548 | { | |
549 | return domain->flags & IRQ_DOMAIN_FLAG_MSI_REMAP; | |
550 | } | |
551 | ||
552 | extern bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain); | |
553 | ||
f8264e34 | 554 | #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
f8264e34 JL |
555 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, |
556 | unsigned int nr_irqs, int node, void *arg) | |
557 | { | |
558 | return -1; | |
559 | } | |
560 | ||
1e2a7d78 JH |
561 | static inline void irq_domain_free_irqs(unsigned int virq, |
562 | unsigned int nr_irqs) { } | |
563 | ||
f8264e34 JL |
564 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
565 | { | |
566 | return false; | |
567 | } | |
0abefbaa QY |
568 | |
569 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
570 | { | |
571 | return false; | |
572 | } | |
573 | ||
574 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
575 | { | |
576 | return false; | |
577 | } | |
578 | ||
579 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
580 | { | |
581 | return false; | |
582 | } | |
631a9639 EA |
583 | |
584 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
585 | { | |
586 | return false; | |
587 | } | |
588 | ||
589 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
590 | { | |
591 | return false; | |
592 | } | |
593 | ||
594 | static inline bool | |
595 | irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain) | |
596 | { | |
597 | return false; | |
598 | } | |
f8264e34 JL |
599 | #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
600 | ||
d593f25f GL |
601 | #else /* CONFIG_IRQ_DOMAIN */ |
602 | static inline void irq_dispose_mapping(unsigned int virq) { } | |
471036b2 SS |
603 | static inline struct irq_domain *irq_find_matching_fwnode( |
604 | struct fwnode_handle *fwnode, enum irq_domain_bus_token bus_token) | |
605 | { | |
606 | return NULL; | |
607 | } | |
b3e22847 MYK |
608 | static inline bool irq_domain_check_msi_remap(void) |
609 | { | |
610 | return false; | |
611 | } | |
d593f25f | 612 | #endif /* !CONFIG_IRQ_DOMAIN */ |
7e713301 | 613 | |
08a543ad | 614 | #endif /* _LINUX_IRQDOMAIN_H */ |