Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
08a543ad GL |
2 | /* |
3 | * irq_domain - IRQ translation domains | |
4 | * | |
5 | * Translation infrastructure between hw and linux irq numbers. This is | |
6 | * helpful for interrupt controllers to implement mapping between hardware | |
7 | * irq numbers and the Linux irq number space. | |
8 | * | |
e7a46c81 MZ |
9 | * irq_domains also have hooks for translating device tree or other |
10 | * firmware interrupt representations into a hardware irq number that | |
11 | * can be mapped back to a Linux irq number without any extra platform | |
12 | * support code. | |
08a543ad | 13 | * |
7bb69bad GL |
14 | * Interrupt controller "domain" data structure. This could be defined as a |
15 | * irq domain controller. That is, it handles the mapping between hardware | |
16 | * and virtual interrupt numbers for a given interrupt domain. The domain | |
17 | * structure is generally created by the PIC code for a given PIC instance | |
18 | * (though a domain can cover more than one PIC if they have a flat number | |
19 | * model). It's the domain callbacks that are responsible for setting the | |
20 | * irq_chip on a given irq_desc after it's been mapped. | |
cc79ca69 | 21 | * |
e7a46c81 MZ |
22 | * The host code and data structures use a fwnode_handle pointer to |
23 | * identify the domain. In some cases, and in order to preserve source | |
24 | * code compatibility, this fwnode pointer is "upgraded" to a DT | |
25 | * device_node. For those firmware infrastructures that do not provide | |
26 | * a unique identifier for an interrupt controller, the irq_domain | |
27 | * code offers a fwnode allocator. | |
08a543ad | 28 | */ |
7bb69bad | 29 | |
08a543ad GL |
30 | #ifndef _LINUX_IRQDOMAIN_H |
31 | #define _LINUX_IRQDOMAIN_H | |
32 | ||
7bb69bad | 33 | #include <linux/types.h> |
1b537708 | 34 | #include <linux/irqhandler.h> |
f110711a | 35 | #include <linux/of.h> |
f1d78358 | 36 | #include <linux/mutex.h> |
7bb69bad | 37 | #include <linux/radix-tree.h> |
08a543ad | 38 | |
08a543ad | 39 | struct device_node; |
08219fb1 | 40 | struct fwnode_handle; |
08a543ad | 41 | struct irq_domain; |
f8264e34 JL |
42 | struct irq_chip; |
43 | struct irq_data; | |
d22558dd | 44 | struct irq_desc; |
06ee6d57 | 45 | struct cpumask; |
c3e7239a | 46 | struct seq_file; |
bec04037 | 47 | struct irq_affinity_desc; |
7bb69bad | 48 | |
11e4438e MZ |
49 | #define IRQ_DOMAIN_IRQ_SPEC_PARAMS 16 |
50 | ||
51 | /** | |
52 | * struct irq_fwspec - generic IRQ specifier structure | |
53 | * | |
54 | * @fwnode: Pointer to a firmware-specific descriptor | |
55 | * @param_count: Number of device-specific parameters | |
56 | * @param: Device-specific parameters | |
57 | * | |
58 | * This structure, directly modeled after of_phandle_args, is used to | |
59 | * pass a device-specific description of an interrupt. | |
60 | */ | |
61 | struct irq_fwspec { | |
62 | struct fwnode_handle *fwnode; | |
63 | int param_count; | |
64 | u32 param[IRQ_DOMAIN_IRQ_SPEC_PARAMS]; | |
65 | }; | |
66 | ||
0ab8d0f6 MZ |
67 | /* Conversion function from of_phandle_args fields to fwspec */ |
68 | void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, | |
69 | unsigned int count, struct irq_fwspec *fwspec); | |
70 | ||
ad3aedfb MZ |
71 | /* |
72 | * Should several domains have the same device node, but serve | |
73 | * different purposes (for example one domain is for PCI/MSI, and the | |
74 | * other for wired IRQs), they can be distinguished using a | |
75 | * bus-specific token. Most domains are expected to only carry | |
76 | * DOMAIN_BUS_ANY. | |
77 | */ | |
78 | enum irq_domain_bus_token { | |
79 | DOMAIN_BUS_ANY = 0, | |
530cbe10 | 80 | DOMAIN_BUS_WIRED, |
61ce8d8d | 81 | DOMAIN_BUS_GENERIC_MSI, |
0380839d | 82 | DOMAIN_BUS_PCI_MSI, |
c706c239 | 83 | DOMAIN_BUS_PLATFORM_MSI, |
a5716070 | 84 | DOMAIN_BUS_NEXUS, |
29d5c8db | 85 | DOMAIN_BUS_IPI, |
9b1b282c | 86 | DOMAIN_BUS_FSL_MC_MSI, |
49b32315 | 87 | DOMAIN_BUS_TI_SCI_INTA_MSI, |
d46bca2b | 88 | DOMAIN_BUS_WAKEUP, |
c6c9e283 | 89 | DOMAIN_BUS_VMD_MSI, |
ad3aedfb MZ |
90 | }; |
91 | ||
08a543ad GL |
92 | /** |
93 | * struct irq_domain_ops - Methods for irq_domain objects | |
7bb69bad GL |
94 | * @match: Match an interrupt controller device node to a host, returns |
95 | * 1 on a match | |
96 | * @map: Create or update a mapping between a virtual irq number and a hw | |
97 | * irq number. This is called only once for a given mapping. | |
98 | * @unmap: Dispose of such a mapping | |
7bb69bad GL |
99 | * @xlate: Given a device tree node and interrupt specifier, decode |
100 | * the hardware irq number and linux irq type value. | |
101 | * | |
102 | * Functions below are provided by the driver and called whenever a new mapping | |
103 | * is created or an old mapping is disposed. The driver can then proceed to | |
104 | * whatever internal data structures management is required. It also needs | |
105 | * to setup the irq_desc when returning from map(). | |
08a543ad GL |
106 | */ |
107 | struct irq_domain_ops { | |
ad3aedfb MZ |
108 | int (*match)(struct irq_domain *d, struct device_node *node, |
109 | enum irq_domain_bus_token bus_token); | |
651e8b54 MZ |
110 | int (*select)(struct irq_domain *d, struct irq_fwspec *fwspec, |
111 | enum irq_domain_bus_token bus_token); | |
7bb69bad GL |
112 | int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw); |
113 | void (*unmap)(struct irq_domain *d, unsigned int virq); | |
7bb69bad GL |
114 | int (*xlate)(struct irq_domain *d, struct device_node *node, |
115 | const u32 *intspec, unsigned int intsize, | |
116 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 JL |
117 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
118 | /* extended V2 interfaces to support hierarchy irq_domains */ | |
119 | int (*alloc)(struct irq_domain *d, unsigned int virq, | |
120 | unsigned int nr_irqs, void *arg); | |
121 | void (*free)(struct irq_domain *d, unsigned int virq, | |
122 | unsigned int nr_irqs); | |
702cb0a0 | 123 | int (*activate)(struct irq_domain *d, struct irq_data *irqd, bool reserve); |
f8264e34 | 124 | void (*deactivate)(struct irq_domain *d, struct irq_data *irq_data); |
11e4438e MZ |
125 | int (*translate)(struct irq_domain *d, struct irq_fwspec *fwspec, |
126 | unsigned long *out_hwirq, unsigned int *out_type); | |
f8264e34 | 127 | #endif |
c3e7239a TG |
128 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
129 | void (*debug_show)(struct seq_file *m, struct irq_domain *d, | |
130 | struct irq_data *irqd, int ind); | |
131 | #endif | |
08a543ad GL |
132 | }; |
133 | ||
4946f15e | 134 | extern const struct irq_domain_ops irq_generic_chip_ops; |
088f40b7 TG |
135 | |
136 | struct irq_domain_chip_generic; | |
137 | ||
08a543ad GL |
138 | /** |
139 | * struct irq_domain - Hardware interrupt number translation object | |
7bb69bad | 140 | * @link: Element in global irq_domain list. |
1aa0dd94 | 141 | * @name: Name of interrupt domain |
7bb69bad GL |
142 | * @ops: pointer to irq_domain methods |
143 | * @host_data: private data pointer for use by owner. Not touched by irq_domain | |
144 | * core code. | |
f8264e34 | 145 | * @flags: host per irq_domain flags |
9dc6be3d | 146 | * @mapcount: The number of mapped interrupts |
1aa0dd94 GL |
147 | * |
148 | * Optional elements | |
4b821300 DL |
149 | * @fwnode: Pointer to firmware node associated with the irq_domain. Pretty easy |
150 | * to swap it for the of_node via the irq_domain_get_of_node accessor | |
1aa0dd94 GL |
151 | * @gc: Pointer to a list of generic chips. There is a helper function for |
152 | * setting up one or more generic chips for interrupt controllers | |
153 | * drivers using the generic chip library which uses this pointer. | |
1f8863bf MZ |
154 | * @dev: Pointer to a device that the domain represent, and that will be |
155 | * used for power management purposes. | |
f8264e34 | 156 | * @parent: Pointer to parent irq_domain to support hierarchy irq_domains |
1aa0dd94 GL |
157 | * |
158 | * Revmap data, used internally by irq_domain | |
1da02736 | 159 | * @revmap_size: Size of the linear map table @revmap[] |
1aa0dd94 | 160 | * @revmap_tree: Radix map tree for hwirqs that don't fit in the linear map |
d4a45c68 | 161 | * @revmap_mutex: Lock for the revmap |
48b15a79 | 162 | * @revmap: Linear table of irq_data pointers |
08a543ad GL |
163 | */ |
164 | struct irq_domain { | |
7bb69bad | 165 | struct list_head link; |
0bb4afb4 | 166 | const char *name; |
a18dc81b | 167 | const struct irq_domain_ops *ops; |
7bb69bad | 168 | void *host_data; |
f8264e34 | 169 | unsigned int flags; |
9dc6be3d | 170 | unsigned int mapcount; |
7bb69bad | 171 | |
1aa0dd94 | 172 | /* Optional data */ |
f110711a | 173 | struct fwnode_handle *fwnode; |
ad3aedfb | 174 | enum irq_domain_bus_token bus_token; |
088f40b7 | 175 | struct irq_domain_chip_generic *gc; |
1f8863bf | 176 | struct device *dev; |
f8264e34 JL |
177 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
178 | struct irq_domain *parent; | |
179 | #endif | |
cef5075c | 180 | |
1aa0dd94 | 181 | /* reverse map data. The linear map gets appended to the irq_domain */ |
ddaf144c | 182 | irq_hw_number_t hwirq_max; |
1aa0dd94 GL |
183 | unsigned int revmap_size; |
184 | struct radix_tree_root revmap_tree; | |
d4a45c68 MZ |
185 | struct mutex revmap_mutex; |
186 | struct irq_data __rcu *revmap[]; | |
08a543ad GL |
187 | }; |
188 | ||
f8264e34 JL |
189 | /* Irq domain flags */ |
190 | enum { | |
191 | /* Irq domain is hierarchical */ | |
192 | IRQ_DOMAIN_FLAG_HIERARCHY = (1 << 0), | |
193 | ||
6a6544e5 | 194 | /* Irq domain name was allocated in __irq_domain_add() */ |
2546287c | 195 | IRQ_DOMAIN_NAME_ALLOCATED = (1 << 1), |
36d72731 | 196 | |
0abefbaa QY |
197 | /* Irq domain is an IPI domain with virq per cpu */ |
198 | IRQ_DOMAIN_FLAG_IPI_PER_CPU = (1 << 2), | |
199 | ||
200 | /* Irq domain is an IPI domain with single virq */ | |
201 | IRQ_DOMAIN_FLAG_IPI_SINGLE = (1 << 3), | |
202 | ||
631a9639 EA |
203 | /* Irq domain implements MSIs */ |
204 | IRQ_DOMAIN_FLAG_MSI = (1 << 4), | |
205 | ||
206 | /* Irq domain implements MSI remapping */ | |
207 | IRQ_DOMAIN_FLAG_MSI_REMAP = (1 << 5), | |
208 | ||
6f1a4891 TG |
209 | /* |
210 | * Quirk to handle MSI implementations which do not provide | |
211 | * masking. Currently known to affect x86, but partially | |
212 | * handled in core code. | |
213 | */ | |
214 | IRQ_DOMAIN_MSI_NOMASK_QUIRK = (1 << 6), | |
215 | ||
4f86a06e MZ |
216 | /* Irq domain doesn't translate anything */ |
217 | IRQ_DOMAIN_FLAG_NO_MAP = (1 << 7), | |
218 | ||
f8264e34 JL |
219 | /* |
220 | * Flags starting from IRQ_DOMAIN_FLAG_NONCORE are reserved | |
221 | * for implementation specific purposes and ignored by the | |
222 | * core code. | |
223 | */ | |
224 | IRQ_DOMAIN_FLAG_NONCORE = (1 << 16), | |
225 | }; | |
226 | ||
10abc7df MZ |
227 | static inline struct device_node *irq_domain_get_of_node(struct irq_domain *d) |
228 | { | |
f110711a | 229 | return to_of_node(d->fwnode); |
10abc7df MZ |
230 | } |
231 | ||
1f8863bf MZ |
232 | static inline void irq_domain_set_pm_device(struct irq_domain *d, |
233 | struct device *dev) | |
234 | { | |
235 | if (d) | |
236 | d->dev = dev; | |
237 | } | |
238 | ||
7bb69bad | 239 | #ifdef CONFIG_IRQ_DOMAIN |
d59f6617 | 240 | struct fwnode_handle *__irq_domain_alloc_fwnode(unsigned int type, int id, |
b977fcf4 | 241 | const char *name, phys_addr_t *pa); |
d59f6617 TG |
242 | |
243 | enum { | |
244 | IRQCHIP_FWNODE_REAL, | |
245 | IRQCHIP_FWNODE_NAMED, | |
246 | IRQCHIP_FWNODE_NAMED_ID, | |
247 | }; | |
248 | ||
249 | static inline | |
250 | struct fwnode_handle *irq_domain_alloc_named_fwnode(const char *name) | |
251 | { | |
252 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED, 0, name, NULL); | |
253 | } | |
254 | ||
255 | static inline | |
256 | struct fwnode_handle *irq_domain_alloc_named_id_fwnode(const char *name, int id) | |
257 | { | |
258 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_NAMED_ID, id, name, | |
259 | NULL); | |
260 | } | |
261 | ||
b977fcf4 | 262 | static inline struct fwnode_handle *irq_domain_alloc_fwnode(phys_addr_t *pa) |
d59f6617 | 263 | { |
b977fcf4 | 264 | return __irq_domain_alloc_fwnode(IRQCHIP_FWNODE_REAL, 0, NULL, pa); |
d59f6617 TG |
265 | } |
266 | ||
b145dcc4 | 267 | void irq_domain_free_fwnode(struct fwnode_handle *fwnode); |
20c36ce2 | 268 | struct irq_domain *__irq_domain_add(struct fwnode_handle *fwnode, unsigned int size, |
ddaf144c | 269 | irq_hw_number_t hwirq_max, int direct_max, |
fa40f377 GL |
270 | const struct irq_domain_ops *ops, |
271 | void *host_data); | |
67196fea AS |
272 | struct irq_domain *irq_domain_create_simple(struct fwnode_handle *fwnode, |
273 | unsigned int size, | |
274 | unsigned int first_irq, | |
275 | const struct irq_domain_ops *ops, | |
276 | void *host_data); | |
a8db8cf0 | 277 | struct irq_domain *irq_domain_add_legacy(struct device_node *of_node, |
1bc04f2c GL |
278 | unsigned int size, |
279 | unsigned int first_irq, | |
280 | irq_hw_number_t first_hwirq, | |
a18dc81b | 281 | const struct irq_domain_ops *ops, |
a8db8cf0 | 282 | void *host_data); |
b6e95788 AS |
283 | struct irq_domain *irq_domain_create_legacy(struct fwnode_handle *fwnode, |
284 | unsigned int size, | |
285 | unsigned int first_irq, | |
286 | irq_hw_number_t first_hwirq, | |
287 | const struct irq_domain_ops *ops, | |
288 | void *host_data); | |
651e8b54 | 289 | extern struct irq_domain *irq_find_matching_fwspec(struct irq_fwspec *fwspec, |
130b8c6c | 290 | enum irq_domain_bus_token bus_token); |
c7b41f0a | 291 | extern bool irq_domain_check_msi_remap(void); |
fa40f377 | 292 | extern void irq_set_default_host(struct irq_domain *host); |
9f199dd3 | 293 | extern struct irq_domain *irq_get_default_host(void); |
ac0a0cd2 | 294 | extern int irq_domain_alloc_descs(int virq, unsigned int nr_irqs, |
06ee6d57 | 295 | irq_hw_number_t hwirq, int node, |
bec04037 | 296 | const struct irq_affinity_desc *affinity); |
fa40f377 | 297 | |
1bf4ddc4 MZ |
298 | static inline struct fwnode_handle *of_node_to_fwnode(struct device_node *node) |
299 | { | |
300 | return node ? &node->fwnode : NULL; | |
301 | } | |
302 | ||
db3e50f3 SA |
303 | extern const struct fwnode_operations irqchip_fwnode_ops; |
304 | ||
75aba7b0 SS |
305 | static inline bool is_fwnode_irqchip(struct fwnode_handle *fwnode) |
306 | { | |
db3e50f3 | 307 | return fwnode && fwnode->ops == &irqchip_fwnode_ops; |
75aba7b0 SS |
308 | } |
309 | ||
61d0a000 MZ |
310 | extern void irq_domain_update_bus_token(struct irq_domain *domain, |
311 | enum irq_domain_bus_token bus_token); | |
312 | ||
651e8b54 MZ |
313 | static inline |
314 | struct irq_domain *irq_find_matching_fwnode(struct fwnode_handle *fwnode, | |
315 | enum irq_domain_bus_token bus_token) | |
316 | { | |
317 | struct irq_fwspec fwspec = { | |
318 | .fwnode = fwnode, | |
319 | }; | |
320 | ||
321 | return irq_find_matching_fwspec(&fwspec, bus_token); | |
322 | } | |
323 | ||
130b8c6c MZ |
324 | static inline struct irq_domain *irq_find_matching_host(struct device_node *node, |
325 | enum irq_domain_bus_token bus_token) | |
326 | { | |
1bf4ddc4 | 327 | return irq_find_matching_fwnode(of_node_to_fwnode(node), bus_token); |
130b8c6c MZ |
328 | } |
329 | ||
ad3aedfb MZ |
330 | static inline struct irq_domain *irq_find_host(struct device_node *node) |
331 | { | |
64619343 MZ |
332 | struct irq_domain *d; |
333 | ||
334 | d = irq_find_matching_host(node, DOMAIN_BUS_WIRED); | |
335 | if (!d) | |
336 | d = irq_find_matching_host(node, DOMAIN_BUS_ANY); | |
337 | ||
338 | return d; | |
ad3aedfb MZ |
339 | } |
340 | ||
67196fea AS |
341 | static inline struct irq_domain *irq_domain_add_simple(struct device_node *of_node, |
342 | unsigned int size, | |
343 | unsigned int first_irq, | |
344 | const struct irq_domain_ops *ops, | |
345 | void *host_data) | |
346 | { | |
347 | return irq_domain_create_simple(of_node_to_fwnode(of_node), size, first_irq, ops, host_data); | |
348 | } | |
349 | ||
fa40f377 GL |
350 | /** |
351 | * irq_domain_add_linear() - Allocate and register a linear revmap irq_domain. | |
352 | * @of_node: pointer to interrupt controller's device tree node. | |
353 | * @size: Number of interrupts in the domain. | |
354 | * @ops: map/unmap domain callbacks | |
355 | * @host_data: Controller private data pointer | |
356 | */ | |
357 | static inline struct irq_domain *irq_domain_add_linear(struct device_node *of_node, | |
a8db8cf0 | 358 | unsigned int size, |
a18dc81b | 359 | const struct irq_domain_ops *ops, |
fa40f377 GL |
360 | void *host_data) |
361 | { | |
1bf4ddc4 | 362 | return __irq_domain_add(of_node_to_fwnode(of_node), size, size, 0, ops, host_data); |
fa40f377 | 363 | } |
e37af801 MZ |
364 | |
365 | #ifdef CONFIG_IRQ_DOMAIN_NOMAP | |
fa40f377 | 366 | static inline struct irq_domain *irq_domain_add_nomap(struct device_node *of_node, |
6fa6c8e2 | 367 | unsigned int max_irq, |
a18dc81b | 368 | const struct irq_domain_ops *ops, |
fa40f377 GL |
369 | void *host_data) |
370 | { | |
1bf4ddc4 | 371 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, max_irq, max_irq, ops, host_data); |
fa40f377 | 372 | } |
e37af801 MZ |
373 | |
374 | extern unsigned int irq_create_direct_mapping(struct irq_domain *host); | |
375 | #endif | |
376 | ||
cef5075c GL |
377 | static inline struct irq_domain *irq_domain_add_tree(struct device_node *of_node, |
378 | const struct irq_domain_ops *ops, | |
379 | void *host_data) | |
380 | { | |
1bf4ddc4 MZ |
381 | return __irq_domain_add(of_node_to_fwnode(of_node), 0, ~0, 0, ops, host_data); |
382 | } | |
383 | ||
384 | static inline struct irq_domain *irq_domain_create_linear(struct fwnode_handle *fwnode, | |
385 | unsigned int size, | |
386 | const struct irq_domain_ops *ops, | |
387 | void *host_data) | |
388 | { | |
389 | return __irq_domain_add(fwnode, size, size, 0, ops, host_data); | |
390 | } | |
391 | ||
392 | static inline struct irq_domain *irq_domain_create_tree(struct fwnode_handle *fwnode, | |
393 | const struct irq_domain_ops *ops, | |
394 | void *host_data) | |
395 | { | |
396 | return __irq_domain_add(fwnode, 0, ~0, 0, ops, host_data); | |
cef5075c | 397 | } |
58ee99ad PM |
398 | |
399 | extern void irq_domain_remove(struct irq_domain *host); | |
400 | ||
ddaf144c GL |
401 | extern int irq_domain_associate(struct irq_domain *domain, unsigned int irq, |
402 | irq_hw_number_t hwirq); | |
403 | extern void irq_domain_associate_many(struct irq_domain *domain, | |
404 | unsigned int irq_base, | |
405 | irq_hw_number_t hwirq_base, int count); | |
98aa468e | 406 | |
bb4c6910 LV |
407 | extern unsigned int irq_create_mapping_affinity(struct irq_domain *host, |
408 | irq_hw_number_t hwirq, | |
409 | const struct irq_affinity_desc *affinity); | |
c0131f09 | 410 | extern unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec); |
cc79ca69 | 411 | extern void irq_dispose_mapping(unsigned int virq); |
d3dcb436 | 412 | |
bb4c6910 LV |
413 | static inline unsigned int irq_create_mapping(struct irq_domain *host, |
414 | irq_hw_number_t hwirq) | |
415 | { | |
416 | return irq_create_mapping_affinity(host, hwirq, NULL); | |
417 | } | |
418 | ||
d22558dd MZ |
419 | extern struct irq_desc *__irq_resolve_mapping(struct irq_domain *domain, |
420 | irq_hw_number_t hwirq, | |
421 | unsigned int *irq); | |
422 | ||
423 | static inline struct irq_desc *irq_resolve_mapping(struct irq_domain *domain, | |
424 | irq_hw_number_t hwirq) | |
425 | { | |
426 | return __irq_resolve_mapping(domain, hwirq, NULL); | |
427 | } | |
428 | ||
d3dcb436 | 429 | /** |
1da02736 | 430 | * irq_find_mapping() - Find a linux irq from a hw irq number. |
d3dcb436 GL |
431 | * @domain: domain owning this hardware interrupt |
432 | * @hwirq: hardware irq number in that domain space | |
d3dcb436 | 433 | */ |
d22558dd MZ |
434 | static inline unsigned int irq_find_mapping(struct irq_domain *domain, |
435 | irq_hw_number_t hwirq) | |
436 | { | |
437 | unsigned int irq; | |
438 | ||
439 | if (__irq_resolve_mapping(domain, hwirq, &irq)) | |
440 | return irq; | |
441 | ||
442 | return 0; | |
443 | } | |
1da02736 | 444 | |
d3dcb436 GL |
445 | static inline unsigned int irq_linear_revmap(struct irq_domain *domain, |
446 | irq_hw_number_t hwirq) | |
447 | { | |
1da02736 | 448 | return irq_find_mapping(domain, hwirq); |
d3dcb436 | 449 | } |
1da02736 | 450 | |
a18dc81b | 451 | extern const struct irq_domain_ops irq_domain_simple_ops; |
16b2e6e2 GL |
452 | |
453 | /* stock xlate functions */ | |
454 | int irq_domain_xlate_onecell(struct irq_domain *d, struct device_node *ctrlr, | |
455 | const u32 *intspec, unsigned int intsize, | |
456 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
457 | int irq_domain_xlate_twocell(struct irq_domain *d, struct device_node *ctrlr, | |
458 | const u32 *intspec, unsigned int intsize, | |
459 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
460 | int irq_domain_xlate_onetwocell(struct irq_domain *d, struct device_node *ctrlr, | |
461 | const u32 *intspec, unsigned int intsize, | |
462 | irq_hw_number_t *out_hwirq, unsigned int *out_type); | |
463 | ||
b5c231d8 BM |
464 | int irq_domain_translate_twocell(struct irq_domain *d, |
465 | struct irq_fwspec *fwspec, | |
466 | unsigned long *out_hwirq, | |
467 | unsigned int *out_type); | |
468 | ||
b01eccea YS |
469 | int irq_domain_translate_onecell(struct irq_domain *d, |
470 | struct irq_fwspec *fwspec, | |
471 | unsigned long *out_hwirq, | |
472 | unsigned int *out_type); | |
473 | ||
d17bf24e | 474 | /* IPI functions */ |
7cec18a3 MR |
475 | int irq_reserve_ipi(struct irq_domain *domain, const struct cpumask *dest); |
476 | int irq_destroy_ipi(unsigned int irq, const struct cpumask *dest); | |
d17bf24e | 477 | |
f8264e34 JL |
478 | /* V2 interfaces to support hierarchy IRQ domains. */ |
479 | extern struct irq_data *irq_domain_get_irq_data(struct irq_domain *domain, | |
480 | unsigned int virq); | |
5f22f5c6 | 481 | extern void irq_domain_set_info(struct irq_domain *domain, unsigned int virq, |
45ec846c MZ |
482 | irq_hw_number_t hwirq, |
483 | const struct irq_chip *chip, | |
5f22f5c6 SA |
484 | void *chip_data, irq_flow_handler_t handler, |
485 | void *handler_data, const char *handler_name); | |
5c8f77a2 | 486 | extern void irq_domain_reset_irq_data(struct irq_data *irq_data); |
f8264e34 | 487 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY |
2a5e9a07 | 488 | extern struct irq_domain *irq_domain_create_hierarchy(struct irq_domain *parent, |
afb7da83 | 489 | unsigned int flags, unsigned int size, |
2a5e9a07 | 490 | struct fwnode_handle *fwnode, |
afb7da83 | 491 | const struct irq_domain_ops *ops, void *host_data); |
2a5e9a07 MZ |
492 | |
493 | static inline struct irq_domain *irq_domain_add_hierarchy(struct irq_domain *parent, | |
494 | unsigned int flags, | |
495 | unsigned int size, | |
496 | struct device_node *node, | |
497 | const struct irq_domain_ops *ops, | |
498 | void *host_data) | |
499 | { | |
500 | return irq_domain_create_hierarchy(parent, flags, size, | |
501 | of_node_to_fwnode(node), | |
502 | ops, host_data); | |
503 | } | |
504 | ||
f8264e34 JL |
505 | extern int __irq_domain_alloc_irqs(struct irq_domain *domain, int irq_base, |
506 | unsigned int nr_irqs, int node, void *arg, | |
bec04037 DL |
507 | bool realloc, |
508 | const struct irq_affinity_desc *affinity); | |
f8264e34 | 509 | extern void irq_domain_free_irqs(unsigned int virq, unsigned int nr_irqs); |
42e1cc2d | 510 | extern int irq_domain_activate_irq(struct irq_data *irq_data, bool early); |
f8264e34 JL |
511 | extern void irq_domain_deactivate_irq(struct irq_data *irq_data); |
512 | ||
513 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, | |
514 | unsigned int nr_irqs, int node, void *arg) | |
515 | { | |
06ee6d57 TG |
516 | return __irq_domain_alloc_irqs(domain, -1, nr_irqs, node, arg, false, |
517 | NULL); | |
f8264e34 JL |
518 | } |
519 | ||
6a6544e5 | 520 | extern int irq_domain_alloc_irqs_hierarchy(struct irq_domain *domain, |
c466595c MZ |
521 | unsigned int irq_base, |
522 | unsigned int nr_irqs, void *arg); | |
f8264e34 JL |
523 | extern int irq_domain_set_hwirq_and_chip(struct irq_domain *domain, |
524 | unsigned int virq, | |
525 | irq_hw_number_t hwirq, | |
45ec846c | 526 | const struct irq_chip *chip, |
f8264e34 | 527 | void *chip_data); |
f8264e34 JL |
528 | extern void irq_domain_free_irqs_common(struct irq_domain *domain, |
529 | unsigned int virq, | |
530 | unsigned int nr_irqs); | |
531 | extern void irq_domain_free_irqs_top(struct irq_domain *domain, | |
532 | unsigned int virq, unsigned int nr_irqs); | |
533 | ||
495c38d3 DD |
534 | extern int irq_domain_push_irq(struct irq_domain *domain, int virq, void *arg); |
535 | extern int irq_domain_pop_irq(struct irq_domain *domain, int virq); | |
536 | ||
36d72731 JL |
537 | extern int irq_domain_alloc_irqs_parent(struct irq_domain *domain, |
538 | unsigned int irq_base, | |
539 | unsigned int nr_irqs, void *arg); | |
f8264e34 | 540 | |
36d72731 JL |
541 | extern void irq_domain_free_irqs_parent(struct irq_domain *domain, |
542 | unsigned int irq_base, | |
543 | unsigned int nr_irqs); | |
f8264e34 | 544 | |
55567976 MZ |
545 | extern int irq_domain_disconnect_hierarchy(struct irq_domain *domain, |
546 | unsigned int virq); | |
547 | ||
f8264e34 JL |
548 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
549 | { | |
550 | return domain->flags & IRQ_DOMAIN_FLAG_HIERARCHY; | |
551 | } | |
0abefbaa QY |
552 | |
553 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
554 | { | |
555 | return domain->flags & | |
556 | (IRQ_DOMAIN_FLAG_IPI_PER_CPU | IRQ_DOMAIN_FLAG_IPI_SINGLE); | |
557 | } | |
558 | ||
559 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
560 | { | |
561 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_PER_CPU; | |
562 | } | |
563 | ||
564 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
565 | { | |
566 | return domain->flags & IRQ_DOMAIN_FLAG_IPI_SINGLE; | |
567 | } | |
631a9639 EA |
568 | |
569 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
570 | { | |
571 | return domain->flags & IRQ_DOMAIN_FLAG_MSI; | |
572 | } | |
573 | ||
574 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
575 | { | |
576 | return domain->flags & IRQ_DOMAIN_FLAG_MSI_REMAP; | |
577 | } | |
578 | ||
579 | extern bool irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain); | |
580 | ||
f8264e34 | 581 | #else /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
f8264e34 JL |
582 | static inline int irq_domain_alloc_irqs(struct irq_domain *domain, |
583 | unsigned int nr_irqs, int node, void *arg) | |
584 | { | |
585 | return -1; | |
586 | } | |
587 | ||
1e2a7d78 JH |
588 | static inline void irq_domain_free_irqs(unsigned int virq, |
589 | unsigned int nr_irqs) { } | |
590 | ||
f8264e34 JL |
591 | static inline bool irq_domain_is_hierarchy(struct irq_domain *domain) |
592 | { | |
593 | return false; | |
594 | } | |
0abefbaa QY |
595 | |
596 | static inline bool irq_domain_is_ipi(struct irq_domain *domain) | |
597 | { | |
598 | return false; | |
599 | } | |
600 | ||
601 | static inline bool irq_domain_is_ipi_per_cpu(struct irq_domain *domain) | |
602 | { | |
603 | return false; | |
604 | } | |
605 | ||
606 | static inline bool irq_domain_is_ipi_single(struct irq_domain *domain) | |
607 | { | |
608 | return false; | |
609 | } | |
631a9639 EA |
610 | |
611 | static inline bool irq_domain_is_msi(struct irq_domain *domain) | |
612 | { | |
613 | return false; | |
614 | } | |
615 | ||
616 | static inline bool irq_domain_is_msi_remap(struct irq_domain *domain) | |
617 | { | |
618 | return false; | |
619 | } | |
620 | ||
621 | static inline bool | |
622 | irq_domain_hierarchical_is_msi_remap(struct irq_domain *domain) | |
623 | { | |
624 | return false; | |
625 | } | |
f8264e34 JL |
626 | #endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */ |
627 | ||
d593f25f GL |
628 | #else /* CONFIG_IRQ_DOMAIN */ |
629 | static inline void irq_dispose_mapping(unsigned int virq) { } | |
471036b2 SS |
630 | static inline struct irq_domain *irq_find_matching_fwnode( |
631 | struct fwnode_handle *fwnode, enum irq_domain_bus_token bus_token) | |
632 | { | |
633 | return NULL; | |
634 | } | |
b3e22847 MYK |
635 | static inline bool irq_domain_check_msi_remap(void) |
636 | { | |
637 | return false; | |
638 | } | |
d593f25f | 639 | #endif /* !CONFIG_IRQ_DOMAIN */ |
7e713301 | 640 | |
08a543ad | 641 | #endif /* _LINUX_IRQDOMAIN_H */ |