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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e144710b TG |
2 | #ifndef _LINUX_IRQDESC_H |
3 | #define _LINUX_IRQDESC_H | |
4 | ||
425a5072 | 5 | #include <linux/rcupdate.h> |
ecb3f394 | 6 | #include <linux/kobject.h> |
9114014c | 7 | #include <linux/mutex.h> |
425a5072 | 8 | |
e144710b TG |
9 | /* |
10 | * Core internal functions to deal with irq descriptors | |
e144710b TG |
11 | */ |
12 | ||
cd7eab44 | 13 | struct irq_affinity_notify; |
e144710b | 14 | struct proc_dir_entry; |
ec53cf23 | 15 | struct module; |
293a7a0a | 16 | struct irq_desc; |
76ba59f8 MZ |
17 | struct irq_domain; |
18 | struct pt_regs; | |
293a7a0a | 19 | |
e144710b TG |
20 | /** |
21 | * struct irq_desc - interrupt descriptor | |
0d0b4c86 | 22 | * @irq_common_data: per irq and chip data passed down to chip functions |
e144710b | 23 | * @kstat_irqs: irq stats per cpu |
77076778 | 24 | * @handle_irq: highlevel irq-events handler |
e144710b | 25 | * @action: the irq action chain |
80ebc420 | 26 | * @status_use_accessors: status information |
dbec07ba | 27 | * @core_internal_state__do_not_mess_with_it: core internal status information |
e144710b | 28 | * @depth: disable-depth, for nested irq_disable() calls |
0911f124 | 29 | * @wake_depth: enable depth, for multiple irq_set_irq_wake() callers |
030fc443 | 30 | * @tot_count: stats field for non-percpu irqs |
e144710b TG |
31 | * @irq_count: stats field to detect stalled irqs |
32 | * @last_unhandled: aging timer for unhandled count | |
33 | * @irqs_unhandled: stats field for spurious unhandled interrupts | |
1e77d0a1 | 34 | * @threads_handled: stats field for deferred spurious detection of threaded handlers |
a359f757 | 35 | * @threads_handled_last: comparator field for deferred spurious detection of threaded handlers |
e144710b | 36 | * @lock: locking for SMP |
77076778 | 37 | * @affinity_hint: hint to user space for preferred irq affinity |
cd7eab44 | 38 | * @affinity_notify: context for notification of affinity changes |
e144710b | 39 | * @pending_mask: pending rebalanced interrupts |
b5faba21 | 40 | * @threads_oneshot: bitfield to handle shared oneshot threads |
e144710b TG |
41 | * @threads_active: number of irqaction threads currently running |
42 | * @wait_for_threads: wait queue for sync_irq to wait for threaded handlers | |
cab303be TG |
43 | * @nr_actions: number of installed actions on this descriptor |
44 | * @no_suspend_depth: number of irqactions on a irq descriptor with | |
45 | * IRQF_NO_SUSPEND set | |
46 | * @force_resume_depth: number of irqactions on a irq descriptor with | |
47 | * IRQF_FORCE_RESUME set | |
425a5072 | 48 | * @rcu: rcu head for delayed free |
ecb3f394 | 49 | * @kobj: kobject used to represent this struct in sysfs |
9114014c | 50 | * @request_mutex: mutex to protect request/free before locking desc->lock |
e144710b | 51 | * @dir: /proc/irq/ procfs entry |
087cdfb6 | 52 | * @debugfs_file: dentry for the debugfs file |
e144710b TG |
53 | * @name: flow handler name for /proc/interrupts output |
54 | */ | |
55 | struct irq_desc { | |
0d0b4c86 | 56 | struct irq_common_data irq_common_data; |
e144710b | 57 | struct irq_data irq_data; |
6c9ae009 | 58 | unsigned int __percpu *kstat_irqs; |
e144710b TG |
59 | irq_flow_handler_t handle_irq; |
60 | struct irqaction *action; /* IRQ action list */ | |
a6967caf | 61 | unsigned int status_use_accessors; |
dbec07ba | 62 | unsigned int core_internal_state__do_not_mess_with_it; |
e144710b TG |
63 | unsigned int depth; /* nested irq disables */ |
64 | unsigned int wake_depth; /* nested wake enables */ | |
1136b072 | 65 | unsigned int tot_count; |
e144710b TG |
66 | unsigned int irq_count; /* For detecting broken IRQs */ |
67 | unsigned long last_unhandled; /* Aging timer for unhandled count */ | |
68 | unsigned int irqs_unhandled; | |
1e77d0a1 TG |
69 | atomic_t threads_handled; |
70 | int threads_handled_last; | |
e144710b | 71 | raw_spinlock_t lock; |
31d9d9b6 | 72 | struct cpumask *percpu_enabled; |
222df54f | 73 | const struct cpumask *percpu_affinity; |
e144710b TG |
74 | #ifdef CONFIG_SMP |
75 | const struct cpumask *affinity_hint; | |
cd7eab44 | 76 | struct irq_affinity_notify *affinity_notify; |
e144710b TG |
77 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
78 | cpumask_var_t pending_mask; | |
79 | #endif | |
80 | #endif | |
b5faba21 | 81 | unsigned long threads_oneshot; |
e144710b TG |
82 | atomic_t threads_active; |
83 | wait_queue_head_t wait_for_threads; | |
cab303be TG |
84 | #ifdef CONFIG_PM_SLEEP |
85 | unsigned int nr_actions; | |
86 | unsigned int no_suspend_depth; | |
17f48034 | 87 | unsigned int cond_suspend_depth; |
cab303be TG |
88 | unsigned int force_resume_depth; |
89 | #endif | |
e144710b TG |
90 | #ifdef CONFIG_PROC_FS |
91 | struct proc_dir_entry *dir; | |
425a5072 | 92 | #endif |
087cdfb6 TG |
93 | #ifdef CONFIG_GENERIC_IRQ_DEBUGFS |
94 | struct dentry *debugfs_file; | |
07557ccb | 95 | const char *dev_name; |
087cdfb6 | 96 | #endif |
425a5072 TG |
97 | #ifdef CONFIG_SPARSE_IRQ |
98 | struct rcu_head rcu; | |
ecb3f394 | 99 | struct kobject kobj; |
e144710b | 100 | #endif |
9114014c | 101 | struct mutex request_mutex; |
293a7a0a | 102 | int parent_irq; |
b6873807 | 103 | struct module *owner; |
e144710b TG |
104 | const char *name; |
105 | } ____cacheline_internodealigned_in_smp; | |
106 | ||
a8994181 TG |
107 | #ifdef CONFIG_SPARSE_IRQ |
108 | extern void irq_lock_sparse(void); | |
109 | extern void irq_unlock_sparse(void); | |
110 | #else | |
111 | static inline void irq_lock_sparse(void) { } | |
112 | static inline void irq_unlock_sparse(void) { } | |
e144710b TG |
113 | extern struct irq_desc irq_desc[NR_IRQS]; |
114 | #endif | |
115 | ||
501e2db6 TG |
116 | static inline unsigned int irq_desc_kstat_cpu(struct irq_desc *desc, |
117 | unsigned int cpu) | |
118 | { | |
119 | return desc->kstat_irqs ? *per_cpu_ptr(desc->kstat_irqs, cpu) : 0; | |
120 | } | |
121 | ||
7bbf1dd2 JL |
122 | static inline struct irq_desc *irq_data_to_desc(struct irq_data *data) |
123 | { | |
755d119a | 124 | return container_of(data->common, struct irq_desc, irq_common_data); |
7bbf1dd2 JL |
125 | } |
126 | ||
304adf8a JL |
127 | static inline unsigned int irq_desc_get_irq(struct irq_desc *desc) |
128 | { | |
129 | return desc->irq_data.irq; | |
130 | } | |
131 | ||
d9936bb3 TG |
132 | static inline struct irq_data *irq_desc_get_irq_data(struct irq_desc *desc) |
133 | { | |
134 | return &desc->irq_data; | |
135 | } | |
136 | ||
a0cd9ca2 TG |
137 | static inline struct irq_chip *irq_desc_get_chip(struct irq_desc *desc) |
138 | { | |
139 | return desc->irq_data.chip; | |
140 | } | |
141 | ||
142 | static inline void *irq_desc_get_chip_data(struct irq_desc *desc) | |
143 | { | |
144 | return desc->irq_data.chip_data; | |
145 | } | |
146 | ||
147 | static inline void *irq_desc_get_handler_data(struct irq_desc *desc) | |
148 | { | |
af7080e0 | 149 | return desc->irq_common_data.handler_data; |
a0cd9ca2 TG |
150 | } |
151 | ||
e144710b TG |
152 | /* |
153 | * Architectures call this to let the generic IRQ layer | |
6584d84c | 154 | * handle an interrupt. |
e144710b | 155 | */ |
bd0b9ac4 | 156 | static inline void generic_handle_irq_desc(struct irq_desc *desc) |
e144710b | 157 | { |
bd0b9ac4 | 158 | desc->handle_irq(desc); |
e144710b TG |
159 | } |
160 | ||
fe12bc2c | 161 | int generic_handle_irq(unsigned int irq); |
e144710b | 162 | |
76ba59f8 MZ |
163 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
164 | /* | |
165 | * Convert a HW interrupt number to a logical one using a IRQ domain, | |
166 | * and handle the result interrupt number. Return -EINVAL if | |
167 | * conversion failed. Providing a NULL domain indicates that the | |
168 | * conversion has already been done. | |
169 | */ | |
170 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, | |
171 | bool lookup, struct pt_regs *regs); | |
172 | ||
173 | static inline int handle_domain_irq(struct irq_domain *domain, | |
174 | unsigned int hwirq, struct pt_regs *regs) | |
175 | { | |
176 | return __handle_domain_irq(domain, hwirq, true, regs); | |
177 | } | |
6e4933a0 JT |
178 | |
179 | #ifdef CONFIG_IRQ_DOMAIN | |
180 | int handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq, | |
181 | struct pt_regs *regs); | |
182 | #endif | |
76ba59f8 MZ |
183 | #endif |
184 | ||
e144710b | 185 | /* Test to see if a driver has successfully requested an irq */ |
f61ae4fb | 186 | static inline int irq_desc_has_action(struct irq_desc *desc) |
e144710b | 187 | { |
a313357e | 188 | return desc && desc->action != NULL; |
f61ae4fb TG |
189 | } |
190 | ||
bbc9d21f TG |
191 | /** |
192 | * irq_set_handler_locked - Set irq handler from a locked region | |
193 | * @data: Pointer to the irq_data structure which identifies the irq | |
194 | * @handler: Flow control handler function for this interrupt | |
195 | * | |
196 | * Sets the handler in the irq descriptor associated to @data. | |
197 | * | |
198 | * Must be called with irq_desc locked and valid parameters. Typical | |
199 | * call site is the irq_set_type() callback. | |
200 | */ | |
201 | static inline void irq_set_handler_locked(struct irq_data *data, | |
202 | irq_flow_handler_t handler) | |
203 | { | |
204 | struct irq_desc *desc = irq_data_to_desc(data); | |
205 | ||
206 | desc->handle_irq = handler; | |
207 | } | |
208 | ||
209 | /** | |
210 | * irq_set_chip_handler_name_locked - Set chip, handler and name from a locked region | |
211 | * @data: Pointer to the irq_data structure for which the chip is set | |
212 | * @chip: Pointer to the new irq chip | |
213 | * @handler: Flow control handler function for this interrupt | |
214 | * @name: Name of the interrupt | |
215 | * | |
216 | * Replace the irq chip at the proper hierarchy level in @data and | |
217 | * sets the handler and name in the associated irq descriptor. | |
218 | * | |
219 | * Must be called with irq_desc locked and valid parameters. | |
220 | */ | |
221 | static inline void | |
222 | irq_set_chip_handler_name_locked(struct irq_data *data, struct irq_chip *chip, | |
223 | irq_flow_handler_t handler, const char *name) | |
224 | { | |
225 | struct irq_desc *desc = irq_data_to_desc(data); | |
226 | ||
227 | desc->handle_irq = handler; | |
228 | desc->name = name; | |
229 | data->chip = chip; | |
230 | } | |
231 | ||
fdd02963 TG |
232 | bool irq_check_status_bit(unsigned int irq, unsigned int bitmask); |
233 | ||
4ce413d1 | 234 | static inline bool irq_balancing_disabled(unsigned int irq) |
e144710b | 235 | { |
fdd02963 | 236 | return irq_check_status_bit(irq, IRQ_NO_BALANCING_MASK); |
e144710b | 237 | } |
78129576 | 238 | |
4ce413d1 | 239 | static inline bool irq_is_percpu(unsigned int irq) |
7f4a8e7b | 240 | { |
fdd02963 | 241 | return irq_check_status_bit(irq, IRQ_PER_CPU); |
7f4a8e7b VK |
242 | } |
243 | ||
4ce413d1 | 244 | static inline bool irq_is_percpu_devid(unsigned int irq) |
08395c7f | 245 | { |
fdd02963 | 246 | return irq_check_status_bit(irq, IRQ_PER_CPU_DEVID); |
08395c7f JT |
247 | } |
248 | ||
f1c6306c TG |
249 | void __irq_set_lockdep_class(unsigned int irq, struct lock_class_key *lock_class, |
250 | struct lock_class_key *request_class); | |
d3e17deb | 251 | static inline void |
39c3fd58 AL |
252 | irq_set_lockdep_class(unsigned int irq, struct lock_class_key *lock_class, |
253 | struct lock_class_key *request_class) | |
d3e17deb | 254 | { |
f1c6306c TG |
255 | if (IS_ENABLED(CONFIG_LOCKDEP)) |
256 | __irq_set_lockdep_class(irq, lock_class, request_class); | |
d3e17deb TG |
257 | } |
258 | ||
e144710b | 259 | #endif |