Commit | Line | Data |
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f27ecacc | 1 | /* |
520f7bd7 | 2 | * include/linux/irqchip/arm-gic.h |
f27ecacc RK |
3 | * |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
520f7bd7 RH |
10 | #ifndef __LINUX_IRQCHIP_ARM_GIC_H |
11 | #define __LINUX_IRQCHIP_ARM_GIC_H | |
f27ecacc | 12 | |
f27ecacc RK |
13 | #define GIC_CPU_CTRL 0x00 |
14 | #define GIC_CPU_PRIMASK 0x04 | |
15 | #define GIC_CPU_BINPOINT 0x08 | |
16 | #define GIC_CPU_INTACK 0x0c | |
17 | #define GIC_CPU_EOI 0x10 | |
18 | #define GIC_CPU_RUNNINGPRI 0x14 | |
19 | #define GIC_CPU_HIGHPRI 0x18 | |
0307e177 CD |
20 | #define GIC_CPU_ALIAS_BINPOINT 0x1c |
21 | #define GIC_CPU_ACTIVEPRIO 0xd0 | |
22 | #define GIC_CPU_IDENT 0xfc | |
0b996fd3 | 23 | #define GIC_CPU_DEACTIVATE 0x1000 |
f27ecacc | 24 | |
e5f81539 FK |
25 | #define GICC_ENABLE 0x1 |
26 | #define GICC_INT_PRI_THRESHOLD 0xf0 | |
0b996fd3 | 27 | |
28232a43 CD |
28 | #define GIC_CPU_CTRL_EnableGrp0_SHIFT 0 |
29 | #define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT) | |
30 | #define GIC_CPU_CTRL_EnableGrp1_SHIFT 1 | |
31 | #define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT) | |
32 | #define GIC_CPU_CTRL_AckCtl_SHIFT 2 | |
33 | #define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT) | |
34 | #define GIC_CPU_CTRL_FIQEn_SHIFT 3 | |
35 | #define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT) | |
36 | #define GIC_CPU_CTRL_CBPR_SHIFT 4 | |
37 | #define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT) | |
38 | #define GIC_CPU_CTRL_EOImodeNS_SHIFT 9 | |
39 | #define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT) | |
0b996fd3 | 40 | |
b8802f76 | 41 | #define GICC_IAR_INT_ID_MASK 0x3ff |
e5f81539 | 42 | #define GICC_INT_SPURIOUS 1023 |
32289506 | 43 | #define GICC_DIS_BYPASS_MASK 0x1e0 |
b8802f76 | 44 | |
f27ecacc RK |
45 | #define GIC_DIST_CTRL 0x000 |
46 | #define GIC_DIST_CTR 0x004 | |
2b0cda87 | 47 | #define GIC_DIST_IIDR 0x008 |
7c7945a8 | 48 | #define GIC_DIST_IGROUP 0x080 |
f27ecacc RK |
49 | #define GIC_DIST_ENABLE_SET 0x100 |
50 | #define GIC_DIST_ENABLE_CLEAR 0x180 | |
51 | #define GIC_DIST_PENDING_SET 0x200 | |
52 | #define GIC_DIST_PENDING_CLEAR 0x280 | |
7c7945a8 CD |
53 | #define GIC_DIST_ACTIVE_SET 0x300 |
54 | #define GIC_DIST_ACTIVE_CLEAR 0x380 | |
f27ecacc RK |
55 | #define GIC_DIST_PRI 0x400 |
56 | #define GIC_DIST_TARGET 0x800 | |
57 | #define GIC_DIST_CONFIG 0xc00 | |
58 | #define GIC_DIST_SOFTINT 0xf00 | |
1a6b69b6 NP |
59 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 |
60 | #define GIC_DIST_SGI_PENDING_SET 0xf20 | |
f27ecacc | 61 | |
e5f81539 FK |
62 | #define GICD_ENABLE 0x1 |
63 | #define GICD_DISABLE 0x0 | |
64 | #define GICD_INT_ACTLOW_LVLTRIG 0x0 | |
65 | #define GICD_INT_EN_CLR_X32 0xffffffff | |
66 | #define GICD_INT_EN_SET_SGI 0x0000ffff | |
67 | #define GICD_INT_EN_CLR_PPI 0xffff0000 | |
68 | #define GICD_INT_DEF_PRI 0xa0 | |
69 | #define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ | |
70 | (GICD_INT_DEF_PRI << 16) |\ | |
71 | (GICD_INT_DEF_PRI << 8) |\ | |
72 | GICD_INT_DEF_PRI) | |
73 | ||
fdf77a72 MZ |
74 | #define GICH_HCR 0x0 |
75 | #define GICH_VTR 0x4 | |
76 | #define GICH_VMCR 0x8 | |
77 | #define GICH_MISR 0x10 | |
78 | #define GICH_EISR0 0x20 | |
79 | #define GICH_EISR1 0x24 | |
80 | #define GICH_ELRSR0 0x30 | |
81 | #define GICH_ELRSR1 0x34 | |
82 | #define GICH_APR 0xf0 | |
83 | #define GICH_LR0 0x100 | |
84 | ||
85 | #define GICH_HCR_EN (1 << 0) | |
86 | #define GICH_HCR_UIE (1 << 1) | |
16ca6a60 | 87 | #define GICH_HCR_NPIE (1 << 3) |
fdf77a72 MZ |
88 | |
89 | #define GICH_LR_VIRTUALID (0x3ff << 0) | |
90 | #define GICH_LR_PHYSID_CPUID_SHIFT (10) | |
fb182cf8 | 91 | #define GICH_LR_PHYSID_CPUID (0x3ff << GICH_LR_PHYSID_CPUID_SHIFT) |
140b086d | 92 | #define GICH_LR_PRIORITY_SHIFT 23 |
fdf77a72 MZ |
93 | #define GICH_LR_STATE (3 << 28) |
94 | #define GICH_LR_PENDING_BIT (1 << 28) | |
95 | #define GICH_LR_ACTIVE_BIT (1 << 29) | |
96 | #define GICH_LR_EOI (1 << 19) | |
fb182cf8 | 97 | #define GICH_LR_HW (1 << 31) |
fdf77a72 | 98 | |
28232a43 CD |
99 | #define GICH_VMCR_ENABLE_GRP0_SHIFT 0 |
100 | #define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT) | |
101 | #define GICH_VMCR_ENABLE_GRP1_SHIFT 1 | |
102 | #define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT) | |
103 | #define GICH_VMCR_ACK_CTL_SHIFT 2 | |
104 | #define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT) | |
105 | #define GICH_VMCR_FIQ_EN_SHIFT 3 | |
106 | #define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT) | |
107 | #define GICH_VMCR_CBPR_SHIFT 4 | |
108 | #define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT) | |
109 | #define GICH_VMCR_EOI_MODE_SHIFT 9 | |
110 | #define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT) | |
111 | ||
0307e177 CD |
112 | #define GICH_VMCR_PRIMASK_SHIFT 27 |
113 | #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) | |
114 | #define GICH_VMCR_BINPOINT_SHIFT 21 | |
115 | #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) | |
116 | #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 | |
117 | #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) | |
118 | ||
fdf77a72 MZ |
119 | #define GICH_MISR_EOI (1 << 0) |
120 | #define GICH_MISR_U (1 << 1) | |
121 | ||
6d56111c CD |
122 | #define GICV_PMR_PRIORITY_SHIFT 3 |
123 | #define GICV_PMR_PRIORITY_MASK (0x1f << GICV_PMR_PRIORITY_SHIFT) | |
124 | ||
a96ab039 MZ |
125 | #ifndef __ASSEMBLY__ |
126 | ||
df870c78 JC |
127 | #include <linux/irqdomain.h> |
128 | ||
4294f8ba | 129 | struct device_node; |
cdbb813d | 130 | struct gic_chip_data; |
4294f8ba | 131 | |
b3a1bde4 | 132 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
4c2880b3 | 133 | int gic_cpu_if_down(unsigned int gic_nr); |
cdbb813d JH |
134 | void gic_cpu_save(struct gic_chip_data *gic); |
135 | void gic_cpu_restore(struct gic_chip_data *gic); | |
136 | void gic_dist_save(struct gic_chip_data *gic); | |
137 | void gic_dist_restore(struct gic_chip_data *gic); | |
e807acbc | 138 | |
8673c1d7 LW |
139 | /* |
140 | * Subdrivers that need some preparatory work can initialize their | |
141 | * chips and call this to register their GICs. | |
142 | */ | |
143 | int gic_of_init(struct device_node *node, struct device_node *parent); | |
144 | ||
9c8edddf JH |
145 | /* |
146 | * Initialises and registers a non-root or child GIC chip. Memory for | |
147 | * the gic_chip_data structure is dynamically allocated. | |
148 | */ | |
149 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq); | |
150 | ||
8673c1d7 LW |
151 | /* |
152 | * Legacy platforms not converted to DT yet must use this to init | |
153 | * their GIC | |
154 | */ | |
e81a7cd9 MZ |
155 | void gic_init(unsigned int nr, int start, |
156 | void __iomem *dist , void __iomem *cpu); | |
db0d4db2 | 157 | |
0644b3da SS |
158 | int gicv2m_init(struct fwnode_handle *parent_handle, |
159 | struct irq_domain *parent); | |
853a33ce | 160 | |
14d2ca61 | 161 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq); |
ed96762e | 162 | int gic_get_cpu_id(unsigned int cpu); |
1a6b69b6 | 163 | void gic_migrate_target(unsigned int new_cpu_id); |
eeb44658 | 164 | unsigned long gic_get_sgir_physaddr(void); |
1a6b69b6 | 165 | |
a96ab039 | 166 | #endif /* __ASSEMBLY */ |
f27ecacc | 167 | #endif |