[linux-2.6-block.git] / include / linux / irqchip / arm-gic.h

/*
 *  include/linux/irqchip/arm-gic.h
 *
 *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __LINUX_IRQCHIP_ARM_GIC_H
#define __LINUX_IRQCHIP_ARM_GIC_H

#define GIC_CPU_CTRL			0x00
#define GIC_CPU_PRIMASK			0x04
#define GIC_CPU_BINPOINT		0x08
#define GIC_CPU_INTACK			0x0c
#define GIC_CPU_EOI			0x10
#define GIC_CPU_RUNNINGPRI		0x14
#define GIC_CPU_HIGHPRI			0x18

#define GIC_DIST_CTRL			0x000
#define GIC_DIST_CTR			0x004
#define GIC_DIST_ENABLE_SET		0x100
#define GIC_DIST_ENABLE_CLEAR		0x180
#define GIC_DIST_PENDING_SET		0x200
#define GIC_DIST_PENDING_CLEAR		0x280
#define GIC_DIST_ACTIVE_BIT		0x300
#define GIC_DIST_PRI			0x400
#define GIC_DIST_TARGET			0x800
#define GIC_DIST_CONFIG			0xc00
#define GIC_DIST_SOFTINT		0xf00

struct device_node;

extern struct irq_chip gic_arch_extn;

void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
		    u32 offset, struct device_node *);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);

static inline void gic_init(unsigned int nr, int start,
			    void __iomem *dist , void __iomem *cpu)
{
	gic_init_bases(nr, start, dist, cpu, 0, NULL);
}

#endif
Commit	Line	Data
f27ecacc	1	/*
520f7bd7	2	* include/linux/irqchip/arm-gic.h
f27ecacc RK	3	*
	4	* Copyright (C) 2002 ARM Limited, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
520f7bd7 RH	10	#ifndef __LINUX_IRQCHIP_ARM_GIC_H
520f7bd7 RH	11	#define __LINUX_IRQCHIP_ARM_GIC_H
f27ecacc	12
f27ecacc RK	13	#define GIC_CPU_CTRL 0x00
	14	#define GIC_CPU_PRIMASK 0x04
	15	#define GIC_CPU_BINPOINT 0x08
	16	#define GIC_CPU_INTACK 0x0c
	17	#define GIC_CPU_EOI 0x10
	18	#define GIC_CPU_RUNNINGPRI 0x14
	19	#define GIC_CPU_HIGHPRI 0x18
	20
	21	#define GIC_DIST_CTRL 0x000
	22	#define GIC_DIST_CTR 0x004
	23	#define GIC_DIST_ENABLE_SET 0x100
	24	#define GIC_DIST_ENABLE_CLEAR 0x180
	25	#define GIC_DIST_PENDING_SET 0x200
	26	#define GIC_DIST_PENDING_CLEAR 0x280
	27	#define GIC_DIST_ACTIVE_BIT 0x300
	28	#define GIC_DIST_PRI 0x400
	29	#define GIC_DIST_TARGET 0x800
	30	#define GIC_DIST_CONFIG 0xc00
	31	#define GIC_DIST_SOFTINT 0xf00
	32
4294f8ba RH	33	struct device_node;
4294f8ba RH	34
d7ed36a4	35	extern struct irq_chip gic_arch_extn;
ff2e27ae	36
db0d4db2	37	void gic_init_bases(unsigned int, int, void __iomem , void __iomem ,
75294957	38	u32 offset, struct device_node *);
38489533	39	void gic_secondary_init(unsigned int);
b3a1bde4	40	void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
e807acbc	41
db0d4db2 MZ	42	static inline void gic_init(unsigned int nr, int start,
	43	void __iomem dist , void __iomem cpu)
	44	{
75294957	45	gic_init_bases(nr, start, dist, cpu, 0, NULL);
db0d4db2 MZ	46	}
db0d4db2 MZ	47
f27ecacc	48	#endif