[linux-block.git] / include / linux / irq.h

#ifndef _LINUX_IRQ_H
#define _LINUX_IRQ_H

/*
 * Please do not include this file in generic code.  There is currently
 * no requirement for any architecture to implement anything held
 * within this file.
 *
 * Thanks. --rmk
 */

#include <linux/smp.h>

#ifndef CONFIG_S390

#include <linux/linkage.h>
#include <linux/cache.h>
#include <linux/spinlock.h>
#include <linux/cpumask.h>
#include <linux/gfp.h>
#include <linux/irqreturn.h>
#include <linux/irqnr.h>
#include <linux/errno.h>
#include <linux/topology.h>
#include <linux/wait.h>

#include <asm/irq.h>
#include <asm/ptrace.h>
#include <asm/irq_regs.h>

struct irq_desc;
typedef	void (*irq_flow_handler_t)(unsigned int irq,
					    struct irq_desc *desc);


/*
 * IRQ line status.
 *
 * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
 *
 * IRQ types
 */
#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */

/* Internal flags */
#define IRQ_INPROGRESS		0x00000100	/* IRQ handler active - do not enter! */
#define IRQ_DISABLED		0x00000200	/* IRQ disabled - do not enter! */
#define IRQ_PENDING		0x00000400	/* IRQ pending - replay on enable */
#define IRQ_REPLAY		0x00000800	/* IRQ has been replayed but not acked yet */
#define IRQ_AUTODETECT		0x00001000	/* IRQ is being autodetected */
#define IRQ_WAITING		0x00002000	/* IRQ not yet seen - for autodetection */
#define IRQ_LEVEL		0x00004000	/* IRQ level triggered */
#define IRQ_MASKED		0x00008000	/* IRQ masked - shouldn't be seen again */
#define IRQ_PER_CPU		0x00010000	/* IRQ is per CPU */
#define IRQ_NOPROBE		0x00020000	/* IRQ is not valid for probing */
#define IRQ_NOREQUEST		0x00040000	/* IRQ cannot be requested */
#define IRQ_NOAUTOEN		0x00080000	/* IRQ will not be enabled on request irq */
#define IRQ_WAKEUP		0x00100000	/* IRQ triggers system wakeup */
#define IRQ_MOVE_PENDING	0x00200000	/* need to re-target IRQ destination */
#define IRQ_NO_BALANCING	0x00400000	/* IRQ is excluded from balancing */
#define IRQ_SPURIOUS_DISABLED	0x00800000	/* IRQ was disabled by the spurious trap */
#define IRQ_MOVE_PCNTXT		0x01000000	/* IRQ migration from process context */
#define IRQ_AFFINITY_SET	0x02000000	/* IRQ affinity was set from userspace*/
#define IRQ_SUSPENDED		0x04000000	/* IRQ has gone through suspend sequence */

#ifdef CONFIG_IRQ_PER_CPU
# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
# define IRQ_NO_BALANCING_MASK	(IRQ_PER_CPU | IRQ_NO_BALANCING)
#else
# define CHECK_IRQ_PER_CPU(var) 0
# define IRQ_NO_BALANCING_MASK	IRQ_NO_BALANCING
#endif

struct proc_dir_entry;
struct msi_desc;

/**
 * struct irq_chip - hardware interrupt chip descriptor
 *
 * @name:		name for /proc/interrupts
 * @startup:		start up the interrupt (defaults to ->enable if NULL)
 * @shutdown:		shut down the interrupt (defaults to ->disable if NULL)
 * @enable:		enable the interrupt (defaults to chip->unmask if NULL)
 * @disable:		disable the interrupt (defaults to chip->mask if NULL)
 * @ack:		start of a new interrupt
 * @mask:		mask an interrupt source
 * @mask_ack:		ack and mask an interrupt source
 * @unmask:		unmask an interrupt source
 * @eoi:		end of interrupt - chip level
 * @end:		end of interrupt - flow level
 * @set_affinity:	set the CPU affinity on SMP machines
 * @retrigger:		resend an IRQ to the CPU
 * @set_type:		set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
 * @set_wake:		enable/disable power-management wake-on of an IRQ
 *
 * @release:		release function solely used by UML
 * @typename:		obsoleted by name, kept as migration helper
 */
struct irq_chip {
	const char	*name;
	unsigned int	(*startup)(unsigned int irq);
	void		(*shutdown)(unsigned int irq);
	void		(*enable)(unsigned int irq);
	void		(*disable)(unsigned int irq);

	void		(*ack)(unsigned int irq);
	void		(*mask)(unsigned int irq);
	void		(*mask_ack)(unsigned int irq);
	void		(*unmask)(unsigned int irq);
	void		(*eoi)(unsigned int irq);

	void		(*end)(unsigned int irq);
	void		(*set_affinity)(unsigned int irq,
					const struct cpumask *dest);
	int		(*retrigger)(unsigned int irq);
	int		(*set_type)(unsigned int irq, unsigned int flow_type);
	int		(*set_wake)(unsigned int irq, unsigned int on);

	/* Currently used only by UML, might disappear one day.*/
#ifdef CONFIG_IRQ_RELEASE_METHOD
	void		(*release)(unsigned int irq, void *dev_id);
#endif
	/*
	 * For compatibility, ->typename is copied into ->name.
	 * Will disappear.
	 */
	const char	*typename;
};

struct timer_rand_state;
struct irq_2_iommu;
/**
 * struct irq_desc - interrupt descriptor
 * @irq:		interrupt number for this descriptor
 * @timer_rand_state:	pointer to timer rand state struct
 * @kstat_irqs:		irq stats per cpu
 * @irq_2_iommu:	iommu with this irq
 * @handle_irq:		highlevel irq-events handler [if NULL, __do_IRQ()]
 * @chip:		low level interrupt hardware access
 * @msi_desc:		MSI descriptor
 * @handler_data:	per-IRQ data for the irq_chip methods
 * @chip_data:		platform-specific per-chip private data for the chip
 *			methods, to allow shared chip implementations
 * @action:		the irq action chain
 * @status:		status information
 * @depth:		disable-depth, for nested irq_disable() calls
 * @wake_depth:		enable depth, for multiple set_irq_wake() callers
 * @irq_count:		stats field to detect stalled irqs
 * @last_unhandled:	aging timer for unhandled count
 * @irqs_unhandled:	stats field for spurious unhandled interrupts
 * @lock:		locking for SMP
 * @affinity:		IRQ affinity on SMP
 * @cpu:		cpu index useful for balancing
 * @pending_mask:	pending rebalanced interrupts
 * @threads_active:	number of irqaction threads currently running
 * @wait_for_threads:	wait queue for sync_irq to wait for threaded handlers
 * @dir:		/proc/irq/ procfs entry
 * @name:		flow handler name for /proc/interrupts output
 */
struct irq_desc {
	unsigned int		irq;
	struct timer_rand_state *timer_rand_state;
	unsigned int            *kstat_irqs;
#ifdef CONFIG_INTR_REMAP
	struct irq_2_iommu      *irq_2_iommu;
#endif
	irq_flow_handler_t	handle_irq;
	struct irq_chip		*chip;
	struct msi_desc		*msi_desc;
	void			*handler_data;
	void			*chip_data;
	struct irqaction	*action;	/* IRQ action list */
	unsigned int		status;		/* IRQ status */

	unsigned int		depth;		/* nested irq disables */
	unsigned int		wake_depth;	/* nested wake enables */
	unsigned int		irq_count;	/* For detecting broken IRQs */
	unsigned long		last_unhandled;	/* Aging timer for unhandled count */
	unsigned int		irqs_unhandled;
	spinlock_t		lock;
#ifdef CONFIG_SMP
	cpumask_var_t		affinity;
	unsigned int		cpu;
#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_var_t		pending_mask;
#endif
#endif
	atomic_t		threads_active;
	wait_queue_head_t       wait_for_threads;
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry	*dir;
#endif
	const char		*name;
} ____cacheline_internodealigned_in_smp;

extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
					struct irq_desc *desc, int cpu);
extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc);

#ifndef CONFIG_SPARSE_IRQ
extern struct irq_desc irq_desc[NR_IRQS];
#else /* CONFIG_SPARSE_IRQ */
extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int cpu);
#endif /* CONFIG_SPARSE_IRQ */

extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);

static inline struct irq_desc *
irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	return irq_to_desc(irq);
#else
	return desc;
#endif
}

/*
 * Migration helpers for obsolete names, they will go away:
 */
#define hw_interrupt_type	irq_chip
#define no_irq_type		no_irq_chip
typedef struct irq_desc		irq_desc_t;

/*
 * Pick up the arch-dependent methods:
 */
#include <asm/hw_irq.h>

extern int setup_irq(unsigned int irq, struct irqaction *new);
extern void remove_irq(unsigned int irq, struct irqaction *act);

#ifdef CONFIG_GENERIC_HARDIRQS

#ifdef CONFIG_SMP

#ifdef CONFIG_GENERIC_PENDING_IRQ

void move_native_irq(int irq);
void move_masked_irq(int irq);

#else /* CONFIG_GENERIC_PENDING_IRQ */

static inline void move_irq(int irq)
{
}

static inline void move_native_irq(int irq)
{
}

static inline void move_masked_irq(int irq)
{
}

#endif /* CONFIG_GENERIC_PENDING_IRQ */

#else /* CONFIG_SMP */

#define move_native_irq(x)
#define move_masked_irq(x)

#endif /* CONFIG_SMP */

extern int no_irq_affinity;

static inline int irq_balancing_disabled(unsigned int irq)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	return desc->status & IRQ_NO_BALANCING_MASK;
}

/* Handle irq action chains: */
extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);

/*
 * Built-in IRQ handlers for various IRQ types,
 * callable via desc->chip->handle_irq()
 */
extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);

/*
 * Monolithic do_IRQ implementation.
 */
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
extern unsigned int __do_IRQ(unsigned int irq);
#endif

/*
 * Architectures call this to let the generic IRQ layer
 * handle an interrupt. If the descriptor is attached to an
 * irqchip-style controller then we call the ->handle_irq() handler,
 * and it calls __do_IRQ() if it's attached to an irqtype-style controller.
 */
static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
{
#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
	desc->handle_irq(irq, desc);
#else
	if (likely(desc->handle_irq))
		desc->handle_irq(irq, desc);
	else
		__do_IRQ(irq);
#endif
}

static inline void generic_handle_irq(unsigned int irq)
{
	generic_handle_irq_desc(irq, irq_to_desc(irq));
}

/* Handling of unhandled and spurious interrupts: */
extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
			   irqreturn_t action_ret);

/* Resending of interrupts :*/
void check_irq_resend(struct irq_desc *desc, unsigned int irq);

/* Enable/disable irq debugging output: */
extern int noirqdebug_setup(char *str);

/* Checks whether the interrupt can be requested by request_irq(): */
extern int can_request_irq(unsigned int irq, unsigned long irqflags);

/* Dummy irq-chip implementations: */
extern struct irq_chip no_irq_chip;
extern struct irq_chip dummy_irq_chip;

extern void
set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
			 irq_flow_handler_t handle);
extern void
set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
			      irq_flow_handler_t handle, const char *name);

extern void
__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
		  const char *name);

/* caller has locked the irq_desc and both params are valid */
static inline void __set_irq_handler_unlocked(int irq,
					      irq_flow_handler_t handler)
{
	struct irq_desc *desc;

	desc = irq_to_desc(irq);
	desc->handle_irq = handler;
}

/*
 * Set a highlevel flow handler for a given IRQ:
 */
static inline void
set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 0, NULL);
}

/*
 * Set a highlevel chained flow handler for a given IRQ.
 * (a chained handler is automatically enabled and set to
 *  IRQ_NOREQUEST and IRQ_NOPROBE)
 */
static inline void
set_irq_chained_handler(unsigned int irq,
			irq_flow_handler_t handle)
{
	__set_irq_handler(irq, handle, 1, NULL);
}

extern void set_irq_noprobe(unsigned int irq);
extern void set_irq_probe(unsigned int irq);

/* Handle dynamic irq creation and destruction */
extern unsigned int create_irq_nr(unsigned int irq_want);
extern int create_irq(void);
extern void destroy_irq(unsigned int irq);

/* Test to see if a driver has successfully requested an irq */
static inline int irq_has_action(unsigned int irq)
{
	struct irq_desc *desc = irq_to_desc(irq);
	return desc->action != NULL;
}

/* Dynamic irq helper functions */
extern void dynamic_irq_init(unsigned int irq);
extern void dynamic_irq_cleanup(unsigned int irq);

/* Set/get chip/data for an IRQ: */
extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
extern int set_irq_data(unsigned int irq, void *data);
extern int set_irq_chip_data(unsigned int irq, void *data);
extern int set_irq_type(unsigned int irq, unsigned int type);
extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);

#define get_irq_chip(irq)	(irq_to_desc(irq)->chip)
#define get_irq_chip_data(irq)	(irq_to_desc(irq)->chip_data)
#define get_irq_data(irq)	(irq_to_desc(irq)->handler_data)
#define get_irq_msi(irq)	(irq_to_desc(irq)->msi_desc)

#define get_irq_desc_chip(desc)		((desc)->chip)
#define get_irq_desc_chip_data(desc)	((desc)->chip_data)
#define get_irq_desc_data(desc)		((desc)->handler_data)
#define get_irq_desc_msi(desc)		((desc)->msi_desc)

#endif /* CONFIG_GENERIC_HARDIRQS */

#endif /* !CONFIG_S390 */

#ifdef CONFIG_SMP
/**
 * init_alloc_desc_masks - allocate cpumasks for irq_desc
 * @desc:	pointer to irq_desc struct
 * @cpu:	cpu which will be handling the cpumasks
 * @boot:	true if need bootmem
 *
 * Allocates affinity and pending_mask cpumask if required.
 * Returns true if successful (or not required).
 * Side effect: affinity has all bits set, pending_mask has all bits clear.
 */
static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	int node;

	if (boot) {
		alloc_bootmem_cpumask_var(&desc->affinity);
		cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
		alloc_bootmem_cpumask_var(&desc->pending_mask);
		cpumask_clear(desc->pending_mask);
#endif
		return true;
	}

	node = cpu_to_node(cpu);

	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
		return false;
	cpumask_setall(desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
		free_cpumask_var(desc->affinity);
		return false;
	}
	cpumask_clear(desc->pending_mask);
#endif
	return true;
}

/**
 * init_copy_desc_masks - copy cpumasks for irq_desc
 * @old_desc:	pointer to old irq_desc struct
 * @new_desc:	pointer to new irq_desc struct
 *
 * Insures affinity and pending_masks are copied to new irq_desc.
 * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
 * irq_desc struct so the copy is redundant.
 */

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
#ifdef CONFIG_CPUMASKS_OFFSTACK
	cpumask_copy(new_desc->affinity, old_desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
#endif
#endif
}

static inline void free_desc_masks(struct irq_desc *old_desc,
				   struct irq_desc *new_desc)
{
	free_cpumask_var(old_desc->affinity);

#ifdef CONFIG_GENERIC_PENDING_IRQ
	free_cpumask_var(old_desc->pending_mask);
#endif
}

#else /* !CONFIG_SMP */

static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
								bool boot)
{
	return true;
}

static inline void init_copy_desc_masks(struct irq_desc *old_desc,
					struct irq_desc *new_desc)
{
}

static inline void free_desc_masks(struct irq_desc *old_desc,
				   struct irq_desc *new_desc)
{
}
#endif	/* CONFIG_SMP */

#endif /* _LINUX_IRQ_H */
Commit	Line	Data
06fcb0c6 IM	1	#ifndef _LINUX_IRQ_H
06fcb0c6 IM	2	#define _LINUX_IRQ_H
1da177e4 LT	3
	4	/*
	5	* Please do not include this file in generic code. There is currently
	6	* no requirement for any architecture to implement anything held
	7	* within this file.
	8	*
	9	* Thanks. --rmk
	10	*/
	11
23f9b317	12	#include <linux/smp.h>
1da177e4	13
06fcb0c6	14	#ifndef CONFIG_S390
1da177e4 LT	15
	16	#include <linux/linkage.h>
	17	#include <linux/cache.h>
	18	#include <linux/spinlock.h>
	19	#include <linux/cpumask.h>
503e5763	20	#include <linux/gfp.h>
908dcecd	21	#include <linux/irqreturn.h>
dd3a1db9	22	#include <linux/irqnr.h>
77904fd6	23	#include <linux/errno.h>
503e5763	24	#include <linux/topology.h>
3aa551c9	25	#include <linux/wait.h>
1da177e4 LT	26
	27	#include <asm/irq.h>
	28	#include <asm/ptrace.h>
7d12e780	29	#include <asm/irq_regs.h>
1da177e4	30
57a58a94	31	struct irq_desc;
ec701584	32	typedef void (*irq_flow_handler_t)(unsigned int irq,
7d12e780	33	struct irq_desc *desc);
57a58a94 DH	34
57a58a94 DH	35
1da177e4 LT	36	/*
1da177e4 LT	37	* IRQ line status.
6e213616	38	*
950f4427	39	* Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h
6e213616 TG	40	*
6e213616 TG	41	* IRQ types
1da177e4	42	*/
6e213616 TG	43	#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
	44	#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
	45	#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
	46	#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING)
	47	#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
	48	#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
	49	#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
	50	#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
	51
	52	/* Internal flags */
950f4427 TG	53	#define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */
	54	#define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */
	55	#define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */
	56	#define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */
	57	#define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */
	58	#define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */
	59	#define IRQ_LEVEL 0x00004000 /* IRQ level triggered */
	60	#define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */
	61	#define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */
	62	#define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */
	63	#define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */
	64	#define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */
d7e25f33 IM	65	#define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */
	66	#define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */
	67	#define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */
1adb0850	68	#define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */
f6d87f4b TG	69	#define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */
f6d87f4b TG	70	#define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/
0a0c5168	71	#define IRQ_SUSPENDED 0x04000000 /* IRQ has gone through suspend sequence */
950f4427	72
0d7012a9	73	#ifdef CONFIG_IRQ_PER_CPU
f26fdd59	74	# define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
950f4427	75	# define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU \| IRQ_NO_BALANCING)
f26fdd59 KW	76	#else
f26fdd59 KW	77	# define CHECK_IRQ_PER_CPU(var) 0
950f4427	78	# define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING
f26fdd59	79	#endif
1da177e4	80
6a6de9ef	81	struct proc_dir_entry;
5b912c10	82	struct msi_desc;
6a6de9ef	83
8fee5c36	84	/**
6a6de9ef	85	* struct irq_chip - hardware interrupt chip descriptor
8fee5c36 IM	86	*
	87	* @name: name for /proc/interrupts
	88	* @startup: start up the interrupt (defaults to ->enable if NULL)
	89	* @shutdown: shut down the interrupt (defaults to ->disable if NULL)
	90	* @enable: enable the interrupt (defaults to chip->unmask if NULL)
	91	* @disable: disable the interrupt (defaults to chip->mask if NULL)
8fee5c36 IM	92	* @ack: start of a new interrupt
	93	* @mask: mask an interrupt source
	94	* @mask_ack: ack and mask an interrupt source
	95	* @unmask: unmask an interrupt source
47c2a3aa IM	96	* @eoi: end of interrupt - chip level
47c2a3aa IM	97	* @end: end of interrupt - flow level
8fee5c36 IM	98	* @set_affinity: set the CPU affinity on SMP machines
	99	* @retrigger: resend an IRQ to the CPU
	100	* @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
	101	* @set_wake: enable/disable power-management wake-on of an IRQ
	102	*
	103	* @release: release function solely used by UML
6a6de9ef	104	* @typename: obsoleted by name, kept as migration helper
1da177e4	105	*/
6a6de9ef TG	106	struct irq_chip {
6a6de9ef TG	107	const char *name;
71d218b7 IM	108	unsigned int (*startup)(unsigned int irq);
	109	void (*shutdown)(unsigned int irq);
	110	void (*enable)(unsigned int irq);
	111	void (*disable)(unsigned int irq);
6a6de9ef	112
71d218b7	113	void (*ack)(unsigned int irq);
6a6de9ef TG	114	void (*mask)(unsigned int irq);
	115	void (*mask_ack)(unsigned int irq);
	116	void (*unmask)(unsigned int irq);
47c2a3aa	117	void (*eoi)(unsigned int irq);
6a6de9ef	118
71d218b7	119	void (*end)(unsigned int irq);
0de26520 RR	120	void (*set_affinity)(unsigned int irq,
0de26520 RR	121	const struct cpumask *dest);
c0ad90a3	122	int (*retrigger)(unsigned int irq);
6a6de9ef TG	123	int (*set_type)(unsigned int irq, unsigned int flow_type);
6a6de9ef TG	124	int (*set_wake)(unsigned int irq, unsigned int on);
c0ad90a3	125
b77d6adc PBG	126	/* Currently used only by UML, might disappear one day.*/
b77d6adc PBG	127	#ifdef CONFIG_IRQ_RELEASE_METHOD
71d218b7	128	void (release)(unsigned int irq, void dev_id);
b77d6adc	129	#endif
6a6de9ef TG	130	/*
	131	* For compatibility, ->typename is copied into ->name.
	132	* Will disappear.
	133	*/
	134	const char *typename;
1da177e4 LT	135	};
1da177e4 LT	136
0b8f1efa YL	137	struct timer_rand_state;
0b8f1efa YL	138	struct irq_2_iommu;
8fee5c36 IM	139	/**
8fee5c36 IM	140	* struct irq_desc - interrupt descriptor
2ed1cdcf	141	* @irq: interrupt number for this descriptor
078a55db YL	142	* @timer_rand_state: pointer to timer rand state struct
	143	* @kstat_irqs: irq stats per cpu
	144	* @irq_2_iommu: iommu with this irq
6a6de9ef TG	145	* @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()]
6a6de9ef TG	146	* @chip: low level interrupt hardware access
472900b8	147	* @msi_desc: MSI descriptor
6a6de9ef TG	148	* @handler_data: per-IRQ data for the irq_chip methods
	149	* @chip_data: platform-specific per-chip private data for the chip
	150	* methods, to allow shared chip implementations
8fee5c36 IM	151	* @action: the irq action chain
	152	* @status: status information
	153	* @depth: disable-depth, for nested irq_disable() calls
15a647eb	154	* @wake_depth: enable depth, for multiple set_irq_wake() callers
8fee5c36	155	* @irq_count: stats field to detect stalled irqs
5ac4d823	156	* @last_unhandled: aging timer for unhandled count
e262a7ba	157	* @irqs_unhandled: stats field for spurious unhandled interrupts
8fee5c36 IM	158	* @lock: locking for SMP
8fee5c36 IM	159	* @affinity: IRQ affinity on SMP
6a6de9ef	160	* @cpu: cpu index useful for balancing
8fee5c36	161	* @pending_mask: pending rebalanced interrupts
3aa551c9 TG	162	* @threads_active: number of irqaction threads currently running
3aa551c9 TG	163	* @wait_for_threads: wait queue for sync_irq to wait for threaded handlers
8fee5c36	164	* @dir: /proc/irq/ procfs entry
a460e745	165	* @name: flow handler name for /proc/interrupts output
1da177e4	166	*/
34ffdb72	167	struct irq_desc {
08678b08	168	unsigned int irq;
0b8f1efa YL	169	struct timer_rand_state *timer_rand_state;
0b8f1efa YL	170	unsigned int *kstat_irqs;
d7e51e66	171	#ifdef CONFIG_INTR_REMAP
0b8f1efa	172	struct irq_2_iommu *irq_2_iommu;
0b8f1efa	173	#endif
57a58a94	174	irq_flow_handler_t handle_irq;
6a6de9ef	175	struct irq_chip *chip;
5b912c10	176	struct msi_desc *msi_desc;
6a6de9ef	177	void *handler_data;
71d218b7 IM	178	void *chip_data;
	179	struct irqaction action; / IRQ action list */
	180	unsigned int status; /* IRQ status */
6a6de9ef	181
71d218b7	182	unsigned int depth; /* nested irq disables */
15a647eb	183	unsigned int wake_depth; /* nested wake enables */
71d218b7	184	unsigned int irq_count; /* For detecting broken IRQs */
4f27c00b	185	unsigned long last_unhandled; /* Aging timer for unhandled count */
e262a7ba	186	unsigned int irqs_unhandled;
71d218b7	187	spinlock_t lock;
a53da52f	188	#ifdef CONFIG_SMP
7f7ace0c	189	cpumask_var_t affinity;
6a6de9ef	190	unsigned int cpu;
8b8e8c1b	191	#ifdef CONFIG_GENERIC_PENDING_IRQ
7f7ace0c MT	192	cpumask_var_t pending_mask;
7f7ace0c MT	193	#endif
54d5d424	194	#endif
3aa551c9 TG	195	atomic_t threads_active;
3aa551c9 TG	196	wait_queue_head_t wait_for_threads;
4a733ee1	197	#ifdef CONFIG_PROC_FS
a460e745	198	struct proc_dir_entry *dir;
4a733ee1	199	#endif
a460e745	200	const char *name;
e729aa16	201	} ____cacheline_internodealigned_in_smp;
1da177e4	202
0b8f1efa YL	203	extern void arch_init_copy_chip_data(struct irq_desc *old_desc,
	204	struct irq_desc *desc, int cpu);
	205	extern void arch_free_chip_data(struct irq_desc old_desc, struct irq_desc desc);
9059d8fa	206
0b8f1efa	207	#ifndef CONFIG_SPARSE_IRQ
34ffdb72	208	extern struct irq_desc irq_desc[NR_IRQS];
f9af0e70	209	#else /* CONFIG_SPARSE_IRQ */
0b8f1efa	210	extern struct irq_desc move_irq_desc(struct irq_desc old_desc, int cpu);
d7e51e66	211	#endif /* CONFIG_SPARSE_IRQ */
0b8f1efa	212
f9af0e70	213	extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu);
0b8f1efa	214
48a1b10a YL	215	static inline struct irq_desc *
	216	irq_remap_to_desc(unsigned int irq, struct irq_desc *desc)
	217	{
	218	#ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
	219	return irq_to_desc(irq);
	220	#else
	221	return desc;
	222	#endif
c6b7674f TG	223	}
c6b7674f TG	224
34ffdb72 IM	225	/*
	226	* Migration helpers for obsolete names, they will go away:
	227	*/
6a6de9ef	228	#define hw_interrupt_type irq_chip
6a6de9ef	229	#define no_irq_type no_irq_chip
34ffdb72 IM	230	typedef struct irq_desc irq_desc_t;
	231
	232	/*
	233	* Pick up the arch-dependent methods:
	234	*/
	235	#include <asm/hw_irq.h>
1da177e4	236
06fcb0c6	237	extern int setup_irq(unsigned int irq, struct irqaction *new);
cbf94f06	238	extern void remove_irq(unsigned int irq, struct irqaction *act);
1da177e4 LT	239
1da177e4 LT	240	#ifdef CONFIG_GENERIC_HARDIRQS
06fcb0c6	241
54d5d424 AR	242	#ifdef CONFIG_SMP
54d5d424 AR	243
8b8e8c1b	244	#ifdef CONFIG_GENERIC_PENDING_IRQ
54d5d424	245
c777ac55	246	void move_native_irq(int irq);
e7b946e9	247	void move_masked_irq(int irq);
54d5d424	248
8b8e8c1b	249	#else /* CONFIG_GENERIC_PENDING_IRQ */
06fcb0c6 IM	250
	251	static inline void move_irq(int irq)
	252	{
	253	}
	254
	255	static inline void move_native_irq(int irq)
	256	{
	257	}
	258
e7b946e9 EB	259	static inline void move_masked_irq(int irq)
	260	{
	261	}
	262
06fcb0c6	263	#endif /* CONFIG_GENERIC_PENDING_IRQ */
54d5d424	264
06fcb0c6	265	#else /* CONFIG_SMP */
54d5d424	266
54d5d424	267	#define move_native_irq(x)
e7b946e9	268	#define move_masked_irq(x)
54d5d424	269
06fcb0c6	270	#endif /* CONFIG_SMP */
54d5d424	271
1da177e4	272	extern int no_irq_affinity;
1da177e4	273
950f4427 TG	274	static inline int irq_balancing_disabled(unsigned int irq)
950f4427 TG	275	{
08678b08 YL	276	struct irq_desc *desc;
	277
	278	desc = irq_to_desc(irq);
	279	return desc->status & IRQ_NO_BALANCING_MASK;
950f4427 TG	280	}
950f4427 TG	281
6a6de9ef	282	/* Handle irq action chains: */
bedd30d9	283	extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action);
6a6de9ef TG	284
	285	/*
	286	* Built-in IRQ handlers for various IRQ types,
	287	* callable via desc->chip->handle_irq()
	288	*/
ec701584 HH	289	extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
	290	extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
	291	extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
	292	extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
	293	extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
	294	extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
6a6de9ef	295
2e60bbb6	296	/*
6a6de9ef	297	* Monolithic do_IRQ implementation.
2e60bbb6	298	*/
af8c65b5	299	#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
ec701584	300	extern unsigned int __do_IRQ(unsigned int irq);
af8c65b5	301	#endif
2e60bbb6	302
dae86204 IM	303	/*
	304	* Architectures call this to let the generic IRQ layer
	305	* handle an interrupt. If the descriptor is attached to an
	306	* irqchip-style controller then we call the ->handle_irq() handler,
	307	* and it calls __do_IRQ() if it's attached to an irqtype-style controller.
	308	*/
46926b67	309	static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc)
dae86204	310	{
af8c65b5	311	#ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
7d12e780	312	desc->handle_irq(irq, desc);
af8c65b5	313	#else
dae86204	314	if (likely(desc->handle_irq))
7d12e780	315	desc->handle_irq(irq, desc);
dae86204	316	else
7d12e780	317	__do_IRQ(irq);
af8c65b5	318	#endif
dae86204 IM	319	}
dae86204 IM	320
46926b67 YL	321	static inline void generic_handle_irq(unsigned int irq)
	322	{
	323	generic_handle_irq_desc(irq, irq_to_desc(irq));
	324	}
	325
6a6de9ef	326	/* Handling of unhandled and spurious interrupts: */
34ffdb72	327	extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
bedd30d9	328	irqreturn_t action_ret);
1da177e4	329
a4633adc TG	330	/* Resending of interrupts :*/
	331	void check_irq_resend(struct irq_desc *desc, unsigned int irq);
	332
6a6de9ef TG	333	/* Enable/disable irq debugging output: */
	334	extern int noirqdebug_setup(char *str);
	335
	336	/* Checks whether the interrupt can be requested by request_irq(): */
	337	extern int can_request_irq(unsigned int irq, unsigned long irqflags);
	338
f8b5473f	339	/* Dummy irq-chip implementations: */
6a6de9ef	340	extern struct irq_chip no_irq_chip;
f8b5473f	341	extern struct irq_chip dummy_irq_chip;
6a6de9ef	342
145fc655 IM	343	extern void
	344	set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
	345	irq_flow_handler_t handle);
6a6de9ef	346	extern void
a460e745 IM	347	set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
	348	irq_flow_handler_t handle, const char *name);
	349
6a6de9ef	350	extern void
a460e745 IM	351	__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 IM	352	const char *name);
1da177e4	353
b019e573 KH	354	/* caller has locked the irq_desc and both params are valid */
	355	static inline void __set_irq_handler_unlocked(int irq,
	356	irq_flow_handler_t handler)
	357	{
08678b08 YL	358	struct irq_desc *desc;
	359
	360	desc = irq_to_desc(irq);
	361	desc->handle_irq = handler;
b019e573 KH	362	}
b019e573 KH	363
6a6de9ef TG	364	/*
	365	* Set a highlevel flow handler for a given IRQ:
	366	*/
	367	static inline void
57a58a94	368	set_irq_handler(unsigned int irq, irq_flow_handler_t handle)
6a6de9ef	369	{
a460e745	370	__set_irq_handler(irq, handle, 0, NULL);
6a6de9ef TG	371	}
	372
	373	/*
	374	* Set a highlevel chained flow handler for a given IRQ.
	375	* (a chained handler is automatically enabled and set to
	376	* IRQ_NOREQUEST and IRQ_NOPROBE)
	377	*/
	378	static inline void
	379	set_irq_chained_handler(unsigned int irq,
57a58a94	380	irq_flow_handler_t handle)
6a6de9ef	381	{
a460e745	382	__set_irq_handler(irq, handle, 1, NULL);
6a6de9ef TG	383	}
6a6de9ef TG	384
46f4f8f6 RB	385	extern void set_irq_noprobe(unsigned int irq);
	386	extern void set_irq_probe(unsigned int irq);
	387
3a16d713	388	/* Handle dynamic irq creation and destruction */
6d50bc26	389	extern unsigned int create_irq_nr(unsigned int irq_want);
3a16d713 EB	390	extern int create_irq(void);
	391	extern void destroy_irq(unsigned int irq);
	392
1f80025e EB	393	/* Test to see if a driver has successfully requested an irq */
	394	static inline int irq_has_action(unsigned int irq)
	395	{
08678b08	396	struct irq_desc *desc = irq_to_desc(irq);
1f80025e EB	397	return desc->action != NULL;
	398	}
	399
3a16d713 EB	400	/* Dynamic irq helper functions */
	401	extern void dynamic_irq_init(unsigned int irq);
	402	extern void dynamic_irq_cleanup(unsigned int irq);
dd87eb3a	403
3a16d713	404	/* Set/get chip/data for an IRQ: */
dd87eb3a TG	405	extern int set_irq_chip(unsigned int irq, struct irq_chip *chip);
	406	extern int set_irq_data(unsigned int irq, void *data);
	407	extern int set_irq_chip_data(unsigned int irq, void *data);
	408	extern int set_irq_type(unsigned int irq, unsigned int type);
5b912c10	409	extern int set_irq_msi(unsigned int irq, struct msi_desc *entry);
dd87eb3a	410
08678b08 YL	411	#define get_irq_chip(irq) (irq_to_desc(irq)->chip)
	412	#define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data)
	413	#define get_irq_data(irq) (irq_to_desc(irq)->handler_data)
	414	#define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc)
dd87eb3a	415
0b8f1efa YL	416	#define get_irq_desc_chip(desc) ((desc)->chip)
	417	#define get_irq_desc_chip_data(desc) ((desc)->chip_data)
	418	#define get_irq_desc_data(desc) ((desc)->handler_data)
	419	#define get_irq_desc_msi(desc) ((desc)->msi_desc)
	420
6a6de9ef	421	#endif /* CONFIG_GENERIC_HARDIRQS */
1da177e4	422
06fcb0c6	423	#endif /* !CONFIG_S390 */
1da177e4	424
7f7ace0c MT	425	#ifdef CONFIG_SMP
	426	/**
	427	* init_alloc_desc_masks - allocate cpumasks for irq_desc
	428	* @desc: pointer to irq_desc struct
802bf931	429	* @cpu: cpu which will be handling the cpumasks
7f7ace0c MT	430	* @boot: true if need bootmem
	431	*
	432	* Allocates affinity and pending_mask cpumask if required.
	433	* Returns true if successful (or not required).
	434	* Side effect: affinity has all bits set, pending_mask has all bits clear.
	435	*/
802bf931	436	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	437	bool boot)
7f7ace0c MT	438	{
802bf931 MT	439	int node;
802bf931 MT	440
7f7ace0c MT	441	if (boot) {
	442	alloc_bootmem_cpumask_var(&desc->affinity);
	443	cpumask_setall(desc->affinity);
	444
	445	#ifdef CONFIG_GENERIC_PENDING_IRQ
	446	alloc_bootmem_cpumask_var(&desc->pending_mask);
	447	cpumask_clear(desc->pending_mask);
	448	#endif
	449	return true;
	450	}
	451
802bf931 MT	452	node = cpu_to_node(cpu);
802bf931 MT	453
7f7ace0c MT	454	if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node))
	455	return false;
	456	cpumask_setall(desc->affinity);
	457
	458	#ifdef CONFIG_GENERIC_PENDING_IRQ
	459	if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) {
	460	free_cpumask_var(desc->affinity);
	461	return false;
	462	}
	463	cpumask_clear(desc->pending_mask);
	464	#endif
	465	return true;
	466	}
	467
	468	/**
	469	* init_copy_desc_masks - copy cpumasks for irq_desc
	470	* @old_desc: pointer to old irq_desc struct
	471	* @new_desc: pointer to new irq_desc struct
	472	*
	473	* Insures affinity and pending_masks are copied to new irq_desc.
	474	* If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the
	475	* irq_desc struct so the copy is redundant.
	476	*/
	477
	478	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	479	struct irq_desc *new_desc)
	480	{
	481	#ifdef CONFIG_CPUMASKS_OFFSTACK
	482	cpumask_copy(new_desc->affinity, old_desc->affinity);
	483
	484	#ifdef CONFIG_GENERIC_PENDING_IRQ
	485	cpumask_copy(new_desc->pending_mask, old_desc->pending_mask);
	486	#endif
	487	#endif
	488	}
	489
9756b15e YL	490	static inline void free_desc_masks(struct irq_desc *old_desc,
	491	struct irq_desc *new_desc)
	492	{
	493	free_cpumask_var(old_desc->affinity);
	494
	495	#ifdef CONFIG_GENERIC_PENDING_IRQ
	496	free_cpumask_var(old_desc->pending_mask);
	497	#endif
	498	}
	499
7f7ace0c MT	500	#else /* !CONFIG_SMP */
7f7ace0c MT	501
802bf931	502	static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu,
7f7ace0c MT	503	bool boot)
	504	{
	505	return true;
	506	}
	507
	508	static inline void init_copy_desc_masks(struct irq_desc *old_desc,
	509	struct irq_desc *new_desc)
	510	{
	511	}
	512
9756b15e YL	513	static inline void free_desc_masks(struct irq_desc *old_desc,
	514	struct irq_desc *new_desc)
	515	{
	516	}
7f7ace0c MT	517	#endif /* CONFIG_SMP */
7f7ace0c MT	518
06fcb0c6	519	#endif /* _LINUX_IRQ_H */