Commit | Line | Data |
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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
1da177e4 LT |
25 | |
26 | #include <asm/irq.h> | |
27 | #include <asm/ptrace.h> | |
7d12e780 | 28 | #include <asm/irq_regs.h> |
1da177e4 | 29 | |
57a58a94 | 30 | struct irq_desc; |
ec701584 | 31 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 32 | struct irq_desc *desc); |
57a58a94 DH |
33 | |
34 | ||
1da177e4 LT |
35 | /* |
36 | * IRQ line status. | |
6e213616 | 37 | * |
950f4427 | 38 | * Bits 0-7 are reserved for the IRQF_* bits in linux/interrupt.h |
6e213616 TG |
39 | * |
40 | * IRQ types | |
1da177e4 | 41 | */ |
6e213616 TG |
42 | #define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ |
43 | #define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ | |
44 | #define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ | |
45 | #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) | |
46 | #define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ | |
47 | #define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ | |
48 | #define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ | |
49 | #define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ | |
50 | ||
51 | /* Internal flags */ | |
950f4427 TG |
52 | #define IRQ_INPROGRESS 0x00000100 /* IRQ handler active - do not enter! */ |
53 | #define IRQ_DISABLED 0x00000200 /* IRQ disabled - do not enter! */ | |
54 | #define IRQ_PENDING 0x00000400 /* IRQ pending - replay on enable */ | |
55 | #define IRQ_REPLAY 0x00000800 /* IRQ has been replayed but not acked yet */ | |
56 | #define IRQ_AUTODETECT 0x00001000 /* IRQ is being autodetected */ | |
57 | #define IRQ_WAITING 0x00002000 /* IRQ not yet seen - for autodetection */ | |
58 | #define IRQ_LEVEL 0x00004000 /* IRQ level triggered */ | |
59 | #define IRQ_MASKED 0x00008000 /* IRQ masked - shouldn't be seen again */ | |
60 | #define IRQ_PER_CPU 0x00010000 /* IRQ is per CPU */ | |
61 | #define IRQ_NOPROBE 0x00020000 /* IRQ is not valid for probing */ | |
62 | #define IRQ_NOREQUEST 0x00040000 /* IRQ cannot be requested */ | |
63 | #define IRQ_NOAUTOEN 0x00080000 /* IRQ will not be enabled on request irq */ | |
d7e25f33 IM |
64 | #define IRQ_WAKEUP 0x00100000 /* IRQ triggers system wakeup */ |
65 | #define IRQ_MOVE_PENDING 0x00200000 /* need to re-target IRQ destination */ | |
66 | #define IRQ_NO_BALANCING 0x00400000 /* IRQ is excluded from balancing */ | |
1adb0850 | 67 | #define IRQ_SPURIOUS_DISABLED 0x00800000 /* IRQ was disabled by the spurious trap */ |
f6d87f4b TG |
68 | #define IRQ_MOVE_PCNTXT 0x01000000 /* IRQ migration from process context */ |
69 | #define IRQ_AFFINITY_SET 0x02000000 /* IRQ affinity was set from userspace*/ | |
0a0c5168 | 70 | #define IRQ_SUSPENDED 0x04000000 /* IRQ has gone through suspend sequence */ |
950f4427 | 71 | |
0d7012a9 | 72 | #ifdef CONFIG_IRQ_PER_CPU |
f26fdd59 | 73 | # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU) |
950f4427 | 74 | # define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
f26fdd59 KW |
75 | #else |
76 | # define CHECK_IRQ_PER_CPU(var) 0 | |
950f4427 | 77 | # define IRQ_NO_BALANCING_MASK IRQ_NO_BALANCING |
f26fdd59 | 78 | #endif |
1da177e4 | 79 | |
6a6de9ef | 80 | struct proc_dir_entry; |
5b912c10 | 81 | struct msi_desc; |
6a6de9ef | 82 | |
8fee5c36 | 83 | /** |
6a6de9ef | 84 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
85 | * |
86 | * @name: name for /proc/interrupts | |
87 | * @startup: start up the interrupt (defaults to ->enable if NULL) | |
88 | * @shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
89 | * @enable: enable the interrupt (defaults to chip->unmask if NULL) | |
90 | * @disable: disable the interrupt (defaults to chip->mask if NULL) | |
8fee5c36 IM |
91 | * @ack: start of a new interrupt |
92 | * @mask: mask an interrupt source | |
93 | * @mask_ack: ack and mask an interrupt source | |
94 | * @unmask: unmask an interrupt source | |
47c2a3aa IM |
95 | * @eoi: end of interrupt - chip level |
96 | * @end: end of interrupt - flow level | |
8fee5c36 IM |
97 | * @set_affinity: set the CPU affinity on SMP machines |
98 | * @retrigger: resend an IRQ to the CPU | |
99 | * @set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
100 | * @set_wake: enable/disable power-management wake-on of an IRQ | |
101 | * | |
102 | * @release: release function solely used by UML | |
6a6de9ef | 103 | * @typename: obsoleted by name, kept as migration helper |
1da177e4 | 104 | */ |
6a6de9ef TG |
105 | struct irq_chip { |
106 | const char *name; | |
71d218b7 IM |
107 | unsigned int (*startup)(unsigned int irq); |
108 | void (*shutdown)(unsigned int irq); | |
109 | void (*enable)(unsigned int irq); | |
110 | void (*disable)(unsigned int irq); | |
6a6de9ef | 111 | |
71d218b7 | 112 | void (*ack)(unsigned int irq); |
6a6de9ef TG |
113 | void (*mask)(unsigned int irq); |
114 | void (*mask_ack)(unsigned int irq); | |
115 | void (*unmask)(unsigned int irq); | |
47c2a3aa | 116 | void (*eoi)(unsigned int irq); |
6a6de9ef | 117 | |
71d218b7 | 118 | void (*end)(unsigned int irq); |
0de26520 RR |
119 | void (*set_affinity)(unsigned int irq, |
120 | const struct cpumask *dest); | |
c0ad90a3 | 121 | int (*retrigger)(unsigned int irq); |
6a6de9ef TG |
122 | int (*set_type)(unsigned int irq, unsigned int flow_type); |
123 | int (*set_wake)(unsigned int irq, unsigned int on); | |
c0ad90a3 | 124 | |
b77d6adc PBG |
125 | /* Currently used only by UML, might disappear one day.*/ |
126 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 127 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 128 | #endif |
6a6de9ef TG |
129 | /* |
130 | * For compatibility, ->typename is copied into ->name. | |
131 | * Will disappear. | |
132 | */ | |
133 | const char *typename; | |
1da177e4 LT |
134 | }; |
135 | ||
0b8f1efa YL |
136 | struct timer_rand_state; |
137 | struct irq_2_iommu; | |
8fee5c36 IM |
138 | /** |
139 | * struct irq_desc - interrupt descriptor | |
2ed1cdcf | 140 | * @irq: interrupt number for this descriptor |
078a55db YL |
141 | * @timer_rand_state: pointer to timer rand state struct |
142 | * @kstat_irqs: irq stats per cpu | |
143 | * @irq_2_iommu: iommu with this irq | |
6a6de9ef TG |
144 | * @handle_irq: highlevel irq-events handler [if NULL, __do_IRQ()] |
145 | * @chip: low level interrupt hardware access | |
472900b8 | 146 | * @msi_desc: MSI descriptor |
6a6de9ef TG |
147 | * @handler_data: per-IRQ data for the irq_chip methods |
148 | * @chip_data: platform-specific per-chip private data for the chip | |
149 | * methods, to allow shared chip implementations | |
8fee5c36 IM |
150 | * @action: the irq action chain |
151 | * @status: status information | |
152 | * @depth: disable-depth, for nested irq_disable() calls | |
15a647eb | 153 | * @wake_depth: enable depth, for multiple set_irq_wake() callers |
8fee5c36 | 154 | * @irq_count: stats field to detect stalled irqs |
5ac4d823 | 155 | * @last_unhandled: aging timer for unhandled count |
e262a7ba | 156 | * @irqs_unhandled: stats field for spurious unhandled interrupts |
8fee5c36 IM |
157 | * @lock: locking for SMP |
158 | * @affinity: IRQ affinity on SMP | |
6a6de9ef | 159 | * @cpu: cpu index useful for balancing |
8fee5c36 | 160 | * @pending_mask: pending rebalanced interrupts |
8fee5c36 | 161 | * @dir: /proc/irq/ procfs entry |
a460e745 | 162 | * @name: flow handler name for /proc/interrupts output |
1da177e4 | 163 | */ |
34ffdb72 | 164 | struct irq_desc { |
08678b08 | 165 | unsigned int irq; |
0b8f1efa YL |
166 | struct timer_rand_state *timer_rand_state; |
167 | unsigned int *kstat_irqs; | |
d7e51e66 | 168 | #ifdef CONFIG_INTR_REMAP |
0b8f1efa | 169 | struct irq_2_iommu *irq_2_iommu; |
0b8f1efa | 170 | #endif |
57a58a94 | 171 | irq_flow_handler_t handle_irq; |
6a6de9ef | 172 | struct irq_chip *chip; |
5b912c10 | 173 | struct msi_desc *msi_desc; |
6a6de9ef | 174 | void *handler_data; |
71d218b7 IM |
175 | void *chip_data; |
176 | struct irqaction *action; /* IRQ action list */ | |
177 | unsigned int status; /* IRQ status */ | |
6a6de9ef | 178 | |
71d218b7 | 179 | unsigned int depth; /* nested irq disables */ |
15a647eb | 180 | unsigned int wake_depth; /* nested wake enables */ |
71d218b7 | 181 | unsigned int irq_count; /* For detecting broken IRQs */ |
4f27c00b | 182 | unsigned long last_unhandled; /* Aging timer for unhandled count */ |
e262a7ba | 183 | unsigned int irqs_unhandled; |
71d218b7 | 184 | spinlock_t lock; |
a53da52f | 185 | #ifdef CONFIG_SMP |
7f7ace0c | 186 | cpumask_var_t affinity; |
6a6de9ef | 187 | unsigned int cpu; |
8b8e8c1b | 188 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
7f7ace0c MT |
189 | cpumask_var_t pending_mask; |
190 | #endif | |
54d5d424 | 191 | #endif |
4a733ee1 | 192 | #ifdef CONFIG_PROC_FS |
a460e745 | 193 | struct proc_dir_entry *dir; |
4a733ee1 | 194 | #endif |
a460e745 | 195 | const char *name; |
e729aa16 | 196 | } ____cacheline_internodealigned_in_smp; |
1da177e4 | 197 | |
0b8f1efa YL |
198 | extern void arch_init_copy_chip_data(struct irq_desc *old_desc, |
199 | struct irq_desc *desc, int cpu); | |
200 | extern void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc); | |
9059d8fa | 201 | |
0b8f1efa | 202 | #ifndef CONFIG_SPARSE_IRQ |
34ffdb72 | 203 | extern struct irq_desc irq_desc[NR_IRQS]; |
f9af0e70 | 204 | #else /* CONFIG_SPARSE_IRQ */ |
0b8f1efa | 205 | extern struct irq_desc *move_irq_desc(struct irq_desc *old_desc, int cpu); |
d7e51e66 | 206 | #endif /* CONFIG_SPARSE_IRQ */ |
0b8f1efa | 207 | |
f9af0e70 | 208 | extern struct irq_desc *irq_to_desc_alloc_cpu(unsigned int irq, int cpu); |
0b8f1efa | 209 | |
48a1b10a YL |
210 | static inline struct irq_desc * |
211 | irq_remap_to_desc(unsigned int irq, struct irq_desc *desc) | |
212 | { | |
213 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
214 | return irq_to_desc(irq); | |
215 | #else | |
216 | return desc; | |
217 | #endif | |
c6b7674f TG |
218 | } |
219 | ||
34ffdb72 IM |
220 | /* |
221 | * Migration helpers for obsolete names, they will go away: | |
222 | */ | |
6a6de9ef | 223 | #define hw_interrupt_type irq_chip |
6a6de9ef | 224 | #define no_irq_type no_irq_chip |
34ffdb72 IM |
225 | typedef struct irq_desc irq_desc_t; |
226 | ||
227 | /* | |
228 | * Pick up the arch-dependent methods: | |
229 | */ | |
230 | #include <asm/hw_irq.h> | |
1da177e4 | 231 | |
06fcb0c6 | 232 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 233 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
1da177e4 LT |
234 | |
235 | #ifdef CONFIG_GENERIC_HARDIRQS | |
06fcb0c6 | 236 | |
54d5d424 AR |
237 | #ifdef CONFIG_SMP |
238 | ||
8b8e8c1b | 239 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54d5d424 | 240 | |
c777ac55 | 241 | void move_native_irq(int irq); |
e7b946e9 | 242 | void move_masked_irq(int irq); |
54d5d424 | 243 | |
8b8e8c1b | 244 | #else /* CONFIG_GENERIC_PENDING_IRQ */ |
06fcb0c6 IM |
245 | |
246 | static inline void move_irq(int irq) | |
247 | { | |
248 | } | |
249 | ||
250 | static inline void move_native_irq(int irq) | |
251 | { | |
252 | } | |
253 | ||
e7b946e9 EB |
254 | static inline void move_masked_irq(int irq) |
255 | { | |
256 | } | |
257 | ||
06fcb0c6 | 258 | #endif /* CONFIG_GENERIC_PENDING_IRQ */ |
54d5d424 | 259 | |
06fcb0c6 | 260 | #else /* CONFIG_SMP */ |
54d5d424 | 261 | |
54d5d424 | 262 | #define move_native_irq(x) |
e7b946e9 | 263 | #define move_masked_irq(x) |
54d5d424 | 264 | |
06fcb0c6 | 265 | #endif /* CONFIG_SMP */ |
54d5d424 | 266 | |
1da177e4 | 267 | extern int no_irq_affinity; |
1da177e4 | 268 | |
950f4427 TG |
269 | static inline int irq_balancing_disabled(unsigned int irq) |
270 | { | |
08678b08 YL |
271 | struct irq_desc *desc; |
272 | ||
273 | desc = irq_to_desc(irq); | |
274 | return desc->status & IRQ_NO_BALANCING_MASK; | |
950f4427 TG |
275 | } |
276 | ||
6a6de9ef | 277 | /* Handle irq action chains: */ |
bedd30d9 | 278 | extern irqreturn_t handle_IRQ_event(unsigned int irq, struct irqaction *action); |
6a6de9ef TG |
279 | |
280 | /* | |
281 | * Built-in IRQ handlers for various IRQ types, | |
282 | * callable via desc->chip->handle_irq() | |
283 | */ | |
ec701584 HH |
284 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
285 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
286 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
287 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); | |
288 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
289 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); | |
6a6de9ef | 290 | |
2e60bbb6 | 291 | /* |
6a6de9ef | 292 | * Monolithic do_IRQ implementation. |
2e60bbb6 | 293 | */ |
af8c65b5 | 294 | #ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
ec701584 | 295 | extern unsigned int __do_IRQ(unsigned int irq); |
af8c65b5 | 296 | #endif |
2e60bbb6 | 297 | |
dae86204 IM |
298 | /* |
299 | * Architectures call this to let the generic IRQ layer | |
300 | * handle an interrupt. If the descriptor is attached to an | |
301 | * irqchip-style controller then we call the ->handle_irq() handler, | |
302 | * and it calls __do_IRQ() if it's attached to an irqtype-style controller. | |
303 | */ | |
46926b67 | 304 | static inline void generic_handle_irq_desc(unsigned int irq, struct irq_desc *desc) |
dae86204 | 305 | { |
af8c65b5 | 306 | #ifdef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ |
7d12e780 | 307 | desc->handle_irq(irq, desc); |
af8c65b5 | 308 | #else |
dae86204 | 309 | if (likely(desc->handle_irq)) |
7d12e780 | 310 | desc->handle_irq(irq, desc); |
dae86204 | 311 | else |
7d12e780 | 312 | __do_IRQ(irq); |
af8c65b5 | 313 | #endif |
dae86204 IM |
314 | } |
315 | ||
46926b67 YL |
316 | static inline void generic_handle_irq(unsigned int irq) |
317 | { | |
318 | generic_handle_irq_desc(irq, irq_to_desc(irq)); | |
319 | } | |
320 | ||
6a6de9ef | 321 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 322 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 323 | irqreturn_t action_ret); |
1da177e4 | 324 | |
a4633adc TG |
325 | /* Resending of interrupts :*/ |
326 | void check_irq_resend(struct irq_desc *desc, unsigned int irq); | |
327 | ||
6a6de9ef TG |
328 | /* Enable/disable irq debugging output: */ |
329 | extern int noirqdebug_setup(char *str); | |
330 | ||
331 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
332 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
333 | ||
f8b5473f | 334 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 335 | extern struct irq_chip no_irq_chip; |
f8b5473f | 336 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 337 | |
145fc655 IM |
338 | extern void |
339 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
340 | irq_flow_handler_t handle); | |
6a6de9ef | 341 | extern void |
a460e745 IM |
342 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
343 | irq_flow_handler_t handle, const char *name); | |
344 | ||
6a6de9ef | 345 | extern void |
a460e745 IM |
346 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
347 | const char *name); | |
1da177e4 | 348 | |
b019e573 KH |
349 | /* caller has locked the irq_desc and both params are valid */ |
350 | static inline void __set_irq_handler_unlocked(int irq, | |
351 | irq_flow_handler_t handler) | |
352 | { | |
08678b08 YL |
353 | struct irq_desc *desc; |
354 | ||
355 | desc = irq_to_desc(irq); | |
356 | desc->handle_irq = handler; | |
b019e573 KH |
357 | } |
358 | ||
6a6de9ef TG |
359 | /* |
360 | * Set a highlevel flow handler for a given IRQ: | |
361 | */ | |
362 | static inline void | |
57a58a94 | 363 | set_irq_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 364 | { |
a460e745 | 365 | __set_irq_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
366 | } |
367 | ||
368 | /* | |
369 | * Set a highlevel chained flow handler for a given IRQ. | |
370 | * (a chained handler is automatically enabled and set to | |
371 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
372 | */ | |
373 | static inline void | |
374 | set_irq_chained_handler(unsigned int irq, | |
57a58a94 | 375 | irq_flow_handler_t handle) |
6a6de9ef | 376 | { |
a460e745 | 377 | __set_irq_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
378 | } |
379 | ||
46f4f8f6 RB |
380 | extern void set_irq_noprobe(unsigned int irq); |
381 | extern void set_irq_probe(unsigned int irq); | |
382 | ||
3a16d713 | 383 | /* Handle dynamic irq creation and destruction */ |
6d50bc26 | 384 | extern unsigned int create_irq_nr(unsigned int irq_want); |
3a16d713 EB |
385 | extern int create_irq(void); |
386 | extern void destroy_irq(unsigned int irq); | |
387 | ||
1f80025e EB |
388 | /* Test to see if a driver has successfully requested an irq */ |
389 | static inline int irq_has_action(unsigned int irq) | |
390 | { | |
08678b08 | 391 | struct irq_desc *desc = irq_to_desc(irq); |
1f80025e EB |
392 | return desc->action != NULL; |
393 | } | |
394 | ||
3a16d713 EB |
395 | /* Dynamic irq helper functions */ |
396 | extern void dynamic_irq_init(unsigned int irq); | |
397 | extern void dynamic_irq_cleanup(unsigned int irq); | |
dd87eb3a | 398 | |
3a16d713 | 399 | /* Set/get chip/data for an IRQ: */ |
dd87eb3a TG |
400 | extern int set_irq_chip(unsigned int irq, struct irq_chip *chip); |
401 | extern int set_irq_data(unsigned int irq, void *data); | |
402 | extern int set_irq_chip_data(unsigned int irq, void *data); | |
403 | extern int set_irq_type(unsigned int irq, unsigned int type); | |
5b912c10 | 404 | extern int set_irq_msi(unsigned int irq, struct msi_desc *entry); |
dd87eb3a | 405 | |
08678b08 YL |
406 | #define get_irq_chip(irq) (irq_to_desc(irq)->chip) |
407 | #define get_irq_chip_data(irq) (irq_to_desc(irq)->chip_data) | |
408 | #define get_irq_data(irq) (irq_to_desc(irq)->handler_data) | |
409 | #define get_irq_msi(irq) (irq_to_desc(irq)->msi_desc) | |
dd87eb3a | 410 | |
0b8f1efa YL |
411 | #define get_irq_desc_chip(desc) ((desc)->chip) |
412 | #define get_irq_desc_chip_data(desc) ((desc)->chip_data) | |
413 | #define get_irq_desc_data(desc) ((desc)->handler_data) | |
414 | #define get_irq_desc_msi(desc) ((desc)->msi_desc) | |
415 | ||
6a6de9ef | 416 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 417 | |
06fcb0c6 | 418 | #endif /* !CONFIG_S390 */ |
1da177e4 | 419 | |
7f7ace0c MT |
420 | #ifdef CONFIG_SMP |
421 | /** | |
422 | * init_alloc_desc_masks - allocate cpumasks for irq_desc | |
423 | * @desc: pointer to irq_desc struct | |
802bf931 | 424 | * @cpu: cpu which will be handling the cpumasks |
7f7ace0c MT |
425 | * @boot: true if need bootmem |
426 | * | |
427 | * Allocates affinity and pending_mask cpumask if required. | |
428 | * Returns true if successful (or not required). | |
429 | * Side effect: affinity has all bits set, pending_mask has all bits clear. | |
430 | */ | |
802bf931 | 431 | static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu, |
7f7ace0c MT |
432 | bool boot) |
433 | { | |
802bf931 MT |
434 | int node; |
435 | ||
7f7ace0c MT |
436 | if (boot) { |
437 | alloc_bootmem_cpumask_var(&desc->affinity); | |
438 | cpumask_setall(desc->affinity); | |
439 | ||
440 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
441 | alloc_bootmem_cpumask_var(&desc->pending_mask); | |
442 | cpumask_clear(desc->pending_mask); | |
443 | #endif | |
444 | return true; | |
445 | } | |
446 | ||
802bf931 MT |
447 | node = cpu_to_node(cpu); |
448 | ||
7f7ace0c MT |
449 | if (!alloc_cpumask_var_node(&desc->affinity, GFP_ATOMIC, node)) |
450 | return false; | |
451 | cpumask_setall(desc->affinity); | |
452 | ||
453 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
454 | if (!alloc_cpumask_var_node(&desc->pending_mask, GFP_ATOMIC, node)) { | |
455 | free_cpumask_var(desc->affinity); | |
456 | return false; | |
457 | } | |
458 | cpumask_clear(desc->pending_mask); | |
459 | #endif | |
460 | return true; | |
461 | } | |
462 | ||
463 | /** | |
464 | * init_copy_desc_masks - copy cpumasks for irq_desc | |
465 | * @old_desc: pointer to old irq_desc struct | |
466 | * @new_desc: pointer to new irq_desc struct | |
467 | * | |
468 | * Insures affinity and pending_masks are copied to new irq_desc. | |
469 | * If !CONFIG_CPUMASKS_OFFSTACK the cpumasks are embedded in the | |
470 | * irq_desc struct so the copy is redundant. | |
471 | */ | |
472 | ||
473 | static inline void init_copy_desc_masks(struct irq_desc *old_desc, | |
474 | struct irq_desc *new_desc) | |
475 | { | |
476 | #ifdef CONFIG_CPUMASKS_OFFSTACK | |
477 | cpumask_copy(new_desc->affinity, old_desc->affinity); | |
478 | ||
479 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
480 | cpumask_copy(new_desc->pending_mask, old_desc->pending_mask); | |
481 | #endif | |
482 | #endif | |
483 | } | |
484 | ||
485 | #else /* !CONFIG_SMP */ | |
486 | ||
802bf931 | 487 | static inline bool init_alloc_desc_masks(struct irq_desc *desc, int cpu, |
7f7ace0c MT |
488 | bool boot) |
489 | { | |
490 | return true; | |
491 | } | |
492 | ||
493 | static inline void init_copy_desc_masks(struct irq_desc *old_desc, | |
494 | struct irq_desc *new_desc) | |
495 | { | |
496 | } | |
497 | ||
498 | #endif /* CONFIG_SMP */ | |
499 | ||
06fcb0c6 | 500 | #endif /* _LINUX_IRQ_H */ |