Commit | Line | Data |
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06fcb0c6 IM |
1 | #ifndef _LINUX_IRQ_H |
2 | #define _LINUX_IRQ_H | |
1da177e4 LT |
3 | |
4 | /* | |
5 | * Please do not include this file in generic code. There is currently | |
6 | * no requirement for any architecture to implement anything held | |
7 | * within this file. | |
8 | * | |
9 | * Thanks. --rmk | |
10 | */ | |
11 | ||
23f9b317 | 12 | #include <linux/smp.h> |
1da177e4 | 13 | |
06fcb0c6 | 14 | #ifndef CONFIG_S390 |
1da177e4 LT |
15 | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/cache.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/cpumask.h> | |
503e5763 | 20 | #include <linux/gfp.h> |
908dcecd | 21 | #include <linux/irqreturn.h> |
dd3a1db9 | 22 | #include <linux/irqnr.h> |
77904fd6 | 23 | #include <linux/errno.h> |
503e5763 | 24 | #include <linux/topology.h> |
3aa551c9 | 25 | #include <linux/wait.h> |
1da177e4 LT |
26 | |
27 | #include <asm/irq.h> | |
28 | #include <asm/ptrace.h> | |
7d12e780 | 29 | #include <asm/irq_regs.h> |
1da177e4 | 30 | |
ab7798ff | 31 | struct seq_file; |
57a58a94 | 32 | struct irq_desc; |
78129576 | 33 | struct irq_data; |
ec701584 | 34 | typedef void (*irq_flow_handler_t)(unsigned int irq, |
7d12e780 | 35 | struct irq_desc *desc); |
78129576 | 36 | typedef void (*irq_preflow_handler_t)(struct irq_data *data); |
57a58a94 | 37 | |
1da177e4 LT |
38 | /* |
39 | * IRQ line status. | |
6e213616 | 40 | * |
5d4d8fc9 TG |
41 | * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h |
42 | * | |
43 | * IRQ_TYPE_NONE - default, unspecified type | |
44 | * IRQ_TYPE_EDGE_RISING - rising edge triggered | |
45 | * IRQ_TYPE_EDGE_FALLING - falling edge triggered | |
46 | * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered | |
47 | * IRQ_TYPE_LEVEL_HIGH - high level triggered | |
48 | * IRQ_TYPE_LEVEL_LOW - low level triggered | |
49 | * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits | |
50 | * IRQ_TYPE_SENSE_MASK - Mask for all the above bits | |
51 | * IRQ_TYPE_PROBE - Special flag for probing in progress | |
52 | * | |
53 | * Bits which can be modified via irq_set/clear/modify_status_flags() | |
54 | * IRQ_LEVEL - Interrupt is level type. Will be also | |
55 | * updated in the code when the above trigger | |
56 | * bits are modified via set_irq_type() | |
57 | * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect | |
58 | * it from affinity setting | |
59 | * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing | |
60 | * IRQ_NOREQUEST - Interrupt cannot be requested via | |
61 | * request_irq() | |
62 | * IRQ_NOAUTOEN - Interrupt is not automatically enabled in | |
63 | * request/setup_irq() | |
64 | * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) | |
65 | * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context | |
66 | * IRQ_NESTED_TRHEAD - Interrupt nests into another thread | |
67 | * | |
68 | * Deprecated bits. They are kept updated as long as | |
69 | * CONFIG_GENERIC_HARDIRQS_NO_COMPAT is not set. Will go away soon. These bits | |
70 | * are internal state of the core code and if you really need to acces | |
71 | * them then talk to the genirq maintainer instead of hacking | |
72 | * something weird. | |
6e213616 | 73 | * |
1da177e4 | 74 | */ |
5d4d8fc9 TG |
75 | enum { |
76 | IRQ_TYPE_NONE = 0x00000000, | |
77 | IRQ_TYPE_EDGE_RISING = 0x00000001, | |
78 | IRQ_TYPE_EDGE_FALLING = 0x00000002, | |
79 | IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), | |
80 | IRQ_TYPE_LEVEL_HIGH = 0x00000004, | |
81 | IRQ_TYPE_LEVEL_LOW = 0x00000008, | |
82 | IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), | |
83 | IRQ_TYPE_SENSE_MASK = 0x0000000f, | |
84 | ||
85 | IRQ_TYPE_PROBE = 0x00000010, | |
86 | ||
87 | IRQ_LEVEL = (1 << 8), | |
88 | IRQ_PER_CPU = (1 << 9), | |
89 | IRQ_NOPROBE = (1 << 10), | |
90 | IRQ_NOREQUEST = (1 << 11), | |
91 | IRQ_NOAUTOEN = (1 << 12), | |
92 | IRQ_NO_BALANCING = (1 << 13), | |
93 | IRQ_MOVE_PCNTXT = (1 << 14), | |
94 | IRQ_NESTED_THREAD = (1 << 15), | |
5d4d8fc9 | 95 | }; |
950f4427 | 96 | |
44247184 TG |
97 | #define IRQF_MODIFY_MASK \ |
98 | (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ | |
872434d6 | 99 | IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \ |
6f91a52d | 100 | IRQ_PER_CPU | IRQ_NESTED_THREAD) |
44247184 | 101 | |
8f53f924 TG |
102 | #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) |
103 | ||
104 | static inline __deprecated bool CHECK_IRQ_PER_CPU(unsigned int status) | |
105 | { | |
106 | return status & IRQ_PER_CPU; | |
107 | } | |
1da177e4 | 108 | |
3b8249e7 TG |
109 | /* |
110 | * Return value for chip->irq_set_affinity() | |
111 | * | |
112 | * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity | |
113 | * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity | |
114 | */ | |
115 | enum { | |
116 | IRQ_SET_MASK_OK = 0, | |
117 | IRQ_SET_MASK_OK_NOCOPY, | |
118 | }; | |
119 | ||
5b912c10 | 120 | struct msi_desc; |
6a6de9ef | 121 | |
ff7dcd44 TG |
122 | /** |
123 | * struct irq_data - per irq and irq chip data passed down to chip functions | |
124 | * @irq: interrupt number | |
125 | * @node: node index useful for balancing | |
30398bf6 | 126 | * @state_use_accessors: status information for irq chip functions. |
91c49917 | 127 | * Use accessor functions to deal with it |
ff7dcd44 TG |
128 | * @chip: low level interrupt hardware access |
129 | * @handler_data: per-IRQ data for the irq_chip methods | |
130 | * @chip_data: platform-specific per-chip private data for the chip | |
131 | * methods, to allow shared chip implementations | |
132 | * @msi_desc: MSI descriptor | |
133 | * @affinity: IRQ affinity on SMP | |
ff7dcd44 TG |
134 | * |
135 | * The fields here need to overlay the ones in irq_desc until we | |
136 | * cleaned up the direct references and switched everything over to | |
137 | * irq_data. | |
138 | */ | |
139 | struct irq_data { | |
140 | unsigned int irq; | |
141 | unsigned int node; | |
91c49917 | 142 | unsigned int state_use_accessors; |
ff7dcd44 TG |
143 | struct irq_chip *chip; |
144 | void *handler_data; | |
145 | void *chip_data; | |
146 | struct msi_desc *msi_desc; | |
147 | #ifdef CONFIG_SMP | |
148 | cpumask_var_t affinity; | |
149 | #endif | |
ff7dcd44 TG |
150 | }; |
151 | ||
f230b6d5 TG |
152 | /* |
153 | * Bit masks for irq_data.state | |
154 | * | |
876dbd4c | 155 | * IRQD_TRIGGER_MASK - Mask for the trigger type bits |
f230b6d5 | 156 | * IRQD_SETAFFINITY_PENDING - Affinity setting is pending |
a005677b TG |
157 | * IRQD_NO_BALANCING - Balancing disabled for this IRQ |
158 | * IRQD_PER_CPU - Interrupt is per cpu | |
2bdd1055 | 159 | * IRQD_AFFINITY_SET - Interrupt affinity was set |
876dbd4c | 160 | * IRQD_LEVEL - Interrupt is level triggered |
7f94226f TG |
161 | * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup |
162 | * from suspend | |
e1ef8241 TG |
163 | * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process |
164 | * context | |
32f4125e TG |
165 | * IRQD_IRQ_DISABLED - Disabled state of the interrupt |
166 | * IRQD_IRQ_MASKED - Masked state of the interrupt | |
167 | * IRQD_IRQ_INPROGRESS - In progress state of the interrupt | |
f230b6d5 TG |
168 | */ |
169 | enum { | |
876dbd4c | 170 | IRQD_TRIGGER_MASK = 0xf, |
a005677b TG |
171 | IRQD_SETAFFINITY_PENDING = (1 << 8), |
172 | IRQD_NO_BALANCING = (1 << 10), | |
173 | IRQD_PER_CPU = (1 << 11), | |
2bdd1055 | 174 | IRQD_AFFINITY_SET = (1 << 12), |
876dbd4c | 175 | IRQD_LEVEL = (1 << 13), |
7f94226f | 176 | IRQD_WAKEUP_STATE = (1 << 14), |
e1ef8241 | 177 | IRQD_MOVE_PCNTXT = (1 << 15), |
801a0e9a | 178 | IRQD_IRQ_DISABLED = (1 << 16), |
32f4125e TG |
179 | IRQD_IRQ_MASKED = (1 << 17), |
180 | IRQD_IRQ_INPROGRESS = (1 << 18), | |
f230b6d5 TG |
181 | }; |
182 | ||
183 | static inline bool irqd_is_setaffinity_pending(struct irq_data *d) | |
184 | { | |
185 | return d->state_use_accessors & IRQD_SETAFFINITY_PENDING; | |
186 | } | |
187 | ||
a005677b TG |
188 | static inline bool irqd_is_per_cpu(struct irq_data *d) |
189 | { | |
190 | return d->state_use_accessors & IRQD_PER_CPU; | |
191 | } | |
192 | ||
193 | static inline bool irqd_can_balance(struct irq_data *d) | |
194 | { | |
195 | return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING)); | |
196 | } | |
197 | ||
2bdd1055 TG |
198 | static inline bool irqd_affinity_was_set(struct irq_data *d) |
199 | { | |
200 | return d->state_use_accessors & IRQD_AFFINITY_SET; | |
201 | } | |
202 | ||
ee38c04b TG |
203 | static inline void irqd_mark_affinity_was_set(struct irq_data *d) |
204 | { | |
205 | d->state_use_accessors |= IRQD_AFFINITY_SET; | |
206 | } | |
207 | ||
876dbd4c TG |
208 | static inline u32 irqd_get_trigger_type(struct irq_data *d) |
209 | { | |
210 | return d->state_use_accessors & IRQD_TRIGGER_MASK; | |
211 | } | |
212 | ||
213 | /* | |
214 | * Must only be called inside irq_chip.irq_set_type() functions. | |
215 | */ | |
216 | static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) | |
217 | { | |
218 | d->state_use_accessors &= ~IRQD_TRIGGER_MASK; | |
219 | d->state_use_accessors |= type & IRQD_TRIGGER_MASK; | |
220 | } | |
221 | ||
222 | static inline bool irqd_is_level_type(struct irq_data *d) | |
223 | { | |
224 | return d->state_use_accessors & IRQD_LEVEL; | |
225 | } | |
226 | ||
7f94226f TG |
227 | static inline bool irqd_is_wakeup_set(struct irq_data *d) |
228 | { | |
229 | return d->state_use_accessors & IRQD_WAKEUP_STATE; | |
230 | } | |
231 | ||
e1ef8241 TG |
232 | static inline bool irqd_can_move_in_process_context(struct irq_data *d) |
233 | { | |
234 | return d->state_use_accessors & IRQD_MOVE_PCNTXT; | |
235 | } | |
236 | ||
801a0e9a TG |
237 | static inline bool irqd_irq_disabled(struct irq_data *d) |
238 | { | |
239 | return d->state_use_accessors & IRQD_IRQ_DISABLED; | |
240 | } | |
241 | ||
32f4125e TG |
242 | static inline bool irqd_irq_masked(struct irq_data *d) |
243 | { | |
244 | return d->state_use_accessors & IRQD_IRQ_MASKED; | |
245 | } | |
246 | ||
247 | static inline bool irqd_irq_inprogress(struct irq_data *d) | |
248 | { | |
249 | return d->state_use_accessors & IRQD_IRQ_INPROGRESS; | |
250 | } | |
251 | ||
9cff60df TG |
252 | /* |
253 | * Functions for chained handlers which can be enabled/disabled by the | |
254 | * standard disable_irq/enable_irq calls. Must be called with | |
255 | * irq_desc->lock held. | |
256 | */ | |
257 | static inline void irqd_set_chained_irq_inprogress(struct irq_data *d) | |
258 | { | |
259 | d->state_use_accessors |= IRQD_IRQ_INPROGRESS; | |
260 | } | |
261 | ||
262 | static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d) | |
263 | { | |
264 | d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS; | |
265 | } | |
266 | ||
8fee5c36 | 267 | /** |
6a6de9ef | 268 | * struct irq_chip - hardware interrupt chip descriptor |
8fee5c36 IM |
269 | * |
270 | * @name: name for /proc/interrupts | |
f8822657 TG |
271 | * @startup: deprecated, replaced by irq_startup |
272 | * @shutdown: deprecated, replaced by irq_shutdown | |
273 | * @enable: deprecated, replaced by irq_enable | |
274 | * @disable: deprecated, replaced by irq_disable | |
275 | * @ack: deprecated, replaced by irq_ack | |
276 | * @mask: deprecated, replaced by irq_mask | |
277 | * @mask_ack: deprecated, replaced by irq_mask_ack | |
278 | * @unmask: deprecated, replaced by irq_unmask | |
279 | * @eoi: deprecated, replaced by irq_eoi | |
280 | * @end: deprecated, will go away with __do_IRQ() | |
281 | * @set_affinity: deprecated, replaced by irq_set_affinity | |
282 | * @retrigger: deprecated, replaced by irq_retrigger | |
283 | * @set_type: deprecated, replaced by irq_set_type | |
284 | * @set_wake: deprecated, replaced by irq_wake | |
285 | * @bus_lock: deprecated, replaced by irq_bus_lock | |
286 | * @bus_sync_unlock: deprecated, replaced by irq_bus_sync_unlock | |
8fee5c36 | 287 | * |
f8822657 TG |
288 | * @irq_startup: start up the interrupt (defaults to ->enable if NULL) |
289 | * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) | |
290 | * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) | |
291 | * @irq_disable: disable the interrupt | |
292 | * @irq_ack: start of a new interrupt | |
293 | * @irq_mask: mask an interrupt source | |
294 | * @irq_mask_ack: ack and mask an interrupt source | |
295 | * @irq_unmask: unmask an interrupt source | |
296 | * @irq_eoi: end of interrupt | |
297 | * @irq_set_affinity: set the CPU affinity on SMP machines | |
298 | * @irq_retrigger: resend an IRQ to the CPU | |
299 | * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ | |
300 | * @irq_set_wake: enable/disable power-management wake-on of an IRQ | |
301 | * @irq_bus_lock: function to lock access to slow bus (i2c) chips | |
302 | * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips | |
0fdb4b25 DD |
303 | * @irq_cpu_online: configure an interrupt source for a secondary CPU |
304 | * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU | |
ab7798ff | 305 | * @irq_print_chip: optional to print special chip info in show_interrupts |
2bff17ad | 306 | * @flags: chip specific flags |
70aedd24 | 307 | * |
8fee5c36 | 308 | * @release: release function solely used by UML |
1da177e4 | 309 | */ |
6a6de9ef TG |
310 | struct irq_chip { |
311 | const char *name; | |
f8822657 TG |
312 | unsigned int (*irq_startup)(struct irq_data *data); |
313 | void (*irq_shutdown)(struct irq_data *data); | |
314 | void (*irq_enable)(struct irq_data *data); | |
315 | void (*irq_disable)(struct irq_data *data); | |
316 | ||
317 | void (*irq_ack)(struct irq_data *data); | |
318 | void (*irq_mask)(struct irq_data *data); | |
319 | void (*irq_mask_ack)(struct irq_data *data); | |
320 | void (*irq_unmask)(struct irq_data *data); | |
321 | void (*irq_eoi)(struct irq_data *data); | |
322 | ||
323 | int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); | |
324 | int (*irq_retrigger)(struct irq_data *data); | |
325 | int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); | |
326 | int (*irq_set_wake)(struct irq_data *data, unsigned int on); | |
327 | ||
328 | void (*irq_bus_lock)(struct irq_data *data); | |
329 | void (*irq_bus_sync_unlock)(struct irq_data *data); | |
330 | ||
0fdb4b25 DD |
331 | void (*irq_cpu_online)(struct irq_data *data); |
332 | void (*irq_cpu_offline)(struct irq_data *data); | |
333 | ||
ab7798ff TG |
334 | void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); |
335 | ||
2bff17ad TG |
336 | unsigned long flags; |
337 | ||
b77d6adc PBG |
338 | /* Currently used only by UML, might disappear one day.*/ |
339 | #ifdef CONFIG_IRQ_RELEASE_METHOD | |
71d218b7 | 340 | void (*release)(unsigned int irq, void *dev_id); |
b77d6adc | 341 | #endif |
1da177e4 LT |
342 | }; |
343 | ||
d4d5e089 TG |
344 | /* |
345 | * irq_chip specific flags | |
346 | * | |
77694b40 TG |
347 | * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() |
348 | * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled | |
d209a699 | 349 | * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path |
b3d42232 TG |
350 | * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks |
351 | * when irq enabled | |
d4d5e089 TG |
352 | */ |
353 | enum { | |
354 | IRQCHIP_SET_TYPE_MASKED = (1 << 0), | |
77694b40 | 355 | IRQCHIP_EOI_IF_HANDLED = (1 << 1), |
d209a699 | 356 | IRQCHIP_MASK_ON_SUSPEND = (1 << 2), |
b3d42232 | 357 | IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), |
d4d5e089 TG |
358 | }; |
359 | ||
e144710b TG |
360 | /* This include will go away once we isolated irq_desc usage to core code */ |
361 | #include <linux/irqdesc.h> | |
0b8f1efa | 362 | |
34ffdb72 IM |
363 | /* |
364 | * Pick up the arch-dependent methods: | |
365 | */ | |
366 | #include <asm/hw_irq.h> | |
1da177e4 | 367 | |
b683de2b TG |
368 | #ifndef NR_IRQS_LEGACY |
369 | # define NR_IRQS_LEGACY 0 | |
370 | #endif | |
371 | ||
1318a481 TG |
372 | #ifndef ARCH_IRQ_INIT_FLAGS |
373 | # define ARCH_IRQ_INIT_FLAGS 0 | |
374 | #endif | |
375 | ||
c1594b77 | 376 | #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS |
1318a481 | 377 | |
e144710b | 378 | struct irqaction; |
06fcb0c6 | 379 | extern int setup_irq(unsigned int irq, struct irqaction *new); |
cbf94f06 | 380 | extern void remove_irq(unsigned int irq, struct irqaction *act); |
1da177e4 | 381 | |
0fdb4b25 DD |
382 | extern void irq_cpu_online(void); |
383 | extern void irq_cpu_offline(void); | |
c2d0c555 | 384 | extern int __irq_set_affinity_locked(struct irq_data *data, const struct cpumask *cpumask); |
0fdb4b25 | 385 | |
1da177e4 | 386 | #ifdef CONFIG_GENERIC_HARDIRQS |
06fcb0c6 | 387 | |
3a3856d0 | 388 | #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) |
a439520f TG |
389 | void irq_move_irq(struct irq_data *data); |
390 | void irq_move_masked_irq(struct irq_data *data); | |
e144710b | 391 | #else |
a439520f TG |
392 | static inline void irq_move_irq(struct irq_data *data) { } |
393 | static inline void irq_move_masked_irq(struct irq_data *data) { } | |
e144710b | 394 | #endif |
54d5d424 | 395 | |
1da177e4 | 396 | extern int no_irq_affinity; |
1da177e4 | 397 | |
6a6de9ef TG |
398 | /* |
399 | * Built-in IRQ handlers for various IRQ types, | |
bebd04cc | 400 | * callable via desc->handle_irq() |
6a6de9ef | 401 | */ |
ec701584 HH |
402 | extern void handle_level_irq(unsigned int irq, struct irq_desc *desc); |
403 | extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc); | |
404 | extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc); | |
0521c8fb | 405 | extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc); |
ec701584 HH |
406 | extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc); |
407 | extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc); | |
408 | extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc); | |
31b47cf7 | 409 | extern void handle_nested_irq(unsigned int irq); |
6a6de9ef | 410 | |
6a6de9ef | 411 | /* Handling of unhandled and spurious interrupts: */ |
34ffdb72 | 412 | extern void note_interrupt(unsigned int irq, struct irq_desc *desc, |
bedd30d9 | 413 | irqreturn_t action_ret); |
1da177e4 | 414 | |
a4633adc | 415 | |
6a6de9ef TG |
416 | /* Enable/disable irq debugging output: */ |
417 | extern int noirqdebug_setup(char *str); | |
418 | ||
419 | /* Checks whether the interrupt can be requested by request_irq(): */ | |
420 | extern int can_request_irq(unsigned int irq, unsigned long irqflags); | |
421 | ||
f8b5473f | 422 | /* Dummy irq-chip implementations: */ |
6a6de9ef | 423 | extern struct irq_chip no_irq_chip; |
f8b5473f | 424 | extern struct irq_chip dummy_irq_chip; |
6a6de9ef | 425 | |
145fc655 | 426 | extern void |
3836ca08 | 427 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, |
a460e745 IM |
428 | irq_flow_handler_t handle, const char *name); |
429 | ||
3836ca08 TG |
430 | static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip, |
431 | irq_flow_handler_t handle) | |
432 | { | |
433 | irq_set_chip_and_handler_name(irq, chip, handle, NULL); | |
434 | } | |
435 | ||
6a6de9ef | 436 | extern void |
3836ca08 | 437 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
a460e745 | 438 | const char *name); |
1da177e4 | 439 | |
6a6de9ef | 440 | static inline void |
3836ca08 | 441 | irq_set_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 442 | { |
3836ca08 | 443 | __irq_set_handler(irq, handle, 0, NULL); |
6a6de9ef TG |
444 | } |
445 | ||
446 | /* | |
447 | * Set a highlevel chained flow handler for a given IRQ. | |
448 | * (a chained handler is automatically enabled and set to | |
449 | * IRQ_NOREQUEST and IRQ_NOPROBE) | |
450 | */ | |
451 | static inline void | |
3836ca08 | 452 | irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) |
6a6de9ef | 453 | { |
3836ca08 | 454 | __irq_set_handler(irq, handle, 1, NULL); |
6a6de9ef TG |
455 | } |
456 | ||
44247184 TG |
457 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); |
458 | ||
459 | static inline void irq_set_status_flags(unsigned int irq, unsigned long set) | |
460 | { | |
461 | irq_modify_status(irq, 0, set); | |
462 | } | |
463 | ||
464 | static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) | |
465 | { | |
466 | irq_modify_status(irq, clr, 0); | |
467 | } | |
468 | ||
a0cd9ca2 | 469 | static inline void irq_set_noprobe(unsigned int irq) |
44247184 TG |
470 | { |
471 | irq_modify_status(irq, 0, IRQ_NOPROBE); | |
472 | } | |
473 | ||
a0cd9ca2 | 474 | static inline void irq_set_probe(unsigned int irq) |
44247184 TG |
475 | { |
476 | irq_modify_status(irq, IRQ_NOPROBE, 0); | |
477 | } | |
46f4f8f6 | 478 | |
6f91a52d TG |
479 | static inline void irq_set_nested_thread(unsigned int irq, bool nest) |
480 | { | |
481 | if (nest) | |
482 | irq_set_status_flags(irq, IRQ_NESTED_THREAD); | |
483 | else | |
484 | irq_clear_status_flags(irq, IRQ_NESTED_THREAD); | |
485 | } | |
486 | ||
3a16d713 | 487 | /* Handle dynamic irq creation and destruction */ |
d047f53a | 488 | extern unsigned int create_irq_nr(unsigned int irq_want, int node); |
3a16d713 EB |
489 | extern int create_irq(void); |
490 | extern void destroy_irq(unsigned int irq); | |
491 | ||
b7b29338 TG |
492 | /* |
493 | * Dynamic irq helper functions. Obsolete. Use irq_alloc_desc* and | |
494 | * irq_free_desc instead. | |
495 | */ | |
3a16d713 | 496 | extern void dynamic_irq_cleanup(unsigned int irq); |
b7b29338 TG |
497 | static inline void dynamic_irq_init(unsigned int irq) |
498 | { | |
499 | dynamic_irq_cleanup(irq); | |
500 | } | |
dd87eb3a | 501 | |
3a16d713 | 502 | /* Set/get chip/data for an IRQ: */ |
a0cd9ca2 TG |
503 | extern int irq_set_chip(unsigned int irq, struct irq_chip *chip); |
504 | extern int irq_set_handler_data(unsigned int irq, void *data); | |
505 | extern int irq_set_chip_data(unsigned int irq, void *data); | |
506 | extern int irq_set_irq_type(unsigned int irq, unsigned int type); | |
507 | extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); | |
f303a6dd | 508 | extern struct irq_data *irq_get_irq_data(unsigned int irq); |
dd87eb3a | 509 | |
a0cd9ca2 | 510 | static inline struct irq_chip *irq_get_chip(unsigned int irq) |
f303a6dd TG |
511 | { |
512 | struct irq_data *d = irq_get_irq_data(irq); | |
513 | return d ? d->chip : NULL; | |
514 | } | |
515 | ||
516 | static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) | |
517 | { | |
518 | return d->chip; | |
519 | } | |
520 | ||
a0cd9ca2 | 521 | static inline void *irq_get_chip_data(unsigned int irq) |
f303a6dd TG |
522 | { |
523 | struct irq_data *d = irq_get_irq_data(irq); | |
524 | return d ? d->chip_data : NULL; | |
525 | } | |
526 | ||
527 | static inline void *irq_data_get_irq_chip_data(struct irq_data *d) | |
528 | { | |
529 | return d->chip_data; | |
530 | } | |
531 | ||
a0cd9ca2 | 532 | static inline void *irq_get_handler_data(unsigned int irq) |
f303a6dd TG |
533 | { |
534 | struct irq_data *d = irq_get_irq_data(irq); | |
535 | return d ? d->handler_data : NULL; | |
536 | } | |
537 | ||
a0cd9ca2 | 538 | static inline void *irq_data_get_irq_handler_data(struct irq_data *d) |
f303a6dd TG |
539 | { |
540 | return d->handler_data; | |
541 | } | |
542 | ||
a0cd9ca2 | 543 | static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) |
f303a6dd TG |
544 | { |
545 | struct irq_data *d = irq_get_irq_data(irq); | |
546 | return d ? d->msi_desc : NULL; | |
547 | } | |
548 | ||
549 | static inline struct msi_desc *irq_data_get_msi(struct irq_data *d) | |
550 | { | |
551 | return d->msi_desc; | |
552 | } | |
553 | ||
1f5a5b87 TG |
554 | int irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node); |
555 | void irq_free_descs(unsigned int irq, unsigned int cnt); | |
06f6c339 | 556 | int irq_reserve_irqs(unsigned int from, unsigned int cnt); |
1f5a5b87 TG |
557 | |
558 | static inline int irq_alloc_desc(int node) | |
559 | { | |
560 | return irq_alloc_descs(-1, 0, 1, node); | |
561 | } | |
562 | ||
563 | static inline int irq_alloc_desc_at(unsigned int at, int node) | |
564 | { | |
565 | return irq_alloc_descs(at, at, 1, node); | |
566 | } | |
567 | ||
568 | static inline int irq_alloc_desc_from(unsigned int from, int node) | |
569 | { | |
570 | return irq_alloc_descs(-1, from, 1, node); | |
571 | } | |
572 | ||
573 | static inline void irq_free_desc(unsigned int irq) | |
574 | { | |
575 | irq_free_descs(irq, 1); | |
576 | } | |
577 | ||
639bd12f PM |
578 | static inline int irq_reserve_irq(unsigned int irq) |
579 | { | |
580 | return irq_reserve_irqs(irq, 1); | |
581 | } | |
582 | ||
6a6de9ef | 583 | #endif /* CONFIG_GENERIC_HARDIRQS */ |
1da177e4 | 584 | |
06fcb0c6 | 585 | #endif /* !CONFIG_S390 */ |
1da177e4 | 586 | |
06fcb0c6 | 587 | #endif /* _LINUX_IRQ_H */ |