Merge tag 'x86_asm_for_v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[linux-block.git] / include / linux / iommu.h
CommitLineData
45051539 1/* SPDX-License-Identifier: GPL-2.0-only */
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2/*
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <joerg.roedel@amd.com>
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5 */
6
7#ifndef __LINUX_IOMMU_H
8#define __LINUX_IOMMU_H
9
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10#include <linux/scatterlist.h>
11#include <linux/device.h>
12#include <linux/types.h>
74315ccc 13#include <linux/errno.h>
9a08d376 14#include <linux/err.h>
d0f60a44 15#include <linux/of.h>
808be0aa 16#include <linux/ioasid.h>
4e32348b 17#include <uapi/linux/iommu.h>
74315ccc 18
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19#define IOMMU_READ (1 << 0)
20#define IOMMU_WRITE (1 << 1)
21#define IOMMU_CACHE (1 << 2) /* DMA cache coherency */
a720b41c 22#define IOMMU_NOEXEC (1 << 3)
31e6850e 23#define IOMMU_MMIO (1 << 4) /* e.g. things like MSI doorbells */
579b2a65 24/*
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25 * Where the bus hardware includes a privilege level as part of its access type
26 * markings, and certain devices are capable of issuing transactions marked as
27 * either 'supervisor' or 'user', the IOMMU_PRIV flag requests that the other
28 * given permission flags only apply to accesses at the higher privilege level,
29 * and that unprivileged transactions should have as little access as possible.
30 * This would usually imply the same permissions as kernel mappings on the CPU,
31 * if the IOMMU page table format is equivalent.
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32 */
33#define IOMMU_PRIV (1 << 5)
4a77a6cf 34
905d66c1 35struct iommu_ops;
d72e31c9 36struct iommu_group;
ff21776d 37struct bus_type;
4a77a6cf 38struct device;
4f3f8d9d 39struct iommu_domain;
9a630a4b 40struct iommu_domain_ops;
ba1eabfa 41struct notifier_block;
26b25a2b 42struct iommu_sva;
4e32348b 43struct iommu_fault_event;
46983fcd 44struct iommu_dma_cookie;
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45
46/* iommu fault flags */
47#define IOMMU_FAULT_READ 0x0
48#define IOMMU_FAULT_WRITE 0x1
49
50typedef int (*iommu_fault_handler_t)(struct iommu_domain *,
77ca2332 51 struct device *, unsigned long, int, void *);
4e32348b 52typedef int (*iommu_dev_fault_handler_t)(struct iommu_fault *, void *);
4a77a6cf 53
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54struct iommu_domain_geometry {
55 dma_addr_t aperture_start; /* First address that can be mapped */
56 dma_addr_t aperture_end; /* Last address that can be mapped */
57 bool force_aperture; /* DMA only allowed in mappable range? */
58};
59
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60/* Domain feature flags */
61#define __IOMMU_DOMAIN_PAGING (1U << 0) /* Support for iommu_map/unmap */
62#define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
63 implementation */
64#define __IOMMU_DOMAIN_PT (1U << 2) /* Domain is identity mapped */
bf3aed46 65#define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */
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66
67/*
68 * This are the possible domain-types
69 *
70 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
71 * devices
72 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
73 * IOMMU_DOMAIN_UNMANAGED - DMA mappings managed by IOMMU-API user, used
74 * for VMs
75 * IOMMU_DOMAIN_DMA - Internally used for DMA-API implementations.
76 * This flag allows IOMMU drivers to implement
77 * certain optimizations for these domains
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78 * IOMMU_DOMAIN_DMA_FQ - As above, but definitely using batched TLB
79 * invalidation.
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80 */
81#define IOMMU_DOMAIN_BLOCKED (0U)
82#define IOMMU_DOMAIN_IDENTITY (__IOMMU_DOMAIN_PT)
83#define IOMMU_DOMAIN_UNMANAGED (__IOMMU_DOMAIN_PAGING)
84#define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING | \
85 __IOMMU_DOMAIN_DMA_API)
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86#define IOMMU_DOMAIN_DMA_FQ (__IOMMU_DOMAIN_PAGING | \
87 __IOMMU_DOMAIN_DMA_API | \
88 __IOMMU_DOMAIN_DMA_FQ)
8539c7c1 89
4a77a6cf 90struct iommu_domain {
8539c7c1 91 unsigned type;
9a630a4b 92 const struct iommu_domain_ops *ops;
d16e0faa 93 unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */
4f3f8d9d 94 iommu_fault_handler_t handler;
77ca2332 95 void *handler_token;
0ff64f80 96 struct iommu_domain_geometry geometry;
46983fcd 97 struct iommu_dma_cookie *iova_cookie;
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98};
99
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100static inline bool iommu_is_dma_domain(struct iommu_domain *domain)
101{
102 return domain->type & __IOMMU_DOMAIN_DMA_API;
103}
104
1aed0748 105enum iommu_cap {
f78dc1da 106 IOMMU_CAP_CACHE_COHERENCY, /* IOMMU_CACHE is supported */
1aed0748 107 IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */
c4986649 108 IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */
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109 IOMMU_CAP_PRE_BOOT_PROTECTION, /* Firmware says it used the IOMMU for
110 DMA protection and we should too */
1aed0748 111};
dbb9fd86 112
d30ddcaa 113/* These are the possible reserved region types */
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114enum iommu_resv_type {
115 /* Memory regions which must be mapped 1:1 at all times */
116 IOMMU_RESV_DIRECT,
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117 /*
118 * Memory regions which are advertised to be 1:1 but are
119 * commonly considered relaxable in some conditions,
120 * for instance in device assignment use case (USB, Graphics)
121 */
122 IOMMU_RESV_DIRECT_RELAXABLE,
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123 /* Arbitrary "never map this or give it to a device" address ranges */
124 IOMMU_RESV_RESERVED,
125 /* Hardware MSI region (untranslated) */
126 IOMMU_RESV_MSI,
127 /* Software-managed MSI translation window */
128 IOMMU_RESV_SW_MSI,
129};
d30ddcaa 130
a1015c2b 131/**
e5b5234a 132 * struct iommu_resv_region - descriptor for a reserved memory region
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133 * @list: Linked list pointers
134 * @start: System physical start address of the region
135 * @length: Length of the region in bytes
136 * @prot: IOMMU Protection flags (READ/WRITE/...)
d30ddcaa 137 * @type: Type of the reserved region
3b7e2482 138 * @free: Callback to free associated memory allocations
a1015c2b 139 */
e5b5234a 140struct iommu_resv_region {
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141 struct list_head list;
142 phys_addr_t start;
143 size_t length;
144 int prot;
9d3a4de4 145 enum iommu_resv_type type;
3b7e2482 146 void (*free)(struct device *dev, struct iommu_resv_region *region);
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147};
148
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149struct iommu_iort_rmr_data {
150 struct iommu_resv_region rr;
151
152 /* Stream IDs associated with IORT RMR entry */
153 const u32 *sids;
154 u32 num_sids;
155};
156
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157/**
158 * enum iommu_dev_features - Per device IOMMU features
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159 * @IOMMU_DEV_FEAT_SVA: Shared Virtual Addresses
160 * @IOMMU_DEV_FEAT_IOPF: I/O Page Faults such as PRI or Stall. Generally
161 * enabling %IOMMU_DEV_FEAT_SVA requires
162 * %IOMMU_DEV_FEAT_IOPF, but some devices manage I/O Page
163 * Faults themselves instead of relying on the IOMMU. When
164 * supported, this feature must be enabled before and
165 * disabled after %IOMMU_DEV_FEAT_SVA.
166 *
309c56e8 167 * Device drivers enable a feature using iommu_dev_enable_feature().
34b48c70 168 */
a3a19592 169enum iommu_dev_features {
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170 IOMMU_DEV_FEAT_SVA,
171 IOMMU_DEV_FEAT_IOPF,
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172};
173
174#define IOMMU_PASID_INVALID (-1U)
175
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176#ifdef CONFIG_IOMMU_API
177
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178/**
179 * struct iommu_iotlb_gather - Range information for a pending IOTLB flush
180 *
181 * @start: IOVA representing the start of the range to be flushed
862c3715 182 * @end: IOVA representing the end of the range to be flushed (inclusive)
a7d20dc1 183 * @pgsize: The interval at which to perform the flush
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184 * @freelist: Removed pages to free after sync
185 * @queued: Indicates that the flush will be queued
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186 *
187 * This structure is intended to be updated by multiple calls to the
188 * ->unmap() function in struct iommu_ops before eventually being passed
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189 * into ->iotlb_sync(). Drivers can add pages to @freelist to be freed after
190 * ->iotlb_sync() or ->iotlb_flush_all() have cleared all cached references to
191 * them. @queued is set to indicate when ->iotlb_flush_all() will be called
192 * later instead of ->iotlb_sync(), so drivers may optimise accordingly.
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193 */
194struct iommu_iotlb_gather {
195 unsigned long start;
196 unsigned long end;
197 size_t pgsize;
87f60cc6 198 struct list_head freelist;
7a7c5bad 199 bool queued;
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200};
201
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202/**
203 * struct iommu_ops - iommu ops and capabilities
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204 * @capable: check capability
205 * @domain_alloc: allocate iommu domain
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206 * @probe_device: Add device to iommu driver handling
207 * @release_device: Remove device from iommu driver handling
208 * @probe_finalize: Do final setup work after the device is added to an IOMMU
209 * group and attached to the groups domain
0d9bacb6 210 * @device_group: find iommu group for a particular device
e5b5234a 211 * @get_resv_regions: Request list of reserved regions for a device
d0f60a44 212 * @of_xlate: add OF master IDs to iommu grouping
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213 * @is_attach_deferred: Check if domain attach should be deferred from iommu
214 * driver init to device driver init (default no)
28394501 215 * @dev_enable/disable_feat: per device entries to enable/disable
a3a19592 216 * iommu specific features.
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217 * @sva_bind: Bind process address space to device
218 * @sva_unbind: Unbind process address space from device
219 * @sva_get_pasid: Get PASID associated to a SVA handle
bf3255b3 220 * @page_response: handle page request response
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221 * @def_domain_type: device default domain type, return value:
222 * - IOMMU_DOMAIN_IDENTITY: must use an identity domain
223 * - IOMMU_DOMAIN_DMA: must use a dma domain
224 * - 0: use the default setting
9a630a4b 225 * @default_domain_ops: the default ops for domains
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226 * @pgsize_bitmap: bitmap of all possible supported page sizes
227 * @owner: Driver module providing these ops
7d3002cc 228 */
4a77a6cf 229struct iommu_ops {
359ad157 230 bool (*capable)(struct device *dev, enum iommu_cap);
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231
232 /* Domain allocation and freeing by the iommu driver */
8539c7c1 233 struct iommu_domain *(*domain_alloc)(unsigned iommu_domain_type);
938c4709 234
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235 struct iommu_device *(*probe_device)(struct device *dev);
236 void (*release_device)(struct device *dev);
237 void (*probe_finalize)(struct device *dev);
46c6b2bc 238 struct iommu_group *(*device_group)(struct device *dev);
d7787d57 239
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240 /* Request/Free a list of reserved regions for a device */
241 void (*get_resv_regions)(struct device *dev, struct list_head *list);
a1015c2b 242
d0f60a44 243 int (*of_xlate)(struct device *dev, struct of_phandle_args *args);
41bb23e7 244 bool (*is_attach_deferred)(struct device *dev);
d0f60a44 245
a3a19592 246 /* Per device IOMMU features */
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247 int (*dev_enable_feat)(struct device *dev, enum iommu_dev_features f);
248 int (*dev_disable_feat)(struct device *dev, enum iommu_dev_features f);
249
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250 struct iommu_sva *(*sva_bind)(struct device *dev, struct mm_struct *mm,
251 void *drvdata);
252 void (*sva_unbind)(struct iommu_sva *handle);
c7b6bac9 253 u32 (*sva_get_pasid)(struct iommu_sva *handle);
26b25a2b 254
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255 int (*page_response)(struct device *dev,
256 struct iommu_fault_event *evt,
257 struct iommu_page_response *msg);
258
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259 int (*def_domain_type)(struct device *dev);
260
9a630a4b 261 const struct iommu_domain_ops *default_domain_ops;
7d3002cc 262 unsigned long pgsize_bitmap;
25f003de 263 struct module *owner;
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264};
265
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266/**
267 * struct iommu_domain_ops - domain specific operations
268 * @attach_dev: attach an iommu domain to a device
269 * @detach_dev: detach an iommu domain from a device
270 * @map: map a physically contiguous memory region to an iommu domain
271 * @map_pages: map a physically contiguous set of pages of the same size to
272 * an iommu domain.
273 * @unmap: unmap a physically contiguous memory region from an iommu domain
274 * @unmap_pages: unmap a number of pages of the same size from an iommu domain
275 * @flush_iotlb_all: Synchronously flush all hardware TLBs for this domain
276 * @iotlb_sync_map: Sync mappings created recently using @map to the hardware
277 * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush
278 * queue
279 * @iova_to_phys: translate iova to physical address
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280 * @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE,
281 * including no-snoop TLPs on PCIe or other platform
282 * specific mechanisms.
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283 * @enable_nesting: Enable nesting
284 * @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*)
285 * @free: Release the domain after use.
286 */
287struct iommu_domain_ops {
288 int (*attach_dev)(struct iommu_domain *domain, struct device *dev);
289 void (*detach_dev)(struct iommu_domain *domain, struct device *dev);
290
291 int (*map)(struct iommu_domain *domain, unsigned long iova,
292 phys_addr_t paddr, size_t size, int prot, gfp_t gfp);
293 int (*map_pages)(struct iommu_domain *domain, unsigned long iova,
294 phys_addr_t paddr, size_t pgsize, size_t pgcount,
295 int prot, gfp_t gfp, size_t *mapped);
296 size_t (*unmap)(struct iommu_domain *domain, unsigned long iova,
297 size_t size, struct iommu_iotlb_gather *iotlb_gather);
298 size_t (*unmap_pages)(struct iommu_domain *domain, unsigned long iova,
299 size_t pgsize, size_t pgcount,
300 struct iommu_iotlb_gather *iotlb_gather);
301
302 void (*flush_iotlb_all)(struct iommu_domain *domain);
303 void (*iotlb_sync_map)(struct iommu_domain *domain, unsigned long iova,
304 size_t size);
305 void (*iotlb_sync)(struct iommu_domain *domain,
306 struct iommu_iotlb_gather *iotlb_gather);
307
308 phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
309 dma_addr_t iova);
310
6043257b 311 bool (*enforce_cache_coherency)(struct iommu_domain *domain);
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312 int (*enable_nesting)(struct iommu_domain *domain);
313 int (*set_pgtable_quirks)(struct iommu_domain *domain,
314 unsigned long quirks);
315
316 void (*free)(struct iommu_domain *domain);
317};
318
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319/**
320 * struct iommu_device - IOMMU core representation of one IOMMU hardware
321 * instance
322 * @list: Used by the iommu-core to keep a list of registered iommus
323 * @ops: iommu-ops for talking to this iommu
39ab9555 324 * @dev: struct device for sysfs handling
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325 */
326struct iommu_device {
327 struct list_head list;
328 const struct iommu_ops *ops;
c73e1ac8 329 struct fwnode_handle *fwnode;
2926a2aa 330 struct device *dev;
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331};
332
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333/**
334 * struct iommu_fault_event - Generic fault event
335 *
336 * Can represent recoverable faults such as a page requests or
337 * unrecoverable faults such as DMA or IRQ remapping faults.
338 *
339 * @fault: fault descriptor
bf3255b3 340 * @list: pending fault event list, used for tracking responses
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341 */
342struct iommu_fault_event {
343 struct iommu_fault fault;
bf3255b3 344 struct list_head list;
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345};
346
347/**
348 * struct iommu_fault_param - per-device IOMMU fault data
349 * @handler: Callback function to handle IOMMU faults at device level
350 * @data: handler private data
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351 * @faults: holds the pending faults which needs response
352 * @lock: protect pending faults list
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353 */
354struct iommu_fault_param {
355 iommu_dev_fault_handler_t handler;
356 void *data;
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357 struct list_head faults;
358 struct mutex lock;
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359};
360
361/**
045a7042 362 * struct dev_iommu - Collection of per-device IOMMU data
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363 *
364 * @fault_param: IOMMU detected device fault reporting data
fc36479d 365 * @iopf_param: I/O Page Fault queue and data
72acd9df 366 * @fwspec: IOMMU fwspec data
a6a4c7e2 367 * @iommu_dev: IOMMU device this device is linked to
986d5ecc 368 * @priv: IOMMU Driver private data
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369 *
370 * TODO: migrate other per device data pointers under iommu_dev_data, e.g.
371 * struct iommu_group *iommu_group;
4e32348b 372 */
045a7042 373struct dev_iommu {
0c830e6b 374 struct mutex lock;
72acd9df 375 struct iommu_fault_param *fault_param;
fc36479d 376 struct iopf_device_param *iopf_param;
72acd9df 377 struct iommu_fwspec *fwspec;
a6a4c7e2 378 struct iommu_device *iommu_dev;
986d5ecc 379 void *priv;
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380};
381
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382int iommu_device_register(struct iommu_device *iommu,
383 const struct iommu_ops *ops,
384 struct device *hwdev);
b0119e87 385void iommu_device_unregister(struct iommu_device *iommu);
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386int iommu_device_sysfs_add(struct iommu_device *iommu,
387 struct device *parent,
388 const struct attribute_group **groups,
389 const char *fmt, ...) __printf(4, 5);
390void iommu_device_sysfs_remove(struct iommu_device *iommu);
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391int iommu_device_link(struct iommu_device *iommu, struct device *link);
392void iommu_device_unlink(struct iommu_device *iommu, struct device *link);
3ab65729 393int iommu_deferred_attach(struct device *dev, struct iommu_domain *domain);
b0119e87 394
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395static inline struct iommu_device *dev_to_iommu_device(struct device *dev)
396{
397 return (struct iommu_device *)dev_get_drvdata(dev);
398}
399
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400static inline void iommu_iotlb_gather_init(struct iommu_iotlb_gather *gather)
401{
402 *gather = (struct iommu_iotlb_gather) {
403 .start = ULONG_MAX,
87f60cc6 404 .freelist = LIST_HEAD_INIT(gather->freelist),
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405 };
406}
407
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408static inline const struct iommu_ops *dev_iommu_ops(struct device *dev)
409{
410 /*
411 * Assume that valid ops must be installed if iommu_probe_device()
412 * has succeeded. The device ops are essentially for internal use
413 * within the IOMMU subsystem itself, so we should be able to trust
414 * ourselves not to misuse the helper.
415 */
416 return dev->iommu->iommu_dev->ops;
417}
418
5012c396 419extern int bus_iommu_probe(struct bus_type *bus);
a1b60c1c 420extern bool iommu_present(struct bus_type *bus);
ed36d04e 421extern bool device_iommu_capable(struct device *dev, enum iommu_cap cap);
905d66c1 422extern struct iommu_domain *iommu_domain_alloc(struct bus_type *bus);
aa16bea9 423extern struct iommu_group *iommu_group_get_by_id(int id);
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424extern void iommu_domain_free(struct iommu_domain *domain);
425extern int iommu_attach_device(struct iommu_domain *domain,
426 struct device *dev);
427extern void iommu_detach_device(struct iommu_domain *domain,
428 struct device *dev);
808be0aa 429extern int iommu_sva_unbind_gpasid(struct iommu_domain *domain,
d9057381 430 struct device *dev, ioasid_t pasid);
2c1296d9 431extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev);
6af588fe 432extern struct iommu_domain *iommu_get_dma_domain(struct device *dev);
cefc53c7 433extern int iommu_map(struct iommu_domain *domain, unsigned long iova,
7d3002cc 434 phys_addr_t paddr, size_t size, int prot);
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435extern int iommu_map_atomic(struct iommu_domain *domain, unsigned long iova,
436 phys_addr_t paddr, size_t size, int prot);
7d3002cc 437extern size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
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438 size_t size);
439extern size_t iommu_unmap_fast(struct iommu_domain *domain,
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440 unsigned long iova, size_t size,
441 struct iommu_iotlb_gather *iotlb_gather);
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442extern ssize_t iommu_map_sg(struct iommu_domain *domain, unsigned long iova,
443 struct scatterlist *sg, unsigned int nents, int prot);
444extern ssize_t iommu_map_sg_atomic(struct iommu_domain *domain,
445 unsigned long iova, struct scatterlist *sg,
446 unsigned int nents, int prot);
bb5547ac 447extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova);
4f3f8d9d 448extern void iommu_set_fault_handler(struct iommu_domain *domain,
77ca2332 449 iommu_fault_handler_t handler, void *token);
d72e31c9 450
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451extern void iommu_get_resv_regions(struct device *dev, struct list_head *list);
452extern void iommu_put_resv_regions(struct device *dev, struct list_head *list);
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453extern void iommu_set_default_passthrough(bool cmd_line);
454extern void iommu_set_default_translated(bool cmd_line);
455extern bool iommu_default_passthrough(void);
2b20cbba 456extern struct iommu_resv_region *
9d3a4de4 457iommu_alloc_resv_region(phys_addr_t start, size_t length, int prot,
0251d010 458 enum iommu_resv_type type, gfp_t gfp);
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459extern int iommu_get_group_resv_regions(struct iommu_group *group,
460 struct list_head *head);
a1015c2b 461
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462extern int iommu_attach_group(struct iommu_domain *domain,
463 struct iommu_group *group);
464extern void iommu_detach_group(struct iommu_domain *domain,
465 struct iommu_group *group);
466extern struct iommu_group *iommu_group_alloc(void);
467extern void *iommu_group_get_iommudata(struct iommu_group *group);
468extern void iommu_group_set_iommudata(struct iommu_group *group,
469 void *iommu_data,
470 void (*release)(void *iommu_data));
471extern int iommu_group_set_name(struct iommu_group *group, const char *name);
472extern int iommu_group_add_device(struct iommu_group *group,
473 struct device *dev);
474extern void iommu_group_remove_device(struct device *dev);
475extern int iommu_group_for_each_dev(struct iommu_group *group, void *data,
476 int (*fn)(struct device *, void *));
477extern struct iommu_group *iommu_group_get(struct device *dev);
13f59a78 478extern struct iommu_group *iommu_group_ref_get(struct iommu_group *group);
d72e31c9 479extern void iommu_group_put(struct iommu_group *group);
0c830e6b
JP
480extern int iommu_register_device_fault_handler(struct device *dev,
481 iommu_dev_fault_handler_t handler,
482 void *data);
483
484extern int iommu_unregister_device_fault_handler(struct device *dev);
485
486extern int iommu_report_device_fault(struct device *dev,
487 struct iommu_fault_event *evt);
bf3255b3
JPB
488extern int iommu_page_response(struct device *dev,
489 struct iommu_page_response *msg);
0c830e6b 490
d72e31c9 491extern int iommu_group_id(struct iommu_group *group);
6827ca83 492extern struct iommu_domain *iommu_group_default_domain(struct iommu_group *);
4f3f8d9d 493
7e147547 494int iommu_enable_nesting(struct iommu_domain *domain);
4fc52b81
CH
495int iommu_set_pgtable_quirks(struct iommu_domain *domain,
496 unsigned long quirks);
4f3f8d9d 497
308723e3 498void iommu_set_dma_strict(void);
207c6e36
JR
499
500extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev,
501 unsigned long iova, int flags);
4a77a6cf 502
aae4c8e2 503static inline void iommu_flush_iotlb_all(struct iommu_domain *domain)
add02cfd
JR
504{
505 if (domain->ops->flush_iotlb_all)
506 domain->ops->flush_iotlb_all(domain);
507}
508
aae4c8e2 509static inline void iommu_iotlb_sync(struct iommu_domain *domain,
a7d20dc1 510 struct iommu_iotlb_gather *iotlb_gather)
add02cfd
JR
511{
512 if (domain->ops->iotlb_sync)
56f8af5e 513 domain->ops->iotlb_sync(domain, iotlb_gather);
a7d20dc1
WD
514
515 iommu_iotlb_gather_init(iotlb_gather);
add02cfd
JR
516}
517
febb82c2
NA
518/**
519 * iommu_iotlb_gather_is_disjoint - Checks whether a new range is disjoint
520 *
521 * @gather: TLB gather data
522 * @iova: start of page to invalidate
523 * @size: size of page to invalidate
524 *
525 * Helper for IOMMU drivers to check whether a new range and the gathered range
526 * are disjoint. For many IOMMUs, flushing the IOMMU in this case is better
527 * than merging the two, which might lead to unnecessary invalidations.
528 */
529static inline
530bool iommu_iotlb_gather_is_disjoint(struct iommu_iotlb_gather *gather,
531 unsigned long iova, size_t size)
532{
533 unsigned long start = iova, end = start + size - 1;
534
535 return gather->end != 0 &&
536 (end + 1 < gather->start || start > gather->end + 1);
537}
538
539
3136895c
RM
540/**
541 * iommu_iotlb_gather_add_range - Gather for address-based TLB invalidation
542 * @gather: TLB gather data
543 * @iova: start of page to invalidate
544 * @size: size of page to invalidate
545 *
546 * Helper for IOMMU drivers to build arbitrarily-sized invalidation commands
547 * where only the address range matters, and simply minimising intermediate
548 * syncs is preferred.
549 */
550static inline void iommu_iotlb_gather_add_range(struct iommu_iotlb_gather *gather,
551 unsigned long iova, size_t size)
552{
553 unsigned long end = iova + size - 1;
554
555 if (gather->start > iova)
556 gather->start = iova;
557 if (gather->end < end)
558 gather->end = end;
559}
560
561/**
562 * iommu_iotlb_gather_add_page - Gather for page-based TLB invalidation
563 * @domain: IOMMU domain to be invalidated
564 * @gather: TLB gather data
565 * @iova: start of page to invalidate
566 * @size: size of page to invalidate
567 *
568 * Helper for IOMMU drivers to build invalidation commands based on individual
569 * pages, or with page size/table level hints which cannot be gathered if they
570 * differ.
571 */
4fcf8544
WD
572static inline void iommu_iotlb_gather_add_page(struct iommu_domain *domain,
573 struct iommu_iotlb_gather *gather,
574 unsigned long iova, size_t size)
575{
4fcf8544
WD
576 /*
577 * If the new page is disjoint from the current range or is mapped at
578 * a different granularity, then sync the TLB so that the gather
579 * structure can be rewritten.
580 */
febb82c2
NA
581 if ((gather->pgsize && gather->pgsize != size) ||
582 iommu_iotlb_gather_is_disjoint(gather, iova, size))
583 iommu_iotlb_sync(domain, gather);
4fcf8544 584
febb82c2 585 gather->pgsize = size;
3136895c 586 iommu_iotlb_gather_add_range(gather, iova, size);
4fcf8544 587}
4fcf8544 588
f7403abf
RM
589static inline bool iommu_iotlb_gather_queued(struct iommu_iotlb_gather *gather)
590{
591 return gather && gather->queued;
4fcf8544
WD
592}
593
5e62292b
JR
594/* PCI device grouping function */
595extern struct iommu_group *pci_device_group(struct device *dev);
6eab556a
JR
596/* Generic device grouping function */
597extern struct iommu_group *generic_device_group(struct device *dev);
eab03e2a
NG
598/* FSL-MC device grouping function */
599struct iommu_group *fsl_mc_device_group(struct device *dev);
5e62292b 600
57f98d2f
RM
601/**
602 * struct iommu_fwspec - per-device IOMMU instance data
603 * @ops: ops for this device's IOMMU
604 * @iommu_fwnode: firmware handle for this device's IOMMU
0d35309a 605 * @flags: IOMMU_FWSPEC_* flags
57f98d2f
RM
606 * @num_ids: number of associated device IDs
607 * @ids: IDs which this device may present to the IOMMU
495b637f
TR
608 *
609 * Note that the IDs (and any other information, really) stored in this structure should be
610 * considered private to the IOMMU device driver and are not to be used directly by IOMMU
611 * consumers.
57f98d2f
RM
612 */
613struct iommu_fwspec {
614 const struct iommu_ops *ops;
615 struct fwnode_handle *iommu_fwnode;
5702ee24 616 u32 flags;
57f98d2f 617 unsigned int num_ids;
098accf2 618 u32 ids[];
57f98d2f
RM
619};
620
5702ee24
JPB
621/* ATS is supported */
622#define IOMMU_FWSPEC_PCI_RC_ATS (1 << 0)
623
26b25a2b
JPB
624/**
625 * struct iommu_sva - handle to a device-mm bond
626 */
627struct iommu_sva {
628 struct device *dev;
26b25a2b
JPB
629};
630
57f98d2f
RM
631int iommu_fwspec_init(struct device *dev, struct fwnode_handle *iommu_fwnode,
632 const struct iommu_ops *ops);
633void iommu_fwspec_free(struct device *dev);
634int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids);
534766df 635const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode);
57f98d2f 636
b4ef725e
JR
637static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev)
638{
72acd9df
JR
639 if (dev->iommu)
640 return dev->iommu->fwspec;
641 else
642 return NULL;
b4ef725e
JR
643}
644
645static inline void dev_iommu_fwspec_set(struct device *dev,
646 struct iommu_fwspec *fwspec)
647{
72acd9df 648 dev->iommu->fwspec = fwspec;
b4ef725e
JR
649}
650
f9867f41
JR
651static inline void *dev_iommu_priv_get(struct device *dev)
652{
4c9fb5d9
JR
653 if (dev->iommu)
654 return dev->iommu->priv;
655 else
656 return NULL;
f9867f41
JR
657}
658
659static inline void dev_iommu_priv_set(struct device *dev, void *priv)
660{
986d5ecc 661 dev->iommu->priv = priv;
f9867f41
JR
662}
663
cc5aed44
JR
664int iommu_probe_device(struct device *dev);
665void iommu_release_device(struct device *dev);
666
a3a19592
LB
667int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features f);
668int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features f);
a3a19592 669
26b25a2b
JPB
670struct iommu_sva *iommu_sva_bind_device(struct device *dev,
671 struct mm_struct *mm,
672 void *drvdata);
673void iommu_sva_unbind_device(struct iommu_sva *handle);
c7b6bac9 674u32 iommu_sva_get_pasid(struct iommu_sva *handle);
26b25a2b 675
1ea2a07a
LB
676int iommu_device_use_default_domain(struct device *dev);
677void iommu_device_unuse_default_domain(struct device *dev);
678
679int iommu_group_claim_dma_owner(struct iommu_group *group, void *owner);
680void iommu_group_release_dma_owner(struct iommu_group *group);
681bool iommu_group_dma_owner_claimed(struct iommu_group *group);
682
4a77a6cf
JR
683#else /* CONFIG_IOMMU_API */
684
39d4ebb9 685struct iommu_ops {};
d72e31c9 686struct iommu_group {};
57f98d2f 687struct iommu_fwspec {};
b0119e87 688struct iommu_device {};
4e32348b 689struct iommu_fault_param {};
a7d20dc1 690struct iommu_iotlb_gather {};
4a77a6cf 691
a1b60c1c 692static inline bool iommu_present(struct bus_type *bus)
4a77a6cf
JR
693{
694 return false;
695}
696
ed36d04e
RM
697static inline bool device_iommu_capable(struct device *dev, enum iommu_cap cap)
698{
699 return false;
700}
701
905d66c1 702static inline struct iommu_domain *iommu_domain_alloc(struct bus_type *bus)
4a77a6cf
JR
703{
704 return NULL;
705}
706
b62dfd29
AK
707static inline struct iommu_group *iommu_group_get_by_id(int id)
708{
709 return NULL;
710}
711
4a77a6cf
JR
712static inline void iommu_domain_free(struct iommu_domain *domain)
713{
714}
715
716static inline int iommu_attach_device(struct iommu_domain *domain,
717 struct device *dev)
718{
719 return -ENODEV;
720}
721
722static inline void iommu_detach_device(struct iommu_domain *domain,
723 struct device *dev)
724{
725}
726
2c1296d9
JR
727static inline struct iommu_domain *iommu_get_domain_for_dev(struct device *dev)
728{
729 return NULL;
730}
731
cefc53c7 732static inline int iommu_map(struct iommu_domain *domain, unsigned long iova,
ebae3e83 733 phys_addr_t paddr, size_t size, int prot)
cefc53c7
JR
734{
735 return -ENODEV;
736}
737
781ca2de
TM
738static inline int iommu_map_atomic(struct iommu_domain *domain,
739 unsigned long iova, phys_addr_t paddr,
740 size_t size, int prot)
741{
742 return -ENODEV;
743}
744
c5611a87
SS
745static inline size_t iommu_unmap(struct iommu_domain *domain,
746 unsigned long iova, size_t size)
cefc53c7 747{
c5611a87 748 return 0;
cefc53c7
JR
749}
750
c5611a87 751static inline size_t iommu_unmap_fast(struct iommu_domain *domain,
a7d20dc1
WD
752 unsigned long iova, int gfp_order,
753 struct iommu_iotlb_gather *iotlb_gather)
cefc53c7 754{
c5611a87 755 return 0;
cefc53c7
JR
756}
757
ad8f36e4
LG
758static inline ssize_t iommu_map_sg(struct iommu_domain *domain,
759 unsigned long iova, struct scatterlist *sg,
760 unsigned int nents, int prot)
315786eb 761{
ad8f36e4 762 return -ENODEV;
315786eb
OH
763}
764
ad8f36e4 765static inline ssize_t iommu_map_sg_atomic(struct iommu_domain *domain,
781ca2de
TM
766 unsigned long iova, struct scatterlist *sg,
767 unsigned int nents, int prot)
768{
ad8f36e4 769 return -ENODEV;
781ca2de
TM
770}
771
aae4c8e2 772static inline void iommu_flush_iotlb_all(struct iommu_domain *domain)
add02cfd
JR
773{
774}
775
aae4c8e2 776static inline void iommu_iotlb_sync(struct iommu_domain *domain,
a7d20dc1 777 struct iommu_iotlb_gather *iotlb_gather)
add02cfd
JR
778{
779}
780
bb5547ac 781static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
4a77a6cf
JR
782{
783 return 0;
784}
785
4f3f8d9d 786static inline void iommu_set_fault_handler(struct iommu_domain *domain,
77ca2332 787 iommu_fault_handler_t handler, void *token)
4f3f8d9d
OBC
788{
789}
790
e5b5234a 791static inline void iommu_get_resv_regions(struct device *dev,
a1015c2b
JR
792 struct list_head *list)
793{
794}
795
e5b5234a 796static inline void iommu_put_resv_regions(struct device *dev,
a1015c2b
JR
797 struct list_head *list)
798{
799}
800
6c65fb31
EA
801static inline int iommu_get_group_resv_regions(struct iommu_group *group,
802 struct list_head *head)
803{
804 return -ENODEV;
805}
806
8a69961c
JR
807static inline void iommu_set_default_passthrough(bool cmd_line)
808{
809}
810
811static inline void iommu_set_default_translated(bool cmd_line)
812{
813}
814
815static inline bool iommu_default_passthrough(void)
816{
817 return true;
818}
819
bef83de5
AW
820static inline int iommu_attach_group(struct iommu_domain *domain,
821 struct iommu_group *group)
d72e31c9
AW
822{
823 return -ENODEV;
824}
825
bef83de5
AW
826static inline void iommu_detach_group(struct iommu_domain *domain,
827 struct iommu_group *group)
d72e31c9
AW
828{
829}
830
bef83de5 831static inline struct iommu_group *iommu_group_alloc(void)
d72e31c9
AW
832{
833 return ERR_PTR(-ENODEV);
834}
835
bef83de5 836static inline void *iommu_group_get_iommudata(struct iommu_group *group)
d72e31c9
AW
837{
838 return NULL;
839}
840
bef83de5
AW
841static inline void iommu_group_set_iommudata(struct iommu_group *group,
842 void *iommu_data,
843 void (*release)(void *iommu_data))
d72e31c9
AW
844{
845}
846
bef83de5
AW
847static inline int iommu_group_set_name(struct iommu_group *group,
848 const char *name)
d72e31c9
AW
849{
850 return -ENODEV;
851}
852
bef83de5
AW
853static inline int iommu_group_add_device(struct iommu_group *group,
854 struct device *dev)
d72e31c9
AW
855{
856 return -ENODEV;
857}
858
bef83de5 859static inline void iommu_group_remove_device(struct device *dev)
d72e31c9
AW
860{
861}
862
bef83de5
AW
863static inline int iommu_group_for_each_dev(struct iommu_group *group,
864 void *data,
865 int (*fn)(struct device *, void *))
d72e31c9
AW
866{
867 return -ENODEV;
868}
869
bef83de5 870static inline struct iommu_group *iommu_group_get(struct device *dev)
d72e31c9
AW
871{
872 return NULL;
873}
874
bef83de5 875static inline void iommu_group_put(struct iommu_group *group)
d72e31c9
AW
876{
877}
878
0c830e6b
JP
879static inline
880int iommu_register_device_fault_handler(struct device *dev,
881 iommu_dev_fault_handler_t handler,
882 void *data)
883{
884 return -ENODEV;
885}
886
887static inline int iommu_unregister_device_fault_handler(struct device *dev)
888{
889 return 0;
890}
891
892static inline
893int iommu_report_device_fault(struct device *dev, struct iommu_fault_event *evt)
894{
895 return -ENODEV;
896}
897
bf3255b3
JPB
898static inline int iommu_page_response(struct device *dev,
899 struct iommu_page_response *msg)
900{
901 return -ENODEV;
902}
903
bef83de5 904static inline int iommu_group_id(struct iommu_group *group)
d72e31c9
AW
905{
906 return -ENODEV;
907}
1460432c 908
4fc52b81
CH
909static inline int iommu_set_pgtable_quirks(struct iommu_domain *domain,
910 unsigned long quirks)
0cd76dd1 911{
4fc52b81 912 return 0;
0cd76dd1
JR
913}
914
2d471b20
RM
915static inline int iommu_device_register(struct iommu_device *iommu,
916 const struct iommu_ops *ops,
917 struct device *hwdev)
c61959ec 918{
39ab9555 919 return -ENODEV;
c61959ec
AW
920}
921
2926a2aa
JR
922static inline struct iommu_device *dev_to_iommu_device(struct device *dev)
923{
924 return NULL;
925}
926
a7d20dc1
WD
927static inline void iommu_iotlb_gather_init(struct iommu_iotlb_gather *gather)
928{
929}
930
4fcf8544
WD
931static inline void iommu_iotlb_gather_add_page(struct iommu_domain *domain,
932 struct iommu_iotlb_gather *gather,
933 unsigned long iova, size_t size)
934{
935}
936
f7403abf
RM
937static inline bool iommu_iotlb_gather_queued(struct iommu_iotlb_gather *gather)
938{
939 return false;
940}
941
39ab9555 942static inline void iommu_device_unregister(struct iommu_device *iommu)
c61959ec 943{
c61959ec
AW
944}
945
39ab9555
JR
946static inline int iommu_device_sysfs_add(struct iommu_device *iommu,
947 struct device *parent,
948 const struct attribute_group **groups,
949 const char *fmt, ...)
b0119e87 950{
39ab9555 951 return -ENODEV;
b0119e87
JR
952}
953
39ab9555 954static inline void iommu_device_sysfs_remove(struct iommu_device *iommu)
c61959ec
AW
955{
956}
957
e09f8ea5 958static inline int iommu_device_link(struct device *dev, struct device *link)
c61959ec
AW
959{
960 return -EINVAL;
961}
962
e09f8ea5 963static inline void iommu_device_unlink(struct device *dev, struct device *link)
c61959ec
AW
964{
965}
966
57f98d2f
RM
967static inline int iommu_fwspec_init(struct device *dev,
968 struct fwnode_handle *iommu_fwnode,
969 const struct iommu_ops *ops)
970{
971 return -ENODEV;
972}
973
974static inline void iommu_fwspec_free(struct device *dev)
975{
976}
977
978static inline int iommu_fwspec_add_ids(struct device *dev, u32 *ids,
979 int num_ids)
980{
981 return -ENODEV;
982}
983
e4f10ffe 984static inline
534766df 985const struct iommu_ops *iommu_ops_from_fwnode(struct fwnode_handle *fwnode)
e4f10ffe
LP
986{
987 return NULL;
988}
989
a3a19592
LB
990static inline int
991iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features feat)
992{
993 return -ENODEV;
994}
995
996static inline int
997iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat)
998{
999 return -ENODEV;
1000}
1001
26b25a2b
JPB
1002static inline struct iommu_sva *
1003iommu_sva_bind_device(struct device *dev, struct mm_struct *mm, void *drvdata)
1004{
1005 return NULL;
1006}
1007
1008static inline void iommu_sva_unbind_device(struct iommu_sva *handle)
1009{
1010}
1011
c7b6bac9 1012static inline u32 iommu_sva_get_pasid(struct iommu_sva *handle)
26b25a2b
JPB
1013{
1014 return IOMMU_PASID_INVALID;
1015}
1016
0008d0c3
JR
1017static inline struct iommu_fwspec *dev_iommu_fwspec_get(struct device *dev)
1018{
1019 return NULL;
1020}
1ea2a07a
LB
1021
1022static inline int iommu_device_use_default_domain(struct device *dev)
1023{
1024 return 0;
1025}
1026
1027static inline void iommu_device_unuse_default_domain(struct device *dev)
1028{
1029}
1030
1031static inline int
1032iommu_group_claim_dma_owner(struct iommu_group *group, void *owner)
1033{
1034 return -ENODEV;
1035}
1036
1037static inline void iommu_group_release_dma_owner(struct iommu_group *group)
1038{
1039}
1040
1041static inline bool iommu_group_dma_owner_claimed(struct iommu_group *group)
1042{
1043 return false;
1044}
4a77a6cf
JR
1045#endif /* CONFIG_IOMMU_API */
1046
ca37faf3
MS
1047/**
1048 * iommu_map_sgtable - Map the given buffer to the IOMMU domain
1049 * @domain: The IOMMU domain to perform the mapping
1050 * @iova: The start address to map the buffer
1051 * @sgt: The sg_table object describing the buffer
1052 * @prot: IOMMU protection bits
1053 *
1054 * Creates a mapping at @iova for the buffer described by a scatterlist
1055 * stored in the given sg_table object in the provided IOMMU domain.
1056 */
1057static inline size_t iommu_map_sgtable(struct iommu_domain *domain,
1058 unsigned long iova, struct sg_table *sgt, int prot)
1059{
1060 return iommu_map_sg(domain, iova, sgt->sgl, sgt->orig_nents, prot);
1061}
1062
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1063#ifdef CONFIG_IOMMU_DEBUGFS
1064extern struct dentry *iommu_debugfs_dir;
1065void iommu_debugfs_setup(void);
1066#else
1067static inline void iommu_debugfs_setup(void) {}
1068#endif
1069
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1070#ifdef CONFIG_IOMMU_DMA
1071#include <linux/msi.h>
1072
1073/* Setup call for arch DMA mapping code */
1074void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit);
1075
1076int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base);
1077
1078int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr);
1079void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg);
1080
1081#else /* CONFIG_IOMMU_DMA */
1082
1083struct msi_desc;
1084struct msi_msg;
1085
1086static inline void iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 dma_limit)
1087{
1088}
1089
1090static inline int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
1091{
1092 return -ENODEV;
1093}
1094
1095static inline int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr)
1096{
1097 return 0;
1098}
1099
1100static inline void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
1101{
1102}
1103
1104#endif /* CONFIG_IOMMU_DMA */
1105
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1106/*
1107 * Newer generations of Tegra SoCs require devices' stream IDs to be directly programmed into
1108 * some registers. These are always paired with a Tegra SMMU or ARM SMMU, for which the contents
1109 * of the struct iommu_fwspec are known. Use this helper to formalize access to these internals.
1110 */
1111#define TEGRA_STREAM_ID_BYPASS 0x7f
1112
1113static inline bool tegra_dev_iommu_get_stream_id(struct device *dev, u32 *stream_id)
1114{
1115#ifdef CONFIG_IOMMU_API
1116 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
1117
1118 if (fwspec && fwspec->num_ids == 1) {
1119 *stream_id = fwspec->ids[0] & 0xffff;
1120 return true;
1121 }
1122#endif
1123
1124 return false;
1125}
1126
4a77a6cf 1127#endif /* __LINUX_IOMMU_H */