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775c8a3d | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
c27a0d75 BS |
2 | /* |
3 | * Copyright 2006 PathScale, Inc. All Rights Reserved. | |
c27a0d75 BS |
4 | */ |
5 | ||
6 | #ifndef _LINUX_IO_H | |
7 | #define _LINUX_IO_H | |
8 | ||
cb1055fb | 9 | #include <linux/types.h> |
d6472302 | 10 | #include <linux/init.h> |
41e94a85 CH |
11 | #include <linux/bug.h> |
12 | #include <linux/err.h> | |
c27a0d75 | 13 | #include <asm/io.h> |
74588d8b | 14 | #include <asm/page.h> |
c27a0d75 | 15 | |
7f253770 | 16 | struct device; |
41e94a85 | 17 | struct resource; |
7f253770 | 18 | |
d47d5c81 | 19 | __visible void __iowrite32_copy(void __iomem *to, const void *from, size_t count); |
a9aec588 | 20 | void __ioread32_copy(void *to, const void __iomem *from, size_t count); |
22ae813b | 21 | void __iowrite64_copy(void __iomem *to, const void *from, size_t count); |
c27a0d75 | 22 | |
218f0aae | 23 | #ifdef CONFIG_MMU |
74588d8b | 24 | int ioremap_page_range(unsigned long addr, unsigned long end, |
ffa71f33 | 25 | phys_addr_t phys_addr, pgprot_t prot); |
218f0aae PM |
26 | #else |
27 | static inline int ioremap_page_range(unsigned long addr, unsigned long end, | |
ffa71f33 | 28 | phys_addr_t phys_addr, pgprot_t prot) |
218f0aae PM |
29 | { |
30 | return 0; | |
31 | } | |
32 | #endif | |
74588d8b | 33 | |
0ddab1d2 TK |
34 | #ifdef CONFIG_HAVE_ARCH_HUGE_VMAP |
35 | void __init ioremap_huge_init(void); | |
0f472d04 | 36 | int arch_ioremap_p4d_supported(void); |
0ddab1d2 TK |
37 | int arch_ioremap_pud_supported(void); |
38 | int arch_ioremap_pmd_supported(void); | |
39 | #else | |
40 | static inline void ioremap_huge_init(void) { } | |
41 | #endif | |
42 | ||
9ac7849e TH |
43 | /* |
44 | * Managed iomap interface | |
45 | */ | |
ce816fa8 | 46 | #ifdef CONFIG_HAS_IOPORT_MAP |
9ac7849e TH |
47 | void __iomem * devm_ioport_map(struct device *dev, unsigned long port, |
48 | unsigned int nr); | |
49 | void devm_ioport_unmap(struct device *dev, void __iomem *addr); | |
93da2879 RK |
50 | #else |
51 | static inline void __iomem *devm_ioport_map(struct device *dev, | |
52 | unsigned long port, | |
53 | unsigned int nr) | |
54 | { | |
55 | return NULL; | |
56 | } | |
57 | ||
58 | static inline void devm_ioport_unmap(struct device *dev, void __iomem *addr) | |
59 | { | |
60 | } | |
61 | #endif | |
9ac7849e | 62 | |
efd342fb MB |
63 | #define IOMEM_ERR_PTR(err) (__force void __iomem *)ERR_PTR(err) |
64 | ||
4f452e8a | 65 | void __iomem *devm_ioremap(struct device *dev, resource_size_t offset, |
5559b7bc | 66 | resource_size_t size); |
e537654b TZ |
67 | void __iomem *devm_ioremap_uc(struct device *dev, resource_size_t offset, |
68 | resource_size_t size); | |
4f452e8a | 69 | void __iomem *devm_ioremap_nocache(struct device *dev, resource_size_t offset, |
5559b7bc | 70 | resource_size_t size); |
34644524 AK |
71 | void __iomem *devm_ioremap_wc(struct device *dev, resource_size_t offset, |
72 | resource_size_t size); | |
9ac7849e | 73 | void devm_iounmap(struct device *dev, void __iomem *addr); |
cc2ea416 AM |
74 | int check_signature(const volatile void __iomem *io_addr, |
75 | const unsigned char *signature, int length); | |
b41e5fff | 76 | void devm_ioremap_release(struct device *dev, void *res); |
e50190a8 | 77 | |
7d3dcf26 CH |
78 | void *devm_memremap(struct device *dev, resource_size_t offset, |
79 | size_t size, unsigned long flags); | |
80 | void devm_memunmap(struct device *dev, void *addr); | |
81 | ||
41e94a85 CH |
82 | void *__devm_memremap_pages(struct device *dev, struct resource *res); |
83 | ||
cf9ea8ca LP |
84 | #ifdef CONFIG_PCI |
85 | /* | |
86 | * The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and | |
87 | * Posting") mandate non-posted configuration transactions. There is | |
88 | * no ioremap API in the kernel that can guarantee non-posted write | |
89 | * semantics across arches so provide a default implementation for | |
90 | * mapping PCI config space that defaults to ioremap_nocache(); arches | |
91 | * should override it if they have memory mapping implementations that | |
92 | * guarantee non-posted writes semantics to make the memory mapping | |
93 | * compliant with the PCI specification. | |
94 | */ | |
95 | #ifndef pci_remap_cfgspace | |
96 | #define pci_remap_cfgspace pci_remap_cfgspace | |
97 | static inline void __iomem *pci_remap_cfgspace(phys_addr_t offset, | |
98 | size_t size) | |
99 | { | |
100 | return ioremap_nocache(offset, size); | |
101 | } | |
102 | #endif | |
103 | #endif | |
104 | ||
e1612de9 HM |
105 | /* |
106 | * Some systems do not have legacy ISA devices. | |
107 | * /dev/port is not a valid interface on these systems. | |
108 | * So for those archs, <asm/io.h> should define the following symbol. | |
109 | */ | |
110 | #ifndef arch_has_dev_port | |
111 | #define arch_has_dev_port() (1) | |
112 | #endif | |
113 | ||
d0d98eed AL |
114 | /* |
115 | * Some systems (x86 without PAT) have a somewhat reliable way to mark a | |
116 | * physical address range such that uncached mappings will actually | |
117 | * end up write-combining. This facility should be used in conjunction | |
118 | * with pgprot_writecombine, ioremap-wc, or set_memory_wc, since it has | |
119 | * no effect if the per-page mechanisms are functional. | |
120 | * (On x86 without PAT, these functions manipulate MTRRs.) | |
121 | * | |
122 | * arch_phys_del_wc(0) or arch_phys_del_wc(any error code) is guaranteed | |
123 | * to have no effect. | |
124 | */ | |
125 | #ifndef arch_phys_wc_add | |
126 | static inline int __must_check arch_phys_wc_add(unsigned long base, | |
127 | unsigned long size) | |
128 | { | |
129 | return 0; /* It worked (i.e. did nothing). */ | |
130 | } | |
131 | ||
132 | static inline void arch_phys_wc_del(int handle) | |
133 | { | |
134 | } | |
135 | ||
136 | #define arch_phys_wc_add arch_phys_wc_add | |
7d010fdf LR |
137 | #ifndef arch_phys_wc_index |
138 | static inline int arch_phys_wc_index(int handle) | |
139 | { | |
140 | return -1; | |
141 | } | |
142 | #define arch_phys_wc_index arch_phys_wc_index | |
143 | #endif | |
d0d98eed AL |
144 | #endif |
145 | ||
92281dee DW |
146 | enum { |
147 | /* See memremap() kernel-doc for usage description... */ | |
148 | MEMREMAP_WB = 1 << 0, | |
149 | MEMREMAP_WT = 1 << 1, | |
c907e0eb | 150 | MEMREMAP_WC = 1 << 2, |
8f716c9b TL |
151 | MEMREMAP_ENC = 1 << 3, |
152 | MEMREMAP_DEC = 1 << 4, | |
92281dee DW |
153 | }; |
154 | ||
155 | void *memremap(resource_size_t offset, size_t size, unsigned long flags); | |
156 | void memunmap(void *addr); | |
157 | ||
8ef42276 DA |
158 | /* |
159 | * On x86 PAT systems we have memory tracking that keeps track of | |
160 | * the allowed mappings on memory ranges. This tracking works for | |
161 | * all the in-kernel mapping APIs (ioremap*), but where the user | |
162 | * wishes to map a range from a physical device into user memory | |
163 | * the tracking won't be updated. This API is to be used by | |
164 | * drivers which remap physical device pages into userspace, | |
165 | * and wants to make sure they are mapped WC and not UC. | |
166 | */ | |
167 | #ifndef arch_io_reserve_memtype_wc | |
168 | static inline int arch_io_reserve_memtype_wc(resource_size_t base, | |
169 | resource_size_t size) | |
170 | { | |
171 | return 0; | |
172 | } | |
173 | ||
174 | static inline void arch_io_free_memtype_wc(resource_size_t base, | |
175 | resource_size_t size) | |
176 | { | |
177 | } | |
178 | #endif | |
179 | ||
c27a0d75 | 180 | #endif /* _LINUX_IO_H */ |