[linux-block.git] / include / linux / io-pgtable.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __IO_PGTABLE_H
#define __IO_PGTABLE_H

#include <linux/bitops.h>
#include <linux/iommu.h>

/*
 * Public API for use by IOMMU drivers
 */
enum io_pgtable_fmt {
	ARM_32_LPAE_S1,
	ARM_32_LPAE_S2,
	ARM_64_LPAE_S1,
	ARM_64_LPAE_S2,
	ARM_V7S,
	ARM_MALI_LPAE,
	AMD_IOMMU_V1,
	APPLE_DART,
	IO_PGTABLE_NUM_FMTS,
};

/**
 * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
 *
 * @tlb_flush_all:  Synchronously invalidate the entire TLB context.
 * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
 *                  (sometimes referred to as the "walk cache") for a virtual
 *                  address range.
 * @tlb_add_page:   Optional callback to queue up leaf TLB invalidation for a
 *                  single page.  IOMMUs that cannot batch TLB invalidation
 *                  operations efficiently will typically issue them here, but
 *                  others may decide to update the iommu_iotlb_gather structure
 *                  and defer the invalidation until iommu_iotlb_sync() instead.
 *
 * Note that these can all be called in atomic context and must therefore
 * not block.
 */
struct iommu_flush_ops {
	void (*tlb_flush_all)(void *cookie);
	void (*tlb_flush_walk)(unsigned long iova, size_t size, size_t granule,
			       void *cookie);
	void (*tlb_add_page)(struct iommu_iotlb_gather *gather,
			     unsigned long iova, size_t granule, void *cookie);
};

/**
 * struct io_pgtable_cfg - Configuration data for a set of page tables.
 *
 * @quirks:        A bitmap of hardware quirks that require some special
 *                 action by the low-level page table allocator.
 * @pgsize_bitmap: A bitmap of page sizes supported by this set of page
 *                 tables.
 * @ias:           Input address (iova) size, in bits.
 * @oas:           Output address (paddr) size, in bits.
 * @coherent_walk  A flag to indicate whether or not page table walks made
 *                 by the IOMMU are coherent with the CPU caches.
 * @tlb:           TLB management callbacks for this set of tables.
 * @iommu_dev:     The device representing the DMA configuration for the
 *                 page table walker.
 */
struct io_pgtable_cfg {
	/*
	 * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
	 *	stage 1 PTEs, for hardware which insists on validating them
	 *	even in	non-secure state where they should normally be ignored.
	 *
	 * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
	 *	IOMMU_NOEXEC flags and map everything with full access, for
	 *	hardware which does not implement the permissions of a given
	 *	format, and/or requires some format-specific default value.
	 *
	 * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend
	 *	to support up to 35 bits PA where the bit32, bit33 and bit34 are
	 *	encoded in the bit9, bit4 and bit5 of the PTE respectively.
	 *
	 * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
	 *	extend the translation table base support up to 35 bits PA, the
	 *	encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
	 *
	 * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
	 *	for use in the upper half of a split address space.
	 *
	 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
	 *	attributes set in the TCR for a non-coherent page-table walker.
	 */
	#define IO_PGTABLE_QUIRK_ARM_NS			BIT(0)
	#define IO_PGTABLE_QUIRK_NO_PERMS		BIT(1)
	#define IO_PGTABLE_QUIRK_ARM_MTK_EXT		BIT(3)
	#define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT	BIT(4)
	#define IO_PGTABLE_QUIRK_ARM_TTBR1		BIT(5)
	#define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA		BIT(6)
	unsigned long			quirks;
	unsigned long			pgsize_bitmap;
	unsigned int			ias;
	unsigned int			oas;
	bool				coherent_walk;
	const struct iommu_flush_ops	*tlb;
	struct device			*iommu_dev;

	/* Low-level data specific to the table format */
	union {
		struct {
			u64	ttbr;
			struct {
				u32	ips:3;
				u32	tg:2;
				u32	sh:2;
				u32	orgn:2;
				u32	irgn:2;
				u32	tsz:6;
			}	tcr;
			u64	mair;
		} arm_lpae_s1_cfg;

		struct {
			u64	vttbr;
			struct {
				u32	ps:3;
				u32	tg:2;
				u32	sh:2;
				u32	orgn:2;
				u32	irgn:2;
				u32	sl:2;
				u32	tsz:6;
			}	vtcr;
		} arm_lpae_s2_cfg;

		struct {
			u32	ttbr;
			u32	tcr;
			u32	nmrr;
			u32	prrr;
		} arm_v7s_cfg;

		struct {
			u64	transtab;
			u64	memattr;
		} arm_mali_lpae_cfg;

		struct {
			u64 ttbr[4];
			u32 n_ttbrs;
		} apple_dart_cfg;
	};
};

/**
 * struct io_pgtable_ops - Page table manipulation API for IOMMU drivers.
 *
 * @map:          Map a physically contiguous memory region.
 * @map_pages:    Map a physically contiguous range of pages of the same size.
 * @unmap:        Unmap a physically contiguous memory region.
 * @unmap_pages:  Unmap a range of virtually contiguous pages of the same size.
 * @iova_to_phys: Translate iova to physical address.
 *
 * These functions map directly onto the iommu_ops member functions with
 * the same names.
 */
struct io_pgtable_ops {
	int (*map)(struct io_pgtable_ops *ops, unsigned long iova,
		   phys_addr_t paddr, size_t size, int prot, gfp_t gfp);
	int (*map_pages)(struct io_pgtable_ops *ops, unsigned long iova,
			 phys_addr_t paddr, size_t pgsize, size_t pgcount,
			 int prot, gfp_t gfp, size_t *mapped);
	size_t (*unmap)(struct io_pgtable_ops *ops, unsigned long iova,
			size_t size, struct iommu_iotlb_gather *gather);
	size_t (*unmap_pages)(struct io_pgtable_ops *ops, unsigned long iova,
			      size_t pgsize, size_t pgcount,
			      struct iommu_iotlb_gather *gather);
	phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops,
				    unsigned long iova);
};

/**
 * alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU.
 *
 * @fmt:    The page table format.
 * @cfg:    The page table configuration. This will be modified to represent
 *          the configuration actually provided by the allocator (e.g. the
 *          pgsize_bitmap may be restricted).
 * @cookie: An opaque token provided by the IOMMU driver and passed back to
 *          the callback routines in cfg->tlb.
 */
struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
					    struct io_pgtable_cfg *cfg,
					    void *cookie);

/**
 * free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller
 *                         *must* ensure that the page table is no longer
 *                         live, but the TLB can be dirty.
 *
 * @ops: The ops returned from alloc_io_pgtable_ops.
 */
void free_io_pgtable_ops(struct io_pgtable_ops *ops);


/*
 * Internal structures for page table allocator implementations.
 */

/**
 * struct io_pgtable - Internal structure describing a set of page tables.
 *
 * @fmt:    The page table format.
 * @cookie: An opaque token provided by the IOMMU driver and passed back to
 *          any callback routines.
 * @cfg:    A copy of the page table configuration.
 * @ops:    The page table operations in use for this set of page tables.
 */
struct io_pgtable {
	enum io_pgtable_fmt	fmt;
	void			*cookie;
	struct io_pgtable_cfg	cfg;
	struct io_pgtable_ops	ops;
};

#define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops)

static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
{
	if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_all)
		iop->cfg.tlb->tlb_flush_all(iop->cookie);
}

static inline void
io_pgtable_tlb_flush_walk(struct io_pgtable *iop, unsigned long iova,
			  size_t size, size_t granule)
{
	if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_walk)
		iop->cfg.tlb->tlb_flush_walk(iova, size, granule, iop->cookie);
}

static inline void
io_pgtable_tlb_add_page(struct io_pgtable *iop,
			struct iommu_iotlb_gather * gather, unsigned long iova,
			size_t granule)
{
	if (iop->cfg.tlb && iop->cfg.tlb->tlb_add_page)
		iop->cfg.tlb->tlb_add_page(gather, iova, granule, iop->cookie);
}

/**
 * struct io_pgtable_init_fns - Alloc/free a set of page tables for a
 *                              particular format.
 *
 * @alloc: Allocate a set of page tables described by cfg.
 * @free:  Free the page tables associated with iop.
 */
struct io_pgtable_init_fns {
	struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie);
	void (*free)(struct io_pgtable *iop);
};

extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns;
extern struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns;

#endif /* __IO_PGTABLE_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
fdb1d7be WD	2	#ifndef __IO_PGTABLE_H
fdb1d7be WD	3	#define __IO_PGTABLE_H
a2d3a382	4
e5fc9753	5	#include <linux/bitops.h>
a2d3a382	6	#include <linux/iommu.h>
fdb1d7be WD	7
	8	/*
	9	* Public API for use by IOMMU drivers
	10	*/
	11	enum io_pgtable_fmt {
e1d3c0fd WD	12	ARM_32_LPAE_S1,
	13	ARM_32_LPAE_S2,
	14	ARM_64_LPAE_S1,
	15	ARM_64_LPAE_S2,
e5fc9753	16	ARM_V7S,
d08d42de	17	ARM_MALI_LPAE,
c9b258c6	18	AMD_IOMMU_V1,
892384cd	19	APPLE_DART,
fdb1d7be WD	20	IO_PGTABLE_NUM_FMTS,
	21	};
	22
	23	/**
298f7889	24	* struct iommu_flush_ops - IOMMU callbacks for TLB and page table management.
fdb1d7be	25	*
3445545b WD	26	* @tlb_flush_all: Synchronously invalidate the entire TLB context.
	27	* @tlb_flush_walk: Synchronously invalidate all intermediate TLB state
	28	* (sometimes referred to as the "walk cache") for a virtual
	29	* address range.
abfd6fe0	30	* @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
3951c41a WD	31	* single page. IOMMUs that cannot batch TLB invalidation
	32	* operations efficiently will typically issue them here, but
	33	* others may decide to update the iommu_iotlb_gather structure
aae4c8e2	34	* and defer the invalidation until iommu_iotlb_sync() instead.
fdb1d7be WD	35	*
	36	* Note that these can all be called in atomic context and must therefore
	37	* not block.
	38	*/
298f7889	39	struct iommu_flush_ops {
fdb1d7be	40	void (tlb_flush_all)(void cookie);
3445545b WD	41	void (*tlb_flush_walk)(unsigned long iova, size_t size, size_t granule,
3445545b WD	42	void *cookie);
3951c41a WD	43	void (tlb_add_page)(struct iommu_iotlb_gather gather,
3951c41a WD	44	unsigned long iova, size_t granule, void *cookie);
fdb1d7be WD	45	};
	46
	47	/**
	48	* struct io_pgtable_cfg - Configuration data for a set of page tables.
	49	*
	50	* @quirks: A bitmap of hardware quirks that require some special
	51	* action by the low-level page table allocator.
	52	* @pgsize_bitmap: A bitmap of page sizes supported by this set of page
	53	* tables.
	54	* @ias: Input address (iova) size, in bits.
	55	* @oas: Output address (paddr) size, in bits.
4f41845b WD	56	* @coherent_walk A flag to indicate whether or not page table walks made
4f41845b WD	57	* by the IOMMU are coherent with the CPU caches.
fdb1d7be	58	* @tlb: TLB management callbacks for this set of tables.
f8d54961 RM	59	* @iommu_dev: The device representing the DMA configuration for the
f8d54961 RM	60	* page table walker.
fdb1d7be WD	61	*/
fdb1d7be WD	62	struct io_pgtable_cfg {
3850db49 RM	63	/*
	64	* IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in
	65	* stage 1 PTEs, for hardware which insists on validating them
	66	* even in non-secure state where they should normally be ignored.
	67	*
	68	* IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and
	69	* IOMMU_NOEXEC flags and map everything with full access, for
	70	* hardware which does not implement the permissions of a given
	71	* format, and/or requires some format-specific default value.
	72	*
4c019de6	73	* IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend
40596d2f YW	74	* to support up to 35 bits PA where the bit32, bit33 and bit34 are
40596d2f YW	75	* encoded in the bit9, bit4 and bit5 of the PTE respectively.
81b3c252	76	*
bfdd2313 YW	77	* IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
	78	* extend the translation table base support up to 35 bits PA, the
	79	* encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
	80	*
db690301 RM	81	* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
db690301 RM	82	* for use in the upper half of a split address space.
e67890c9 SPR	83	*
	84	* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
	85	* attributes set in the TCR for a non-coherent page-table walker.
3850db49	86	*/
bfdd2313 YW	87	#define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
	88	#define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
	89	#define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
	90	#define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
	91	#define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
	92	#define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
3850db49	93	unsigned long quirks;
fdb1d7be WD	94	unsigned long pgsize_bitmap;
	95	unsigned int ias;
	96	unsigned int oas;
4f41845b	97	bool coherent_walk;
298f7889	98	const struct iommu_flush_ops *tlb;
f8d54961	99	struct device *iommu_dev;
fdb1d7be WD	100
	101	/* Low-level data specific to the table format */
	102	union {
e1d3c0fd	103	struct {
d1e5f26f	104	u64 ttbr;
fb485eb1 RM	105	struct {
	106	u32 ips:3;
	107	u32 tg:2;
	108	u32 sh:2;
	109	u32 orgn:2;
	110	u32 irgn:2;
	111	u32 tsz:6;
	112	} tcr;
205577ab	113	u64 mair;
e1d3c0fd WD	114	} arm_lpae_s1_cfg;
	115
	116	struct {
	117	u64 vttbr;
ac4b80e5 WD	118	struct {
	119	u32 ps:3;
	120	u32 tg:2;
	121	u32 sh:2;
	122	u32 orgn:2;
	123	u32 irgn:2;
	124	u32 sl:2;
	125	u32 tsz:6;
	126	} vtcr;
e1d3c0fd	127	} arm_lpae_s2_cfg;
e5fc9753 RM	128
e5fc9753 RM	129	struct {
d1e5f26f	130	u32 ttbr;
e5fc9753 RM	131	u32 tcr;
	132	u32 nmrr;
	133	u32 prrr;
	134	} arm_v7s_cfg;
d08d42de RH	135
	136	struct {
	137	u64 transtab;
	138	u64 memattr;
	139	} arm_mali_lpae_cfg;
892384cd SP	140
	141	struct {
	142	u64 ttbr[4];
	143	u32 n_ttbrs;
	144	} apple_dart_cfg;
fdb1d7be WD	145	};
	146	};
	147
	148	/**
	149	* struct io_pgtable_ops - Page table manipulation API for IOMMU drivers.
	150	*
	151	* @map: Map a physically contiguous memory region.
ca073b55	152	* @map_pages: Map a physically contiguous range of pages of the same size.
fdb1d7be	153	* @unmap: Unmap a physically contiguous memory region.
374c1559	154	* @unmap_pages: Unmap a range of virtually contiguous pages of the same size.
fdb1d7be WD	155	* @iova_to_phys: Translate iova to physical address.
	156	*
	157	* These functions map directly onto the iommu_ops member functions with
	158	* the same names.
	159	*/
	160	struct io_pgtable_ops {
	161	int (map)(struct io_pgtable_ops ops, unsigned long iova,
f34ce7a7	162	phys_addr_t paddr, size_t size, int prot, gfp_t gfp);
ca073b55 IM	163	int (map_pages)(struct io_pgtable_ops ops, unsigned long iova,
	164	phys_addr_t paddr, size_t pgsize, size_t pgcount,
	165	int prot, gfp_t gfp, size_t *mapped);
193e67c0	166	size_t (unmap)(struct io_pgtable_ops ops, unsigned long iova,
a2d3a382	167	size_t size, struct iommu_iotlb_gather *gather);
374c1559 IM	168	size_t (unmap_pages)(struct io_pgtable_ops ops, unsigned long iova,
	169	size_t pgsize, size_t pgcount,
	170	struct iommu_iotlb_gather *gather);
fdb1d7be WD	171	phys_addr_t (iova_to_phys)(struct io_pgtable_ops ops,
	172	unsigned long iova);
	173	};
	174
	175	/**
	176	* alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU.
	177	*
	178	* @fmt: The page table format.
	179	* @cfg: The page table configuration. This will be modified to represent
	180	* the configuration actually provided by the allocator (e.g. the
	181	* pgsize_bitmap may be restricted).
	182	* @cookie: An opaque token provided by the IOMMU driver and passed back to
	183	* the callback routines in cfg->tlb.
	184	*/
	185	struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt,
	186	struct io_pgtable_cfg *cfg,
	187	void *cookie);
	188
	189	/**
	190	* free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller
	191	* must ensure that the page table is no longer
	192	* live, but the TLB can be dirty.
	193	*
	194	* @ops: The ops returned from alloc_io_pgtable_ops.
	195	*/
	196	void free_io_pgtable_ops(struct io_pgtable_ops *ops);
	197
	198
	199	/*
	200	* Internal structures for page table allocator implementations.
	201	*/
	202
	203	/**
	204	* struct io_pgtable - Internal structure describing a set of page tables.
	205	*
	206	* @fmt: The page table format.
	207	* @cookie: An opaque token provided by the IOMMU driver and passed back to
	208	* any callback routines.
	209	* @cfg: A copy of the page table configuration.
	210	* @ops: The page table operations in use for this set of page tables.
	211	*/
	212	struct io_pgtable {
	213	enum io_pgtable_fmt fmt;
	214	void *cookie;
	215	struct io_pgtable_cfg cfg;
	216	struct io_pgtable_ops ops;
	217	};
	218
fdc38967 RM	219	#define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops)
fdc38967 RM	220
507e4c9d RM	221	static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop)
507e4c9d RM	222	{
77e0992a YW	223	if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_all)
77e0992a YW	224	iop->cfg.tlb->tlb_flush_all(iop->cookie);
507e4c9d RM	225	}
507e4c9d RM	226
10b7a7d9 WD	227	static inline void
	228	io_pgtable_tlb_flush_walk(struct io_pgtable *iop, unsigned long iova,
	229	size_t size, size_t granule)
	230	{
77e0992a YW	231	if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_walk)
77e0992a YW	232	iop->cfg.tlb->tlb_flush_walk(iova, size, granule, iop->cookie);
10b7a7d9 WD	233	}
10b7a7d9 WD	234
abfd6fe0	235	static inline void
3951c41a WD	236	io_pgtable_tlb_add_page(struct io_pgtable *iop,
3951c41a WD	237	struct iommu_iotlb_gather * gather, unsigned long iova,
abfd6fe0	238	size_t granule)
507e4c9d	239	{
77e0992a	240	if (iop->cfg.tlb && iop->cfg.tlb->tlb_add_page)
3951c41a	241	iop->cfg.tlb->tlb_add_page(gather, iova, granule, iop->cookie);
507e4c9d RM	242	}
507e4c9d RM	243
fdb1d7be WD	244	/**
	245	* struct io_pgtable_init_fns - Alloc/free a set of page tables for a
	246	* particular format.
	247	*
	248	* @alloc: Allocate a set of page tables described by cfg.
	249	* @free: Free the page tables associated with iop.
	250	*/
	251	struct io_pgtable_init_fns {
	252	struct io_pgtable (alloc)(struct io_pgtable_cfg cfg, void cookie);
	253	void (free)(struct io_pgtable iop);
	254	};
	255
2e169bb3 JR	256	extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns;
	257	extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns;
	258	extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns;
	259	extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns;
e5fc9753	260	extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns;
d08d42de	261	extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns;
c9b258c6	262	extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns;
892384cd	263	extern struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns;
2e169bb3	264
fdb1d7be	265	#endif /* __IO_PGTABLE_H */