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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
fdb1d7be WD |
2 | #ifndef __IO_PGTABLE_H |
3 | #define __IO_PGTABLE_H | |
a2d3a382 | 4 | |
e5fc9753 | 5 | #include <linux/bitops.h> |
a2d3a382 | 6 | #include <linux/iommu.h> |
fdb1d7be WD |
7 | |
8 | /* | |
9 | * Public API for use by IOMMU drivers | |
10 | */ | |
11 | enum io_pgtable_fmt { | |
e1d3c0fd WD |
12 | ARM_32_LPAE_S1, |
13 | ARM_32_LPAE_S2, | |
14 | ARM_64_LPAE_S1, | |
15 | ARM_64_LPAE_S2, | |
e5fc9753 | 16 | ARM_V7S, |
d08d42de | 17 | ARM_MALI_LPAE, |
c9b258c6 | 18 | AMD_IOMMU_V1, |
aaac38f6 | 19 | AMD_IOMMU_V2, |
892384cd | 20 | APPLE_DART, |
dc09fe1c | 21 | APPLE_DART2, |
fdb1d7be WD |
22 | IO_PGTABLE_NUM_FMTS, |
23 | }; | |
24 | ||
25 | /** | |
298f7889 | 26 | * struct iommu_flush_ops - IOMMU callbacks for TLB and page table management. |
fdb1d7be | 27 | * |
3445545b WD |
28 | * @tlb_flush_all: Synchronously invalidate the entire TLB context. |
29 | * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state | |
30 | * (sometimes referred to as the "walk cache") for a virtual | |
31 | * address range. | |
abfd6fe0 | 32 | * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a |
3951c41a WD |
33 | * single page. IOMMUs that cannot batch TLB invalidation |
34 | * operations efficiently will typically issue them here, but | |
35 | * others may decide to update the iommu_iotlb_gather structure | |
aae4c8e2 | 36 | * and defer the invalidation until iommu_iotlb_sync() instead. |
fdb1d7be WD |
37 | * |
38 | * Note that these can all be called in atomic context and must therefore | |
39 | * not block. | |
40 | */ | |
298f7889 | 41 | struct iommu_flush_ops { |
fdb1d7be | 42 | void (*tlb_flush_all)(void *cookie); |
3445545b WD |
43 | void (*tlb_flush_walk)(unsigned long iova, size_t size, size_t granule, |
44 | void *cookie); | |
3951c41a WD |
45 | void (*tlb_add_page)(struct iommu_iotlb_gather *gather, |
46 | unsigned long iova, size_t granule, void *cookie); | |
fdb1d7be WD |
47 | }; |
48 | ||
49 | /** | |
50 | * struct io_pgtable_cfg - Configuration data for a set of page tables. | |
51 | * | |
52 | * @quirks: A bitmap of hardware quirks that require some special | |
53 | * action by the low-level page table allocator. | |
54 | * @pgsize_bitmap: A bitmap of page sizes supported by this set of page | |
55 | * tables. | |
56 | * @ias: Input address (iova) size, in bits. | |
57 | * @oas: Output address (paddr) size, in bits. | |
4f41845b WD |
58 | * @coherent_walk A flag to indicate whether or not page table walks made |
59 | * by the IOMMU are coherent with the CPU caches. | |
fdb1d7be | 60 | * @tlb: TLB management callbacks for this set of tables. |
f8d54961 RM |
61 | * @iommu_dev: The device representing the DMA configuration for the |
62 | * page table walker. | |
fdb1d7be WD |
63 | */ |
64 | struct io_pgtable_cfg { | |
3850db49 RM |
65 | /* |
66 | * IO_PGTABLE_QUIRK_ARM_NS: (ARM formats) Set NS and NSTABLE bits in | |
67 | * stage 1 PTEs, for hardware which insists on validating them | |
68 | * even in non-secure state where they should normally be ignored. | |
69 | * | |
70 | * IO_PGTABLE_QUIRK_NO_PERMS: Ignore the IOMMU_READ, IOMMU_WRITE and | |
71 | * IOMMU_NOEXEC flags and map everything with full access, for | |
72 | * hardware which does not implement the permissions of a given | |
73 | * format, and/or requires some format-specific default value. | |
74 | * | |
4c019de6 | 75 | * IO_PGTABLE_QUIRK_ARM_MTK_EXT: (ARM v7s format) MediaTek IOMMUs extend |
40596d2f YW |
76 | * to support up to 35 bits PA where the bit32, bit33 and bit34 are |
77 | * encoded in the bit9, bit4 and bit5 of the PTE respectively. | |
81b3c252 | 78 | * |
bfdd2313 YW |
79 | * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs |
80 | * extend the translation table base support up to 35 bits PA, the | |
81 | * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT. | |
82 | * | |
db690301 RM |
83 | * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table |
84 | * for use in the upper half of a split address space. | |
e67890c9 SPR |
85 | * |
86 | * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability | |
87 | * attributes set in the TCR for a non-coherent page-table walker. | |
3850db49 | 88 | */ |
bfdd2313 YW |
89 | #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) |
90 | #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) | |
91 | #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) | |
92 | #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4) | |
93 | #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) | |
94 | #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6) | |
3850db49 | 95 | unsigned long quirks; |
fdb1d7be WD |
96 | unsigned long pgsize_bitmap; |
97 | unsigned int ias; | |
98 | unsigned int oas; | |
4f41845b | 99 | bool coherent_walk; |
298f7889 | 100 | const struct iommu_flush_ops *tlb; |
f8d54961 | 101 | struct device *iommu_dev; |
fdb1d7be WD |
102 | |
103 | /* Low-level data specific to the table format */ | |
104 | union { | |
e1d3c0fd | 105 | struct { |
d1e5f26f | 106 | u64 ttbr; |
fb485eb1 RM |
107 | struct { |
108 | u32 ips:3; | |
109 | u32 tg:2; | |
110 | u32 sh:2; | |
111 | u32 orgn:2; | |
112 | u32 irgn:2; | |
113 | u32 tsz:6; | |
114 | } tcr; | |
205577ab | 115 | u64 mair; |
e1d3c0fd WD |
116 | } arm_lpae_s1_cfg; |
117 | ||
118 | struct { | |
119 | u64 vttbr; | |
ac4b80e5 WD |
120 | struct { |
121 | u32 ps:3; | |
122 | u32 tg:2; | |
123 | u32 sh:2; | |
124 | u32 orgn:2; | |
125 | u32 irgn:2; | |
126 | u32 sl:2; | |
127 | u32 tsz:6; | |
128 | } vtcr; | |
e1d3c0fd | 129 | } arm_lpae_s2_cfg; |
e5fc9753 RM |
130 | |
131 | struct { | |
d1e5f26f | 132 | u32 ttbr; |
e5fc9753 RM |
133 | u32 tcr; |
134 | u32 nmrr; | |
135 | u32 prrr; | |
136 | } arm_v7s_cfg; | |
d08d42de RH |
137 | |
138 | struct { | |
139 | u64 transtab; | |
140 | u64 memattr; | |
141 | } arm_mali_lpae_cfg; | |
892384cd SP |
142 | |
143 | struct { | |
144 | u64 ttbr[4]; | |
145 | u32 n_ttbrs; | |
146 | } apple_dart_cfg; | |
fdb1d7be WD |
147 | }; |
148 | }; | |
149 | ||
150 | /** | |
151 | * struct io_pgtable_ops - Page table manipulation API for IOMMU drivers. | |
152 | * | |
ca073b55 | 153 | * @map_pages: Map a physically contiguous range of pages of the same size. |
374c1559 | 154 | * @unmap_pages: Unmap a range of virtually contiguous pages of the same size. |
fdb1d7be WD |
155 | * @iova_to_phys: Translate iova to physical address. |
156 | * | |
157 | * These functions map directly onto the iommu_ops member functions with | |
158 | * the same names. | |
159 | */ | |
160 | struct io_pgtable_ops { | |
ca073b55 IM |
161 | int (*map_pages)(struct io_pgtable_ops *ops, unsigned long iova, |
162 | phys_addr_t paddr, size_t pgsize, size_t pgcount, | |
163 | int prot, gfp_t gfp, size_t *mapped); | |
374c1559 IM |
164 | size_t (*unmap_pages)(struct io_pgtable_ops *ops, unsigned long iova, |
165 | size_t pgsize, size_t pgcount, | |
166 | struct iommu_iotlb_gather *gather); | |
fdb1d7be WD |
167 | phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops, |
168 | unsigned long iova); | |
169 | }; | |
170 | ||
171 | /** | |
172 | * alloc_io_pgtable_ops() - Allocate a page table allocator for use by an IOMMU. | |
173 | * | |
174 | * @fmt: The page table format. | |
175 | * @cfg: The page table configuration. This will be modified to represent | |
176 | * the configuration actually provided by the allocator (e.g. the | |
177 | * pgsize_bitmap may be restricted). | |
178 | * @cookie: An opaque token provided by the IOMMU driver and passed back to | |
179 | * the callback routines in cfg->tlb. | |
180 | */ | |
181 | struct io_pgtable_ops *alloc_io_pgtable_ops(enum io_pgtable_fmt fmt, | |
182 | struct io_pgtable_cfg *cfg, | |
183 | void *cookie); | |
184 | ||
185 | /** | |
186 | * free_io_pgtable_ops() - Free an io_pgtable_ops structure. The caller | |
187 | * *must* ensure that the page table is no longer | |
188 | * live, but the TLB can be dirty. | |
189 | * | |
190 | * @ops: The ops returned from alloc_io_pgtable_ops. | |
191 | */ | |
192 | void free_io_pgtable_ops(struct io_pgtable_ops *ops); | |
193 | ||
194 | ||
195 | /* | |
196 | * Internal structures for page table allocator implementations. | |
197 | */ | |
198 | ||
199 | /** | |
200 | * struct io_pgtable - Internal structure describing a set of page tables. | |
201 | * | |
202 | * @fmt: The page table format. | |
203 | * @cookie: An opaque token provided by the IOMMU driver and passed back to | |
204 | * any callback routines. | |
205 | * @cfg: A copy of the page table configuration. | |
206 | * @ops: The page table operations in use for this set of page tables. | |
207 | */ | |
208 | struct io_pgtable { | |
209 | enum io_pgtable_fmt fmt; | |
210 | void *cookie; | |
211 | struct io_pgtable_cfg cfg; | |
212 | struct io_pgtable_ops ops; | |
213 | }; | |
214 | ||
fdc38967 RM |
215 | #define io_pgtable_ops_to_pgtable(x) container_of((x), struct io_pgtable, ops) |
216 | ||
507e4c9d RM |
217 | static inline void io_pgtable_tlb_flush_all(struct io_pgtable *iop) |
218 | { | |
77e0992a YW |
219 | if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_all) |
220 | iop->cfg.tlb->tlb_flush_all(iop->cookie); | |
507e4c9d RM |
221 | } |
222 | ||
10b7a7d9 WD |
223 | static inline void |
224 | io_pgtable_tlb_flush_walk(struct io_pgtable *iop, unsigned long iova, | |
225 | size_t size, size_t granule) | |
226 | { | |
77e0992a YW |
227 | if (iop->cfg.tlb && iop->cfg.tlb->tlb_flush_walk) |
228 | iop->cfg.tlb->tlb_flush_walk(iova, size, granule, iop->cookie); | |
10b7a7d9 WD |
229 | } |
230 | ||
abfd6fe0 | 231 | static inline void |
3951c41a WD |
232 | io_pgtable_tlb_add_page(struct io_pgtable *iop, |
233 | struct iommu_iotlb_gather * gather, unsigned long iova, | |
abfd6fe0 | 234 | size_t granule) |
507e4c9d | 235 | { |
77e0992a | 236 | if (iop->cfg.tlb && iop->cfg.tlb->tlb_add_page) |
3951c41a | 237 | iop->cfg.tlb->tlb_add_page(gather, iova, granule, iop->cookie); |
507e4c9d RM |
238 | } |
239 | ||
fdb1d7be WD |
240 | /** |
241 | * struct io_pgtable_init_fns - Alloc/free a set of page tables for a | |
242 | * particular format. | |
243 | * | |
244 | * @alloc: Allocate a set of page tables described by cfg. | |
245 | * @free: Free the page tables associated with iop. | |
246 | */ | |
247 | struct io_pgtable_init_fns { | |
248 | struct io_pgtable *(*alloc)(struct io_pgtable_cfg *cfg, void *cookie); | |
249 | void (*free)(struct io_pgtable *iop); | |
250 | }; | |
251 | ||
2e169bb3 JR |
252 | extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns; |
253 | extern struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns; | |
254 | extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns; | |
255 | extern struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns; | |
e5fc9753 | 256 | extern struct io_pgtable_init_fns io_pgtable_arm_v7s_init_fns; |
d08d42de | 257 | extern struct io_pgtable_init_fns io_pgtable_arm_mali_lpae_init_fns; |
c9b258c6 | 258 | extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v1_init_fns; |
aaac38f6 | 259 | extern struct io_pgtable_init_fns io_pgtable_amd_iommu_v2_init_fns; |
892384cd | 260 | extern struct io_pgtable_init_fns io_pgtable_apple_dart_init_fns; |
2e169bb3 | 261 | |
fdb1d7be | 262 | #endif /* __IO_PGTABLE_H */ |