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3b20eb23 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
ba395927 | 2 | /* |
2f26e0a9 DW |
3 | * Copyright © 2006-2015, Intel Corporation. |
4 | * | |
5 | * Authors: Ashok Raj <ashok.raj@intel.com> | |
6 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
7 | * David Woodhouse <David.Woodhouse@intel.com> | |
ba395927 KA |
8 | */ |
9 | ||
10 | #ifndef _INTEL_IOMMU_H_ | |
11 | #define _INTEL_IOMMU_H_ | |
12 | ||
13 | #include <linux/types.h> | |
38717946 | 14 | #include <linux/iova.h> |
ba395927 | 15 | #include <linux/io.h> |
2f26e0a9 | 16 | #include <linux/idr.h> |
2f26e0a9 DW |
17 | #include <linux/mmu_notifier.h> |
18 | #include <linux/list.h> | |
b0119e87 | 19 | #include <linux/iommu.h> |
61012985 | 20 | #include <linux/io-64-nonatomic-lo-hi.h> |
9ddbfb42 | 21 | #include <linux/dmar.h> |
61012985 | 22 | |
fe962e90 | 23 | #include <asm/cacheflush.h> |
5b6985ce | 24 | #include <asm/iommu.h> |
f661197e | 25 | |
ba395927 | 26 | /* |
daedaa33 | 27 | * VT-d hardware uses 4KiB page size regardless of host page size. |
ba395927 | 28 | */ |
daedaa33 LB |
29 | #define VTD_PAGE_SHIFT (12) |
30 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) | |
31 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) | |
32 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) | |
33 | ||
34 | #define VTD_STRIDE_SHIFT (9) | |
35 | #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) | |
36 | ||
ddf09b6d LB |
37 | #define DMA_PTE_READ BIT_ULL(0) |
38 | #define DMA_PTE_WRITE BIT_ULL(1) | |
39 | #define DMA_PTE_LARGE_PAGE BIT_ULL(7) | |
40 | #define DMA_PTE_SNP BIT_ULL(11) | |
41 | ||
42 | #define DMA_FL_PTE_PRESENT BIT_ULL(0) | |
43 | #define DMA_FL_PTE_XD BIT_ULL(63) | |
daedaa33 | 44 | |
b0d1f874 JP |
45 | #define ADDR_WIDTH_5LEVEL (57) |
46 | #define ADDR_WIDTH_4LEVEL (48) | |
47 | ||
daedaa33 LB |
48 | #define CONTEXT_TT_MULTI_LEVEL 0 |
49 | #define CONTEXT_TT_DEV_IOTLB 1 | |
50 | #define CONTEXT_TT_PASS_THROUGH 2 | |
1c4f88b7 | 51 | #define CONTEXT_PASIDE BIT_ULL(3) |
ba395927 | 52 | |
daedaa33 LB |
53 | /* |
54 | * Intel IOMMU register specification per version 1.0 public spec. | |
55 | */ | |
ba395927 KA |
56 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ |
57 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
58 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
59 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
60 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
61 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
62 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
63 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
64 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
65 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
66 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
67 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
68 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
69 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
70 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
71 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
72 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
73 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
74 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
75 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
6ba6c3a4 | 76 | #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ |
fe962e90 | 77 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ |
82aeef0b | 78 | #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ |
2ae21010 | 79 | #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ |
1208225c DW |
80 | #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ |
81 | #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ | |
82 | #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ | |
83 | #define DMAR_PRS_REG 0xdc /* Page request status register */ | |
84 | #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ | |
85 | #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ | |
86 | #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ | |
87 | #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ | |
4a2d80db SM |
88 | #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */ |
89 | #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */ | |
90 | #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */ | |
91 | #define DMAR_MTRR_FIX16K_80000_REG 0x128 | |
92 | #define DMAR_MTRR_FIX16K_A0000_REG 0x130 | |
93 | #define DMAR_MTRR_FIX4K_C0000_REG 0x138 | |
94 | #define DMAR_MTRR_FIX4K_C8000_REG 0x140 | |
95 | #define DMAR_MTRR_FIX4K_D0000_REG 0x148 | |
96 | #define DMAR_MTRR_FIX4K_D8000_REG 0x150 | |
97 | #define DMAR_MTRR_FIX4K_E0000_REG 0x158 | |
98 | #define DMAR_MTRR_FIX4K_E8000_REG 0x160 | |
99 | #define DMAR_MTRR_FIX4K_F0000_REG 0x168 | |
100 | #define DMAR_MTRR_FIX4K_F8000_REG 0x170 | |
101 | #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */ | |
102 | #define DMAR_MTRR_PHYSMASK0_REG 0x188 | |
103 | #define DMAR_MTRR_PHYSBASE1_REG 0x190 | |
104 | #define DMAR_MTRR_PHYSMASK1_REG 0x198 | |
105 | #define DMAR_MTRR_PHYSBASE2_REG 0x1a0 | |
106 | #define DMAR_MTRR_PHYSMASK2_REG 0x1a8 | |
107 | #define DMAR_MTRR_PHYSBASE3_REG 0x1b0 | |
108 | #define DMAR_MTRR_PHYSMASK3_REG 0x1b8 | |
109 | #define DMAR_MTRR_PHYSBASE4_REG 0x1c0 | |
110 | #define DMAR_MTRR_PHYSMASK4_REG 0x1c8 | |
111 | #define DMAR_MTRR_PHYSBASE5_REG 0x1d0 | |
112 | #define DMAR_MTRR_PHYSMASK5_REG 0x1d8 | |
113 | #define DMAR_MTRR_PHYSBASE6_REG 0x1e0 | |
114 | #define DMAR_MTRR_PHYSMASK6_REG 0x1e8 | |
115 | #define DMAR_MTRR_PHYSBASE7_REG 0x1f0 | |
116 | #define DMAR_MTRR_PHYSMASK7_REG 0x1f8 | |
117 | #define DMAR_MTRR_PHYSBASE8_REG 0x200 | |
118 | #define DMAR_MTRR_PHYSMASK8_REG 0x208 | |
119 | #define DMAR_MTRR_PHYSBASE9_REG 0x210 | |
120 | #define DMAR_MTRR_PHYSMASK9_REG 0x218 | |
121 | #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */ | |
122 | #define DMAR_VCMD_REG 0xe10 /* Virtual command register */ | |
123 | #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */ | |
ba395927 KA |
124 | |
125 | #define OFFSET_STRIDE (9) | |
50d3fb56 | 126 | |
50d3fb56 DW |
127 | #define dmar_readq(a) readq(a) |
128 | #define dmar_writeq(a,v) writeq(v,a) | |
ba3b01d7 MD |
129 | #define dmar_readl(a) readl(a) |
130 | #define dmar_writel(a, v) writel(v, a) | |
ba395927 KA |
131 | |
132 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
133 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
134 | ||
135 | /* | |
136 | * Decoding Capability Register | |
137 | */ | |
f1ac10c2 | 138 | #define cap_5lp_support(c) (((c) >> 60) & 1) |
07c09787 | 139 | #define cap_pi_support(c) (((c) >> 59) & 1) |
59103caa | 140 | #define cap_fl1gp_support(c) (((c) >> 56) & 1) |
ba395927 KA |
141 | #define cap_read_drain(c) (((c) >> 55) & 1) |
142 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
143 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
144 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
145 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
146 | ||
147 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
148 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
149 | * OFFSET_STRIDE) + 21) | |
150 | ||
151 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
152 | #define cap_max_fault_reg_offset(c) \ | |
153 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
154 | ||
155 | #define cap_zlr(c) (((c) >> 22) & 1) | |
156 | #define cap_isoch(c) (((c) >> 23) & 1) | |
157 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
158 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
159 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
160 | #define cap_phmr(c) (((c) >> 6) & 1) | |
161 | #define cap_plmr(c) (((c) >> 5) & 1) | |
162 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
163 | #define cap_afl(c) (((c) >> 3) & 1) | |
164 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
165 | /* | |
166 | * Extended Capability Register | |
167 | */ | |
168 | ||
6f7db75e | 169 | #define ecap_smpwc(e) (((e) >> 48) & 0x1) |
437f35e1 | 170 | #define ecap_flts(e) (((e) >> 47) & 0x1) |
6f7db75e | 171 | #define ecap_slts(e) (((e) >> 46) & 0x1) |
765b6a98 | 172 | #define ecap_smts(e) (((e) >> 43) & 0x1) |
0f725561 | 173 | #define ecap_dit(e) ((e >> 41) & 0x1) |
bd00c606 | 174 | #define ecap_pasid(e) ((e >> 40) & 0x1) |
4423f5e7 DW |
175 | #define ecap_pss(e) ((e >> 35) & 0x1f) |
176 | #define ecap_eafs(e) ((e >> 34) & 0x1) | |
177 | #define ecap_nwfs(e) ((e >> 33) & 0x1) | |
178 | #define ecap_srs(e) ((e >> 31) & 0x1) | |
179 | #define ecap_ers(e) ((e >> 30) & 0x1) | |
180 | #define ecap_prs(e) ((e >> 29) & 0x1) | |
2db1581e | 181 | #define ecap_broken_pasid(e) ((e >> 28) & 0x1) |
4423f5e7 DW |
182 | #define ecap_dis(e) ((e >> 27) & 0x1) |
183 | #define ecap_nest(e) ((e >> 26) & 0x1) | |
184 | #define ecap_mts(e) ((e >> 25) & 0x1) | |
185 | #define ecap_ecs(e) ((e >> 24) & 0x1) | |
ba395927 | 186 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) |
44caf2f3 | 187 | #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) |
ba395927 | 188 | #define ecap_coherent(e) ((e) & 0x1) |
fe962e90 | 189 | #define ecap_qis(e) ((e) & 0x2) |
4ed0d3e6 | 190 | #define ecap_pass_through(e) ((e >> 6) & 0x1) |
ad3ad3f6 SS |
191 | #define ecap_eim_support(e) ((e >> 4) & 0x1) |
192 | #define ecap_ir_support(e) ((e >> 3) & 0x1) | |
93a23a72 | 193 | #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) |
b6fcb33a | 194 | #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) |
58c610bd | 195 | #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ |
ba395927 KA |
196 | |
197 | /* IOTLB_REG */ | |
3481f210 | 198 | #define DMA_TLB_FLUSH_GRANU_OFFSET 60 |
ba395927 KA |
199 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
200 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
201 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
aaa59306 CT |
202 | #define DMA_TLB_IIRG(type) ((type >> 60) & 3) |
203 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) | |
ba395927 KA |
204 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) |
205 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
206 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
207 | #define DMA_TLB_IVT (((u64)1) << 63) | |
208 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
209 | #define DMA_TLB_MAX_SIZE (0x3f) | |
210 | ||
fe962e90 | 211 | /* INVALID_DESC */ |
3481f210 | 212 | #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
aaa59306 CT |
213 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) |
214 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) | |
215 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) | |
fe962e90 SS |
216 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) |
217 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
218 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
219 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
220 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
221 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
222 | ||
f8bab735 | 223 | /* PMEN_REG */ |
224 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
225 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
226 | ||
ba395927 KA |
227 | /* GCMD_REG */ |
228 | #define DMA_GCMD_TE (((u32)1) << 31) | |
229 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
230 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
231 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
232 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
2ae21010 SS |
233 | #define DMA_GCMD_QIE (((u32)1) << 26) |
234 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | |
235 | #define DMA_GCMD_IRE (((u32) 1) << 25) | |
161fde08 | 236 | #define DMA_GCMD_CFI (((u32) 1) << 23) |
ba395927 KA |
237 | |
238 | /* GSTS_REG */ | |
239 | #define DMA_GSTS_TES (((u32)1) << 31) | |
240 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
241 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
242 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
243 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
2ae21010 SS |
244 | #define DMA_GSTS_QIES (((u32)1) << 26) |
245 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | |
246 | #define DMA_GSTS_IRES (((u32)1) << 25) | |
161fde08 | 247 | #define DMA_GSTS_CFIS (((u32)1) << 23) |
ba395927 | 248 | |
4423f5e7 DW |
249 | /* DMA_RTADDR_REG */ |
250 | #define DMA_RTADDR_RTT (((u64)1) << 11) | |
7373a8cc | 251 | #define DMA_RTADDR_SMT (((u64)1) << 10) |
4423f5e7 | 252 | |
ba395927 KA |
253 | /* CCMD_REG */ |
254 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
255 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
256 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
257 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
258 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
259 | #define DMA_CCMD_MASK_NOBIT 0 | |
260 | #define DMA_CCMD_MASK_1BIT 1 | |
261 | #define DMA_CCMD_MASK_2BIT 2 | |
262 | #define DMA_CCMD_MASK_3BIT 3 | |
263 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
264 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
265 | ||
266 | /* FECTL_REG */ | |
267 | #define DMA_FECTL_IM (((u32)1) << 31) | |
268 | ||
269 | /* FSTS_REG */ | |
b1d03c1d DS |
270 | #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ |
271 | #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ | |
272 | #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ | |
273 | #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ | |
274 | #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ | |
275 | #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ | |
ba395927 KA |
276 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) |
277 | ||
278 | /* FRCD_REG, 32 bits access */ | |
279 | #define DMA_FRCD_F (((u32)1) << 31) | |
280 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
281 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
282 | #define dma_frcd_source_id(c) (c & 0xffff) | |
fd730007 KMP |
283 | #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff) |
284 | #define dma_frcd_pasid_present(c) (((c) >> 31) & 1) | |
5b6985ce FY |
285 | /* low 64 bit */ |
286 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) | |
287 | ||
46924008 DW |
288 | /* PRS_REG */ |
289 | #define DMA_PRS_PPR ((u32)1) | |
290 | ||
5b6985ce FY |
291 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ |
292 | do { \ | |
293 | cycles_t start_time = get_cycles(); \ | |
294 | while (1) { \ | |
295 | sts = op(iommu->reg + offset); \ | |
296 | if (cond) \ | |
297 | break; \ | |
cf1337f0 | 298 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ |
5b6985ce FY |
299 | panic("DMAR hardware is malfunctioning\n"); \ |
300 | cpu_relax(); \ | |
301 | } \ | |
302 | } while (0) | |
cf1337f0 | 303 | |
fe962e90 SS |
304 | #define QI_LENGTH 256 /* queue length */ |
305 | ||
306 | enum { | |
307 | QI_FREE, | |
308 | QI_IN_USE, | |
6ba6c3a4 YZ |
309 | QI_DONE, |
310 | QI_ABORT | |
fe962e90 SS |
311 | }; |
312 | ||
313 | #define QI_CC_TYPE 0x1 | |
314 | #define QI_IOTLB_TYPE 0x2 | |
315 | #define QI_DIOTLB_TYPE 0x3 | |
316 | #define QI_IEC_TYPE 0x4 | |
317 | #define QI_IWD_TYPE 0x5 | |
2f26e0a9 DW |
318 | #define QI_EIOTLB_TYPE 0x6 |
319 | #define QI_PC_TYPE 0x7 | |
320 | #define QI_DEIOTLB_TYPE 0x8 | |
a222a7f0 DW |
321 | #define QI_PGRP_RESP_TYPE 0x9 |
322 | #define QI_PSTRM_RESP_TYPE 0xa | |
fe962e90 SS |
323 | |
324 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
325 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
326 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
327 | ||
328 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
329 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
330 | ||
3481f210 YS |
331 | #define QI_IOTLB_DID(did) (((u64)did) << 16) |
332 | #define QI_IOTLB_DR(dr) (((u64)dr) << 7) | |
333 | #define QI_IOTLB_DW(dw) (((u64)dw) << 6) | |
334 | #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) | |
5b6985ce | 335 | #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) |
3481f210 | 336 | #define QI_IOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 337 | #define QI_IOTLB_AM(am) (((u8)am) & 0x3f) |
3481f210 YS |
338 | |
339 | #define QI_CC_FM(fm) (((u64)fm) << 48) | |
340 | #define QI_CC_SID(sid) (((u64)sid) << 32) | |
341 | #define QI_CC_DID(did) (((u64)did) << 16) | |
342 | #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) | |
343 | ||
6ba6c3a4 YZ |
344 | #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
345 | #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) | |
346 | #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
4e7120d7 EA |
347 | #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
348 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
6ba6c3a4 YZ |
349 | #define QI_DEV_IOTLB_SIZE 1 |
350 | #define QI_DEV_IOTLB_MAX_INVS 32 | |
351 | ||
2f26e0a9 DW |
352 | #define QI_PC_PASID(pasid) (((u64)pasid) << 32) |
353 | #define QI_PC_DID(did) (((u64)did) << 16) | |
354 | #define QI_PC_GRAN(gran) (((u64)gran) << 4) | |
355 | ||
61a06a16 JP |
356 | /* PASID cache invalidation granu */ |
357 | #define QI_PC_ALL_PASIDS 0 | |
358 | #define QI_PC_PASID_SEL 1 | |
2f26e0a9 DW |
359 | |
360 | #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
2f26e0a9 | 361 | #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 362 | #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) |
2f26e0a9 DW |
363 | #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) |
364 | #define QI_EIOTLB_DID(did) (((u64)did) << 16) | |
365 | #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) | |
366 | ||
61a06a16 JP |
367 | /* QI Dev-IOTLB inv granu */ |
368 | #define QI_DEV_IOTLB_GRAN_ALL 1 | |
369 | #define QI_DEV_IOTLB_GRAN_PASID_SEL 0 | |
370 | ||
2f26e0a9 DW |
371 | #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) |
372 | #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) | |
373 | #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) | |
374 | #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) | |
aaa59306 CT |
375 | #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
376 | #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) | |
4e7120d7 EA |
377 | #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
378 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
2f26e0a9 DW |
379 | #define QI_DEV_EIOTLB_MAX_INVS 32 |
380 | ||
5b438f4b | 381 | /* Page group response descriptor QW0 */ |
a222a7f0 | 382 | #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) |
5b438f4b JP |
383 | #define QI_PGRP_PDP(p) (((u64)(p)) << 5) |
384 | #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) | |
385 | #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) | |
386 | #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) | |
387 | ||
388 | /* Page group response descriptor QW1 */ | |
389 | #define QI_PGRP_LPIG(x) (((u64)(x)) << 2) | |
390 | #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3) | |
a222a7f0 | 391 | |
a222a7f0 DW |
392 | |
393 | #define QI_RESP_SUCCESS 0x0 | |
394 | #define QI_RESP_INVALID 0x1 | |
395 | #define QI_RESP_FAILURE 0xf | |
396 | ||
2f26e0a9 DW |
397 | #define QI_GRAN_NONG_PASID 2 |
398 | #define QI_GRAN_PSI_PASID 3 | |
399 | ||
5d308fc1 LB |
400 | #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap)) |
401 | ||
fe962e90 | 402 | struct qi_desc { |
5d308fc1 LB |
403 | u64 qw0; |
404 | u64 qw1; | |
405 | u64 qw2; | |
406 | u64 qw3; | |
fe962e90 SS |
407 | }; |
408 | ||
409 | struct q_inval { | |
3b8f4048 | 410 | raw_spinlock_t q_lock; |
5d308fc1 | 411 | void *desc; /* invalidation queue */ |
fe962e90 SS |
412 | int *desc_status; /* desc status */ |
413 | int free_head; /* first free entry */ | |
414 | int free_tail; /* last free entry */ | |
415 | int free_cnt; | |
416 | }; | |
417 | ||
d3f13810 | 418 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
419 | /* 1MB - maximum possible interrupt remapping table size */ |
420 | #define INTR_REMAP_PAGE_ORDER 8 | |
421 | #define INTR_REMAP_TABLE_REG_SIZE 0xf | |
af3b358e | 422 | #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf |
2ae21010 | 423 | |
b6fcb33a SS |
424 | #define INTR_REMAP_TABLE_ENTRIES 65536 |
425 | ||
b106ee63 JL |
426 | struct irq_domain; |
427 | ||
2ae21010 SS |
428 | struct ir_table { |
429 | struct irte *base; | |
360eb3c5 | 430 | unsigned long *bitmap; |
2ae21010 SS |
431 | }; |
432 | #endif | |
433 | ||
a77b67d4 | 434 | struct iommu_flush { |
4c25a2c1 DW |
435 | void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, |
436 | u8 fm, u64 type); | |
1f0ef2aa DW |
437 | void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, |
438 | unsigned int size_order, u64 type); | |
a77b67d4 YS |
439 | }; |
440 | ||
f59c7b69 FY |
441 | enum { |
442 | SR_DMAR_FECTL_REG, | |
443 | SR_DMAR_FEDATA_REG, | |
444 | SR_DMAR_FEADDR_REG, | |
445 | SR_DMAR_FEUADDR_REG, | |
446 | MAX_SR_DMAR_REGS | |
447 | }; | |
448 | ||
4158c2ec JR |
449 | #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) |
450 | #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) | |
ff3dc652 | 451 | #define VTD_FLAG_SVM_CAPABLE (1 << 2) |
4158c2ec | 452 | |
cdd3a249 | 453 | extern int intel_iommu_sm; |
e2726dae | 454 | extern spinlock_t device_domain_lock; |
cdd3a249 SPP |
455 | |
456 | #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) | |
457 | #define pasid_supported(iommu) (sm_supported(iommu) && \ | |
458 | ecap_pasid((iommu)->ecap)) | |
459 | ||
8a94ade4 DW |
460 | struct pasid_entry; |
461 | struct pasid_state_entry; | |
a222a7f0 | 462 | struct page_req_dsc; |
8a94ade4 | 463 | |
26b86092 SM |
464 | /* |
465 | * 0: Present | |
466 | * 1-11: Reserved | |
467 | * 12-63: Context Ptr (12 - (haw-1)) | |
468 | * 64-127: Reserved | |
469 | */ | |
470 | struct root_entry { | |
471 | u64 lo; | |
472 | u64 hi; | |
473 | }; | |
474 | ||
475 | /* | |
476 | * low 64 bits: | |
477 | * 0: present | |
478 | * 1: fault processing disable | |
479 | * 2-3: translation type | |
480 | * 12-63: address space root | |
481 | * high 64 bits: | |
482 | * 0-2: address width | |
483 | * 3-6: aval | |
484 | * 8-23: domain id | |
485 | */ | |
486 | struct context_entry { | |
487 | u64 lo; | |
488 | u64 hi; | |
489 | }; | |
490 | ||
b0d1f874 JP |
491 | /* si_domain contains mulitple devices */ |
492 | #define DOMAIN_FLAG_STATIC_IDENTITY BIT(0) | |
493 | ||
494 | /* | |
495 | * When VT-d works in the scalable mode, it allows DMA translation to | |
496 | * happen through either first level or second level page table. This | |
497 | * bit marks that the DMA translation for the domain goes through the | |
498 | * first level page table, otherwise, it goes through the second level. | |
499 | */ | |
500 | #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1) | |
501 | ||
502 | /* | |
503 | * Domain represents a virtual machine which demands iommu nested | |
504 | * translation mode support. | |
505 | */ | |
506 | #define DOMAIN_FLAG_NESTING_MODE BIT(2) | |
507 | ||
9ddbfb42 LB |
508 | struct dmar_domain { |
509 | int nid; /* node id */ | |
510 | ||
511 | unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED]; | |
512 | /* Refcount of devices per iommu */ | |
513 | ||
514 | ||
515 | u16 iommu_did[DMAR_UNITS_SUPPORTED]; | |
516 | /* Domain ids per IOMMU. Use u16 since | |
517 | * domain ids are 16 bit wide according | |
518 | * to VT-d spec, section 9.3 */ | |
67b8e02b | 519 | unsigned int auxd_refcnt; /* Refcount of auxiliary attaching */ |
9ddbfb42 LB |
520 | |
521 | bool has_iotlb_device; | |
522 | struct list_head devices; /* all devices' list */ | |
67b8e02b | 523 | struct list_head auxd; /* link to device's auxiliary list */ |
9ddbfb42 LB |
524 | struct iova_domain iovad; /* iova's that belong to this domain */ |
525 | ||
526 | struct dma_pte *pgd; /* virtual address */ | |
527 | int gaw; /* max guest address width */ | |
528 | ||
529 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
530 | int agaw; | |
531 | ||
532 | int flags; /* flags to find out type of domain */ | |
533 | ||
534 | int iommu_coherency;/* indicate coherency of iommu access */ | |
535 | int iommu_snooping; /* indicate snooping control feature*/ | |
536 | int iommu_count; /* reference count of iommu */ | |
537 | int iommu_superpage;/* Level of superpages supported: | |
538 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
539 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
540 | u64 max_addr; /* maximum mapped address */ | |
541 | ||
67b8e02b LB |
542 | int default_pasid; /* |
543 | * The default pasid used for non-SVM | |
544 | * traffic on mediated devices. | |
545 | */ | |
546 | ||
9ddbfb42 LB |
547 | struct iommu_domain domain; /* generic domain data structure for |
548 | iommu core */ | |
549 | }; | |
550 | ||
ba395927 KA |
551 | struct intel_iommu { |
552 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
6f5cf521 DD |
553 | u64 reg_phys; /* physical address of hw register set */ |
554 | u64 reg_size; /* size of hw register set */ | |
ba395927 KA |
555 | u64 cap; |
556 | u64 ecap; | |
ba395927 | 557 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ |
1f5b3c3f | 558 | raw_spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 559 | int seq_id; /* sequence id of the iommu */ |
1b573683 | 560 | int agaw; /* agaw of this iommu */ |
4ed0d3e6 | 561 | int msagaw; /* max sagaw of this iommu */ |
1208225c | 562 | unsigned int irq, pr_irq; |
67ccac41 | 563 | u16 segment; /* PCI segment# */ |
9d783ba0 | 564 | unsigned char name[13]; /* Device Name */ |
e61d98d8 | 565 | |
d3f13810 | 566 | #ifdef CONFIG_INTEL_IOMMU |
e61d98d8 | 567 | unsigned long *domain_ids; /* bitmap of domains */ |
8bf47816 | 568 | struct dmar_domain ***domains; /* ptr to domains */ |
e61d98d8 | 569 | spinlock_t lock; /* protect context, domain ids */ |
ba395927 KA |
570 | struct root_entry *root_entry; /* virtual address */ |
571 | ||
a77b67d4 | 572 | struct iommu_flush flush; |
8a94ade4 DW |
573 | #endif |
574 | #ifdef CONFIG_INTEL_IOMMU_SVM | |
a222a7f0 DW |
575 | struct page_req_dsc *prq; |
576 | unsigned char prq_name[16]; /* Name for PRQ interrupt */ | |
e61d98d8 | 577 | #endif |
fe962e90 | 578 | struct q_inval *qi; /* Queued invalidation info */ |
f59c7b69 FY |
579 | u32 *iommu_state; /* Store iommu states between suspend and resume.*/ |
580 | ||
d3f13810 | 581 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 | 582 | struct ir_table *ir_table; /* Interrupt remapping info */ |
b106ee63 JL |
583 | struct irq_domain *ir_domain; |
584 | struct irq_domain *ir_msi_domain; | |
2ae21010 | 585 | #endif |
b0119e87 | 586 | struct iommu_device iommu; /* IOMMU core code handle */ |
ee34b32d | 587 | int node; |
4158c2ec | 588 | u32 flags; /* Software defined flags */ |
ba395927 KA |
589 | }; |
590 | ||
9ddbfb42 LB |
591 | /* PCI domain-device relationship */ |
592 | struct device_domain_info { | |
593 | struct list_head link; /* link to domain siblings */ | |
594 | struct list_head global; /* link to global list */ | |
cc580e41 | 595 | struct list_head table; /* link to pasid table */ |
67b8e02b LB |
596 | struct list_head auxiliary_domains; /* auxiliary domains |
597 | * attached to this device | |
598 | */ | |
9ddbfb42 LB |
599 | u8 bus; /* PCI bus number */ |
600 | u8 devfn; /* PCI devfn number */ | |
601 | u16 pfsid; /* SRIOV physical function source ID */ | |
602 | u8 pasid_supported:3; | |
603 | u8 pasid_enabled:1; | |
604 | u8 pri_supported:1; | |
605 | u8 pri_enabled:1; | |
606 | u8 ats_supported:1; | |
607 | u8 ats_enabled:1; | |
95587a75 | 608 | u8 auxd_enabled:1; /* Multiple domains per device */ |
9ddbfb42 LB |
609 | u8 ats_qdep; |
610 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ | |
611 | struct intel_iommu *iommu; /* IOMMU used by this device */ | |
612 | struct dmar_domain *domain; /* pointer to domain */ | |
cc580e41 | 613 | struct pasid_table *pasid_table; /* pasid table */ |
9ddbfb42 LB |
614 | }; |
615 | ||
fe962e90 SS |
616 | static inline void __iommu_flush_cache( |
617 | struct intel_iommu *iommu, void *addr, int size) | |
618 | { | |
619 | if (!ecap_coherent(iommu->ecap)) | |
620 | clflush_cache_range(addr, size); | |
621 | } | |
622 | ||
3db9983e JP |
623 | /* Convert generic struct iommu_domain to private struct dmar_domain */ |
624 | static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) | |
625 | { | |
626 | return container_of(dom, struct dmar_domain, domain); | |
627 | } | |
628 | ||
4f2ed183 LB |
629 | /* |
630 | * 0: readable | |
631 | * 1: writable | |
632 | * 2-6: reserved | |
633 | * 7: super page | |
634 | * 8-10: available | |
635 | * 11: snoop behavior | |
636 | * 12-63: Host physcial address | |
637 | */ | |
638 | struct dma_pte { | |
639 | u64 val; | |
640 | }; | |
641 | ||
642 | static inline void dma_clear_pte(struct dma_pte *pte) | |
643 | { | |
644 | pte->val = 0; | |
645 | } | |
646 | ||
647 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
648 | { | |
649 | #ifdef CONFIG_64BIT | |
ddf09b6d | 650 | return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); |
4f2ed183 LB |
651 | #else |
652 | /* Must have a full atomic 64-bit read */ | |
ddf09b6d LB |
653 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & |
654 | VTD_PAGE_MASK & (~DMA_FL_PTE_XD); | |
4f2ed183 LB |
655 | #endif |
656 | } | |
657 | ||
658 | static inline bool dma_pte_present(struct dma_pte *pte) | |
659 | { | |
660 | return (pte->val & 3) != 0; | |
661 | } | |
662 | ||
663 | static inline bool dma_pte_superpage(struct dma_pte *pte) | |
664 | { | |
665 | return (pte->val & DMA_PTE_LARGE_PAGE); | |
666 | } | |
667 | ||
668 | static inline int first_pte_in_page(struct dma_pte *pte) | |
669 | { | |
670 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
671 | } | |
672 | ||
e61d98d8 | 673 | extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); |
aa5d2b51 | 674 | extern int dmar_find_matched_atsr_unit(struct pci_dev *dev); |
e61d98d8 | 675 | |
2ae21010 | 676 | extern int dmar_enable_qi(struct intel_iommu *iommu); |
eba67e5d | 677 | extern void dmar_disable_qi(struct intel_iommu *iommu); |
f59c7b69 | 678 | extern int dmar_reenable_qi(struct intel_iommu *iommu); |
2ae21010 | 679 | extern void qi_global_iec(struct intel_iommu *iommu); |
e820482c | 680 | |
4c25a2c1 DW |
681 | extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, |
682 | u8 fm, u64 type); | |
1f0ef2aa DW |
683 | extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
684 | unsigned int size_order, u64 type); | |
1c48db44 JP |
685 | extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, |
686 | u16 qdep, u64 addr, unsigned mask); | |
61a06a16 | 687 | |
33cd6e64 LB |
688 | void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, |
689 | unsigned long npages, bool ih); | |
61a06a16 JP |
690 | |
691 | void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, | |
692 | u32 pasid, u16 qdep, u64 addr, | |
693 | unsigned int size_order, u64 granu); | |
694 | void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, | |
695 | int pasid); | |
696 | ||
704126ad | 697 | extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu); |
38717946 | 698 | |
074835f0 YS |
699 | extern int dmar_ir_support(void); |
700 | ||
9ddbfb42 LB |
701 | void *alloc_pgtable_page(int node); |
702 | void free_pgtable_page(void *vaddr); | |
703 | struct intel_iommu *domain_get_iommu(struct dmar_domain *domain); | |
85319dcc LB |
704 | int for_each_device_domain(int (*fn)(struct device_domain_info *info, |
705 | void *data), void *data); | |
6f7db75e | 706 | void iommu_flush_write_buffer(struct intel_iommu *iommu); |
d7cbc0f3 | 707 | int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev); |
e2726dae | 708 | struct dmar_domain *find_domain(struct device *dev); |
9ddbfb42 | 709 | |
2f26e0a9 | 710 | #ifdef CONFIG_INTEL_IOMMU_SVM |
ff3dc652 | 711 | extern void intel_svm_check(struct intel_iommu *iommu); |
a222a7f0 DW |
712 | extern int intel_svm_enable_prq(struct intel_iommu *iommu); |
713 | extern int intel_svm_finish_prq(struct intel_iommu *iommu); | |
56722a43 JP |
714 | int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev, |
715 | struct iommu_gpasid_bind_data *data); | |
716 | int intel_svm_unbind_gpasid(struct device *dev, int pasid); | |
0204a496 DW |
717 | struct svm_dev_ops; |
718 | ||
2f26e0a9 DW |
719 | struct intel_svm_dev { |
720 | struct list_head list; | |
721 | struct rcu_head rcu; | |
722 | struct device *dev; | |
0204a496 | 723 | struct svm_dev_ops *ops; |
2f26e0a9 DW |
724 | int users; |
725 | u16 did; | |
726 | u16 dev_iotlb:1; | |
727 | u16 sid, qdep; | |
728 | }; | |
729 | ||
730 | struct intel_svm { | |
731 | struct mmu_notifier notifier; | |
732 | struct mm_struct *mm; | |
56722a43 | 733 | |
2f26e0a9 | 734 | struct intel_iommu *iommu; |
569e4f77 | 735 | int flags; |
2f26e0a9 | 736 | int pasid; |
56722a43 | 737 | int gpasid; /* In case that guest PASID is different from host PASID */ |
2f26e0a9 | 738 | struct list_head devs; |
51261aac | 739 | struct list_head list; |
2f26e0a9 DW |
740 | }; |
741 | ||
2f26e0a9 | 742 | extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev); |
ff3dc652 JP |
743 | #else |
744 | static inline void intel_svm_check(struct intel_iommu *iommu) {} | |
2f26e0a9 DW |
745 | #endif |
746 | ||
ee2636b8 SM |
747 | #ifdef CONFIG_INTEL_IOMMU_DEBUGFS |
748 | void intel_iommu_debugfs_init(void); | |
749 | #else | |
750 | static inline void intel_iommu_debugfs_init(void) {} | |
751 | #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */ | |
752 | ||
a5459cfe | 753 | extern const struct attribute_group *intel_iommu_groups[]; |
26b86092 SM |
754 | bool context_present(struct context_entry *context); |
755 | struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, | |
756 | u8 devfn, int alloc); | |
a5459cfe | 757 | |
daedaa33 LB |
758 | #ifdef CONFIG_INTEL_IOMMU |
759 | extern int iommu_calculate_agaw(struct intel_iommu *iommu); | |
760 | extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu); | |
761 | extern int dmar_disabled; | |
762 | extern int intel_iommu_enabled; | |
763 | extern int intel_iommu_tboot_noforce; | |
764 | #else | |
765 | static inline int iommu_calculate_agaw(struct intel_iommu *iommu) | |
766 | { | |
767 | return 0; | |
768 | } | |
769 | static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
770 | { | |
771 | return 0; | |
772 | } | |
773 | #define dmar_disabled (1) | |
774 | #define intel_iommu_enabled (0) | |
775 | #endif | |
776 | ||
ba395927 | 777 | #endif |