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ba395927 | 1 | /* |
2f26e0a9 DW |
2 | * Copyright © 2006-2015, Intel Corporation. |
3 | * | |
4 | * Authors: Ashok Raj <ashok.raj@intel.com> | |
5 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
6 | * David Woodhouse <David.Woodhouse@intel.com> | |
ba395927 KA |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
19 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
ba395927 KA |
20 | */ |
21 | ||
22 | #ifndef _INTEL_IOMMU_H_ | |
23 | #define _INTEL_IOMMU_H_ | |
24 | ||
25 | #include <linux/types.h> | |
38717946 | 26 | #include <linux/iova.h> |
ba395927 | 27 | #include <linux/io.h> |
2f26e0a9 | 28 | #include <linux/idr.h> |
38717946 | 29 | #include <linux/dma_remapping.h> |
2f26e0a9 DW |
30 | #include <linux/mmu_notifier.h> |
31 | #include <linux/list.h> | |
b0119e87 | 32 | #include <linux/iommu.h> |
fe962e90 | 33 | #include <asm/cacheflush.h> |
5b6985ce | 34 | #include <asm/iommu.h> |
f661197e | 35 | |
ba395927 KA |
36 | /* |
37 | * Intel IOMMU register specification per version 1.0 public spec. | |
38 | */ | |
39 | ||
40 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ | |
41 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
42 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
43 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
44 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
45 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
46 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
47 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
48 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
49 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
50 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
51 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
52 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
53 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
54 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
55 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
56 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
57 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
58 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
59 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
6ba6c3a4 | 60 | #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ |
fe962e90 | 61 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ |
82aeef0b | 62 | #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ |
2ae21010 | 63 | #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ |
1208225c DW |
64 | #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ |
65 | #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ | |
66 | #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ | |
67 | #define DMAR_PRS_REG 0xdc /* Page request status register */ | |
68 | #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ | |
69 | #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ | |
70 | #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ | |
71 | #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ | |
ba395927 KA |
72 | |
73 | #define OFFSET_STRIDE (9) | |
50d3fb56 DW |
74 | |
75 | #ifdef CONFIG_64BIT | |
76 | #define dmar_readq(a) readq(a) | |
77 | #define dmar_writeq(a,v) writeq(v,a) | |
78 | #else | |
4fe05bbc | 79 | static inline u64 dmar_readq(void __iomem *addr) |
ba395927 KA |
80 | { |
81 | u32 lo, hi; | |
82 | lo = readl(addr); | |
83 | hi = readl(addr + 4); | |
84 | return (((u64) hi) << 32) + lo; | |
85 | } | |
86 | ||
87 | static inline void dmar_writeq(void __iomem *addr, u64 val) | |
88 | { | |
89 | writel((u32)val, addr); | |
90 | writel((u32)(val >> 32), addr + 4); | |
91 | } | |
50d3fb56 | 92 | #endif |
ba395927 KA |
93 | |
94 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
95 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
96 | ||
97 | /* | |
98 | * Decoding Capability Register | |
99 | */ | |
07c09787 | 100 | #define cap_pi_support(c) (((c) >> 59) & 1) |
ba395927 KA |
101 | #define cap_read_drain(c) (((c) >> 55) & 1) |
102 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
103 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
104 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
105 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
106 | ||
107 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
108 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
109 | * OFFSET_STRIDE) + 21) | |
110 | ||
111 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
112 | #define cap_max_fault_reg_offset(c) \ | |
113 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
114 | ||
115 | #define cap_zlr(c) (((c) >> 22) & 1) | |
116 | #define cap_isoch(c) (((c) >> 23) & 1) | |
117 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
118 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
119 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
120 | #define cap_phmr(c) (((c) >> 6) & 1) | |
121 | #define cap_plmr(c) (((c) >> 5) & 1) | |
122 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
123 | #define cap_afl(c) (((c) >> 3) & 1) | |
124 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
125 | /* | |
126 | * Extended Capability Register | |
127 | */ | |
128 | ||
bd00c606 | 129 | #define ecap_pasid(e) ((e >> 40) & 0x1) |
4423f5e7 DW |
130 | #define ecap_pss(e) ((e >> 35) & 0x1f) |
131 | #define ecap_eafs(e) ((e >> 34) & 0x1) | |
132 | #define ecap_nwfs(e) ((e >> 33) & 0x1) | |
133 | #define ecap_srs(e) ((e >> 31) & 0x1) | |
134 | #define ecap_ers(e) ((e >> 30) & 0x1) | |
135 | #define ecap_prs(e) ((e >> 29) & 0x1) | |
ae853ddb | 136 | #define ecap_broken_pasid(e) ((e >> 28) & 0x1) |
4423f5e7 DW |
137 | #define ecap_dis(e) ((e >> 27) & 0x1) |
138 | #define ecap_nest(e) ((e >> 26) & 0x1) | |
139 | #define ecap_mts(e) ((e >> 25) & 0x1) | |
140 | #define ecap_ecs(e) ((e >> 24) & 0x1) | |
ba395927 | 141 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) |
44caf2f3 | 142 | #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) |
ba395927 | 143 | #define ecap_coherent(e) ((e) & 0x1) |
fe962e90 | 144 | #define ecap_qis(e) ((e) & 0x2) |
4ed0d3e6 | 145 | #define ecap_pass_through(e) ((e >> 6) & 0x1) |
ad3ad3f6 SS |
146 | #define ecap_eim_support(e) ((e >> 4) & 0x1) |
147 | #define ecap_ir_support(e) ((e >> 3) & 0x1) | |
93a23a72 | 148 | #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) |
b6fcb33a | 149 | #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) |
58c610bd | 150 | #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ |
ba395927 KA |
151 | |
152 | /* IOTLB_REG */ | |
3481f210 | 153 | #define DMA_TLB_FLUSH_GRANU_OFFSET 60 |
ba395927 KA |
154 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
155 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
156 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
aaa59306 CT |
157 | #define DMA_TLB_IIRG(type) ((type >> 60) & 3) |
158 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) | |
ba395927 KA |
159 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) |
160 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
161 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
162 | #define DMA_TLB_IVT (((u64)1) << 63) | |
163 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
164 | #define DMA_TLB_MAX_SIZE (0x3f) | |
165 | ||
fe962e90 | 166 | /* INVALID_DESC */ |
3481f210 | 167 | #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
aaa59306 CT |
168 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) |
169 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) | |
170 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) | |
fe962e90 SS |
171 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) |
172 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
173 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
174 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
175 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
176 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
177 | ||
f8bab735 | 178 | /* PMEN_REG */ |
179 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
180 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
181 | ||
ba395927 KA |
182 | /* GCMD_REG */ |
183 | #define DMA_GCMD_TE (((u32)1) << 31) | |
184 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
185 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
186 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
187 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
2ae21010 SS |
188 | #define DMA_GCMD_QIE (((u32)1) << 26) |
189 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | |
190 | #define DMA_GCMD_IRE (((u32) 1) << 25) | |
161fde08 | 191 | #define DMA_GCMD_CFI (((u32) 1) << 23) |
ba395927 KA |
192 | |
193 | /* GSTS_REG */ | |
194 | #define DMA_GSTS_TES (((u32)1) << 31) | |
195 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
196 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
197 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
198 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
2ae21010 SS |
199 | #define DMA_GSTS_QIES (((u32)1) << 26) |
200 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | |
201 | #define DMA_GSTS_IRES (((u32)1) << 25) | |
161fde08 | 202 | #define DMA_GSTS_CFIS (((u32)1) << 23) |
ba395927 | 203 | |
4423f5e7 DW |
204 | /* DMA_RTADDR_REG */ |
205 | #define DMA_RTADDR_RTT (((u64)1) << 11) | |
206 | ||
ba395927 KA |
207 | /* CCMD_REG */ |
208 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
209 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
210 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
211 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
212 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
213 | #define DMA_CCMD_MASK_NOBIT 0 | |
214 | #define DMA_CCMD_MASK_1BIT 1 | |
215 | #define DMA_CCMD_MASK_2BIT 2 | |
216 | #define DMA_CCMD_MASK_3BIT 3 | |
217 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
218 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
219 | ||
220 | /* FECTL_REG */ | |
221 | #define DMA_FECTL_IM (((u32)1) << 31) | |
222 | ||
223 | /* FSTS_REG */ | |
224 | #define DMA_FSTS_PPF ((u32)2) | |
225 | #define DMA_FSTS_PFO ((u32)1) | |
704126ad | 226 | #define DMA_FSTS_IQE (1 << 4) |
6ba6c3a4 YZ |
227 | #define DMA_FSTS_ICE (1 << 5) |
228 | #define DMA_FSTS_ITE (1 << 6) | |
ba395927 KA |
229 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) |
230 | ||
231 | /* FRCD_REG, 32 bits access */ | |
232 | #define DMA_FRCD_F (((u32)1) << 31) | |
233 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
234 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
235 | #define dma_frcd_source_id(c) (c & 0xffff) | |
5b6985ce FY |
236 | /* low 64 bit */ |
237 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) | |
238 | ||
46924008 DW |
239 | /* PRS_REG */ |
240 | #define DMA_PRS_PPR ((u32)1) | |
241 | ||
5b6985ce FY |
242 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ |
243 | do { \ | |
244 | cycles_t start_time = get_cycles(); \ | |
245 | while (1) { \ | |
246 | sts = op(iommu->reg + offset); \ | |
247 | if (cond) \ | |
248 | break; \ | |
cf1337f0 | 249 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ |
5b6985ce FY |
250 | panic("DMAR hardware is malfunctioning\n"); \ |
251 | cpu_relax(); \ | |
252 | } \ | |
253 | } while (0) | |
cf1337f0 | 254 | |
fe962e90 SS |
255 | #define QI_LENGTH 256 /* queue length */ |
256 | ||
257 | enum { | |
258 | QI_FREE, | |
259 | QI_IN_USE, | |
6ba6c3a4 YZ |
260 | QI_DONE, |
261 | QI_ABORT | |
fe962e90 SS |
262 | }; |
263 | ||
264 | #define QI_CC_TYPE 0x1 | |
265 | #define QI_IOTLB_TYPE 0x2 | |
266 | #define QI_DIOTLB_TYPE 0x3 | |
267 | #define QI_IEC_TYPE 0x4 | |
268 | #define QI_IWD_TYPE 0x5 | |
2f26e0a9 DW |
269 | #define QI_EIOTLB_TYPE 0x6 |
270 | #define QI_PC_TYPE 0x7 | |
271 | #define QI_DEIOTLB_TYPE 0x8 | |
a222a7f0 DW |
272 | #define QI_PGRP_RESP_TYPE 0x9 |
273 | #define QI_PSTRM_RESP_TYPE 0xa | |
fe962e90 SS |
274 | |
275 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
276 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
277 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
278 | ||
279 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
280 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
281 | ||
3481f210 YS |
282 | #define QI_IOTLB_DID(did) (((u64)did) << 16) |
283 | #define QI_IOTLB_DR(dr) (((u64)dr) << 7) | |
284 | #define QI_IOTLB_DW(dw) (((u64)dw) << 6) | |
285 | #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) | |
5b6985ce | 286 | #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) |
3481f210 YS |
287 | #define QI_IOTLB_IH(ih) (((u64)ih) << 6) |
288 | #define QI_IOTLB_AM(am) (((u8)am)) | |
289 | ||
290 | #define QI_CC_FM(fm) (((u64)fm) << 48) | |
291 | #define QI_CC_SID(sid) (((u64)sid) << 32) | |
292 | #define QI_CC_DID(did) (((u64)did) << 16) | |
293 | #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) | |
294 | ||
6ba6c3a4 YZ |
295 | #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
296 | #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) | |
297 | #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
298 | #define QI_DEV_IOTLB_SIZE 1 | |
299 | #define QI_DEV_IOTLB_MAX_INVS 32 | |
300 | ||
2f26e0a9 DW |
301 | #define QI_PC_PASID(pasid) (((u64)pasid) << 32) |
302 | #define QI_PC_DID(did) (((u64)did) << 16) | |
303 | #define QI_PC_GRAN(gran) (((u64)gran) << 4) | |
304 | ||
305 | #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0)) | |
306 | #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1)) | |
307 | ||
308 | #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
309 | #define QI_EIOTLB_GL(gl) (((u64)gl) << 7) | |
310 | #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) | |
311 | #define QI_EIOTLB_AM(am) (((u64)am)) | |
312 | #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) | |
313 | #define QI_EIOTLB_DID(did) (((u64)did) << 16) | |
314 | #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) | |
315 | ||
316 | #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) | |
317 | #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) | |
318 | #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) | |
319 | #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) | |
aaa59306 CT |
320 | #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
321 | #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) | |
2f26e0a9 DW |
322 | #define QI_DEV_EIOTLB_MAX_INVS 32 |
323 | ||
a222a7f0 DW |
324 | #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55) |
325 | #define QI_PGRP_PRIV(priv) (((u64)(priv)) << 32) | |
326 | #define QI_PGRP_RESP_CODE(res) ((u64)(res)) | |
327 | #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) | |
328 | #define QI_PGRP_DID(did) (((u64)(did)) << 16) | |
329 | #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) | |
330 | ||
331 | #define QI_PSTRM_ADDR(addr) (((u64)(addr)) & VTD_PAGE_MASK) | |
332 | #define QI_PSTRM_DEVFN(devfn) (((u64)(devfn)) << 4) | |
333 | #define QI_PSTRM_RESP_CODE(res) ((u64)(res)) | |
334 | #define QI_PSTRM_IDX(idx) (((u64)(idx)) << 55) | |
335 | #define QI_PSTRM_PRIV(priv) (((u64)(priv)) << 32) | |
336 | #define QI_PSTRM_BUS(bus) (((u64)(bus)) << 24) | |
337 | #define QI_PSTRM_PASID(pasid) (((u64)(pasid)) << 4) | |
338 | ||
339 | #define QI_RESP_SUCCESS 0x0 | |
340 | #define QI_RESP_INVALID 0x1 | |
341 | #define QI_RESP_FAILURE 0xf | |
342 | ||
2f26e0a9 DW |
343 | #define QI_GRAN_ALL_ALL 0 |
344 | #define QI_GRAN_NONG_ALL 1 | |
345 | #define QI_GRAN_NONG_PASID 2 | |
346 | #define QI_GRAN_PSI_PASID 3 | |
347 | ||
fe962e90 SS |
348 | struct qi_desc { |
349 | u64 low, high; | |
350 | }; | |
351 | ||
352 | struct q_inval { | |
3b8f4048 | 353 | raw_spinlock_t q_lock; |
fe962e90 SS |
354 | struct qi_desc *desc; /* invalidation queue */ |
355 | int *desc_status; /* desc status */ | |
356 | int free_head; /* first free entry */ | |
357 | int free_tail; /* last free entry */ | |
358 | int free_cnt; | |
359 | }; | |
360 | ||
d3f13810 | 361 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
362 | /* 1MB - maximum possible interrupt remapping table size */ |
363 | #define INTR_REMAP_PAGE_ORDER 8 | |
364 | #define INTR_REMAP_TABLE_REG_SIZE 0xf | |
af3b358e | 365 | #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf |
2ae21010 | 366 | |
b6fcb33a SS |
367 | #define INTR_REMAP_TABLE_ENTRIES 65536 |
368 | ||
b106ee63 JL |
369 | struct irq_domain; |
370 | ||
2ae21010 SS |
371 | struct ir_table { |
372 | struct irte *base; | |
360eb3c5 | 373 | unsigned long *bitmap; |
2ae21010 SS |
374 | }; |
375 | #endif | |
376 | ||
a77b67d4 | 377 | struct iommu_flush { |
4c25a2c1 DW |
378 | void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, |
379 | u8 fm, u64 type); | |
1f0ef2aa DW |
380 | void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, |
381 | unsigned int size_order, u64 type); | |
a77b67d4 YS |
382 | }; |
383 | ||
f59c7b69 FY |
384 | enum { |
385 | SR_DMAR_FECTL_REG, | |
386 | SR_DMAR_FEDATA_REG, | |
387 | SR_DMAR_FEADDR_REG, | |
388 | SR_DMAR_FEUADDR_REG, | |
389 | MAX_SR_DMAR_REGS | |
390 | }; | |
391 | ||
4158c2ec JR |
392 | #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) |
393 | #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) | |
394 | ||
8a94ade4 DW |
395 | struct pasid_entry; |
396 | struct pasid_state_entry; | |
a222a7f0 | 397 | struct page_req_dsc; |
8a94ade4 | 398 | |
ba395927 KA |
399 | struct intel_iommu { |
400 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
6f5cf521 DD |
401 | u64 reg_phys; /* physical address of hw register set */ |
402 | u64 reg_size; /* size of hw register set */ | |
ba395927 KA |
403 | u64 cap; |
404 | u64 ecap; | |
ba395927 | 405 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ |
1f5b3c3f | 406 | raw_spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 407 | int seq_id; /* sequence id of the iommu */ |
1b573683 | 408 | int agaw; /* agaw of this iommu */ |
4ed0d3e6 | 409 | int msagaw; /* max sagaw of this iommu */ |
1208225c | 410 | unsigned int irq, pr_irq; |
67ccac41 | 411 | u16 segment; /* PCI segment# */ |
9d783ba0 | 412 | unsigned char name[13]; /* Device Name */ |
e61d98d8 | 413 | |
d3f13810 | 414 | #ifdef CONFIG_INTEL_IOMMU |
e61d98d8 | 415 | unsigned long *domain_ids; /* bitmap of domains */ |
8bf47816 | 416 | struct dmar_domain ***domains; /* ptr to domains */ |
e61d98d8 | 417 | spinlock_t lock; /* protect context, domain ids */ |
ba395927 KA |
418 | struct root_entry *root_entry; /* virtual address */ |
419 | ||
a77b67d4 | 420 | struct iommu_flush flush; |
8a94ade4 DW |
421 | #endif |
422 | #ifdef CONFIG_INTEL_IOMMU_SVM | |
423 | /* These are large and need to be contiguous, so we allocate just | |
424 | * one for now. We'll maybe want to rethink that if we truly give | |
425 | * devices away to userspace processes (e.g. for DPDK) and don't | |
426 | * want to trust that userspace will use *only* the PASID it was | |
427 | * told to. But while it's all driver-arbitrated, we're fine. */ | |
428 | struct pasid_entry *pasid_table; | |
429 | struct pasid_state_entry *pasid_state_table; | |
a222a7f0 DW |
430 | struct page_req_dsc *prq; |
431 | unsigned char prq_name[16]; /* Name for PRQ interrupt */ | |
2f26e0a9 | 432 | struct idr pasid_idr; |
91017044 | 433 | u32 pasid_max; |
e61d98d8 | 434 | #endif |
fe962e90 | 435 | struct q_inval *qi; /* Queued invalidation info */ |
f59c7b69 FY |
436 | u32 *iommu_state; /* Store iommu states between suspend and resume.*/ |
437 | ||
d3f13810 | 438 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 | 439 | struct ir_table *ir_table; /* Interrupt remapping info */ |
b106ee63 JL |
440 | struct irq_domain *ir_domain; |
441 | struct irq_domain *ir_msi_domain; | |
2ae21010 | 442 | #endif |
b0119e87 | 443 | struct iommu_device iommu; /* IOMMU core code handle */ |
ee34b32d | 444 | int node; |
4158c2ec | 445 | u32 flags; /* Software defined flags */ |
ba395927 KA |
446 | }; |
447 | ||
fe962e90 SS |
448 | static inline void __iommu_flush_cache( |
449 | struct intel_iommu *iommu, void *addr, int size) | |
450 | { | |
451 | if (!ecap_coherent(iommu->ecap)) | |
452 | clflush_cache_range(addr, size); | |
453 | } | |
454 | ||
e61d98d8 | 455 | extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); |
aa5d2b51 | 456 | extern int dmar_find_matched_atsr_unit(struct pci_dev *dev); |
e61d98d8 | 457 | |
2ae21010 | 458 | extern int dmar_enable_qi(struct intel_iommu *iommu); |
eba67e5d | 459 | extern void dmar_disable_qi(struct intel_iommu *iommu); |
f59c7b69 | 460 | extern int dmar_reenable_qi(struct intel_iommu *iommu); |
2ae21010 | 461 | extern void qi_global_iec(struct intel_iommu *iommu); |
e820482c | 462 | |
4c25a2c1 DW |
463 | extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, |
464 | u8 fm, u64 type); | |
1f0ef2aa DW |
465 | extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
466 | unsigned int size_order, u64 type); | |
6ba6c3a4 YZ |
467 | extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep, |
468 | u64 addr, unsigned mask); | |
3481f210 | 469 | |
704126ad | 470 | extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu); |
38717946 | 471 | |
074835f0 YS |
472 | extern int dmar_ir_support(void); |
473 | ||
2f26e0a9 | 474 | #ifdef CONFIG_INTEL_IOMMU_SVM |
8a94ade4 DW |
475 | extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu); |
476 | extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu); | |
a222a7f0 DW |
477 | extern int intel_svm_enable_prq(struct intel_iommu *iommu); |
478 | extern int intel_svm_finish_prq(struct intel_iommu *iommu); | |
8a94ade4 | 479 | |
0204a496 DW |
480 | struct svm_dev_ops; |
481 | ||
2f26e0a9 DW |
482 | struct intel_svm_dev { |
483 | struct list_head list; | |
484 | struct rcu_head rcu; | |
485 | struct device *dev; | |
0204a496 | 486 | struct svm_dev_ops *ops; |
2f26e0a9 DW |
487 | int users; |
488 | u16 did; | |
489 | u16 dev_iotlb:1; | |
490 | u16 sid, qdep; | |
491 | }; | |
492 | ||
493 | struct intel_svm { | |
494 | struct mmu_notifier notifier; | |
495 | struct mm_struct *mm; | |
496 | struct intel_iommu *iommu; | |
569e4f77 | 497 | int flags; |
2f26e0a9 DW |
498 | int pasid; |
499 | struct list_head devs; | |
500 | }; | |
501 | ||
502 | extern int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdev); | |
503 | extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev); | |
504 | #endif | |
505 | ||
a5459cfe AW |
506 | extern const struct attribute_group *intel_iommu_groups[]; |
507 | ||
ba395927 | 508 | #endif |