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3b20eb23 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
ba395927 | 2 | /* |
2f26e0a9 DW |
3 | * Copyright © 2006-2015, Intel Corporation. |
4 | * | |
5 | * Authors: Ashok Raj <ashok.raj@intel.com> | |
6 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
7 | * David Woodhouse <David.Woodhouse@intel.com> | |
ba395927 KA |
8 | */ |
9 | ||
10 | #ifndef _INTEL_IOMMU_H_ | |
11 | #define _INTEL_IOMMU_H_ | |
12 | ||
13 | #include <linux/types.h> | |
38717946 | 14 | #include <linux/iova.h> |
ba395927 | 15 | #include <linux/io.h> |
2f26e0a9 | 16 | #include <linux/idr.h> |
2f26e0a9 DW |
17 | #include <linux/mmu_notifier.h> |
18 | #include <linux/list.h> | |
b0119e87 | 19 | #include <linux/iommu.h> |
61012985 | 20 | #include <linux/io-64-nonatomic-lo-hi.h> |
9ddbfb42 | 21 | #include <linux/dmar.h> |
3375303e | 22 | #include <linux/ioasid.h> |
61012985 | 23 | |
fe962e90 | 24 | #include <asm/cacheflush.h> |
5b6985ce | 25 | #include <asm/iommu.h> |
f661197e | 26 | |
ba395927 | 27 | /* |
daedaa33 | 28 | * VT-d hardware uses 4KiB page size regardless of host page size. |
ba395927 | 29 | */ |
daedaa33 LB |
30 | #define VTD_PAGE_SHIFT (12) |
31 | #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT) | |
32 | #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT) | |
33 | #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK) | |
34 | ||
35 | #define VTD_STRIDE_SHIFT (9) | |
36 | #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT) | |
37 | ||
ddf09b6d LB |
38 | #define DMA_PTE_READ BIT_ULL(0) |
39 | #define DMA_PTE_WRITE BIT_ULL(1) | |
40 | #define DMA_PTE_LARGE_PAGE BIT_ULL(7) | |
41 | #define DMA_PTE_SNP BIT_ULL(11) | |
42 | ||
43 | #define DMA_FL_PTE_PRESENT BIT_ULL(0) | |
16ecf10e | 44 | #define DMA_FL_PTE_US BIT_ULL(2) |
ddf09b6d | 45 | #define DMA_FL_PTE_XD BIT_ULL(63) |
daedaa33 | 46 | |
b0d1f874 JP |
47 | #define ADDR_WIDTH_5LEVEL (57) |
48 | #define ADDR_WIDTH_4LEVEL (48) | |
49 | ||
daedaa33 LB |
50 | #define CONTEXT_TT_MULTI_LEVEL 0 |
51 | #define CONTEXT_TT_DEV_IOTLB 1 | |
52 | #define CONTEXT_TT_PASS_THROUGH 2 | |
1c4f88b7 | 53 | #define CONTEXT_PASIDE BIT_ULL(3) |
ba395927 | 54 | |
daedaa33 LB |
55 | /* |
56 | * Intel IOMMU register specification per version 1.0 public spec. | |
57 | */ | |
ba395927 KA |
58 | #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */ |
59 | #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */ | |
60 | #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */ | |
61 | #define DMAR_GCMD_REG 0x18 /* Global command register */ | |
62 | #define DMAR_GSTS_REG 0x1c /* Global status register */ | |
63 | #define DMAR_RTADDR_REG 0x20 /* Root entry table */ | |
64 | #define DMAR_CCMD_REG 0x28 /* Context command reg */ | |
65 | #define DMAR_FSTS_REG 0x34 /* Fault Status register */ | |
66 | #define DMAR_FECTL_REG 0x38 /* Fault control register */ | |
67 | #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */ | |
68 | #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */ | |
69 | #define DMAR_FEUADDR_REG 0x44 /* Upper address register */ | |
70 | #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */ | |
71 | #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */ | |
72 | #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */ | |
73 | #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */ | |
74 | #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */ | |
75 | #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */ | |
fe962e90 SS |
76 | #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */ |
77 | #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */ | |
6ba6c3a4 | 78 | #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */ |
fe962e90 | 79 | #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */ |
82aeef0b | 80 | #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */ |
2ae21010 | 81 | #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */ |
1208225c DW |
82 | #define DMAR_PQH_REG 0xc0 /* Page request queue head register */ |
83 | #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */ | |
84 | #define DMAR_PQA_REG 0xd0 /* Page request queue address register */ | |
85 | #define DMAR_PRS_REG 0xdc /* Page request status register */ | |
86 | #define DMAR_PECTL_REG 0xe0 /* Page request event control register */ | |
87 | #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */ | |
88 | #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */ | |
89 | #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */ | |
4a2d80db SM |
90 | #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */ |
91 | #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */ | |
92 | #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */ | |
93 | #define DMAR_MTRR_FIX16K_80000_REG 0x128 | |
94 | #define DMAR_MTRR_FIX16K_A0000_REG 0x130 | |
95 | #define DMAR_MTRR_FIX4K_C0000_REG 0x138 | |
96 | #define DMAR_MTRR_FIX4K_C8000_REG 0x140 | |
97 | #define DMAR_MTRR_FIX4K_D0000_REG 0x148 | |
98 | #define DMAR_MTRR_FIX4K_D8000_REG 0x150 | |
99 | #define DMAR_MTRR_FIX4K_E0000_REG 0x158 | |
100 | #define DMAR_MTRR_FIX4K_E8000_REG 0x160 | |
101 | #define DMAR_MTRR_FIX4K_F0000_REG 0x168 | |
102 | #define DMAR_MTRR_FIX4K_F8000_REG 0x170 | |
103 | #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */ | |
104 | #define DMAR_MTRR_PHYSMASK0_REG 0x188 | |
105 | #define DMAR_MTRR_PHYSBASE1_REG 0x190 | |
106 | #define DMAR_MTRR_PHYSMASK1_REG 0x198 | |
107 | #define DMAR_MTRR_PHYSBASE2_REG 0x1a0 | |
108 | #define DMAR_MTRR_PHYSMASK2_REG 0x1a8 | |
109 | #define DMAR_MTRR_PHYSBASE3_REG 0x1b0 | |
110 | #define DMAR_MTRR_PHYSMASK3_REG 0x1b8 | |
111 | #define DMAR_MTRR_PHYSBASE4_REG 0x1c0 | |
112 | #define DMAR_MTRR_PHYSMASK4_REG 0x1c8 | |
113 | #define DMAR_MTRR_PHYSBASE5_REG 0x1d0 | |
114 | #define DMAR_MTRR_PHYSMASK5_REG 0x1d8 | |
115 | #define DMAR_MTRR_PHYSBASE6_REG 0x1e0 | |
116 | #define DMAR_MTRR_PHYSMASK6_REG 0x1e8 | |
117 | #define DMAR_MTRR_PHYSBASE7_REG 0x1f0 | |
118 | #define DMAR_MTRR_PHYSMASK7_REG 0x1f8 | |
119 | #define DMAR_MTRR_PHYSBASE8_REG 0x200 | |
120 | #define DMAR_MTRR_PHYSMASK8_REG 0x208 | |
121 | #define DMAR_MTRR_PHYSBASE9_REG 0x210 | |
122 | #define DMAR_MTRR_PHYSMASK9_REG 0x218 | |
123 | #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */ | |
124 | #define DMAR_VCMD_REG 0xe10 /* Virtual command register */ | |
125 | #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */ | |
ba395927 KA |
126 | |
127 | #define OFFSET_STRIDE (9) | |
50d3fb56 | 128 | |
50d3fb56 DW |
129 | #define dmar_readq(a) readq(a) |
130 | #define dmar_writeq(a,v) writeq(v,a) | |
ba3b01d7 MD |
131 | #define dmar_readl(a) readl(a) |
132 | #define dmar_writel(a, v) writel(v, a) | |
ba395927 KA |
133 | |
134 | #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4) | |
135 | #define DMAR_VER_MINOR(v) ((v) & 0x0f) | |
136 | ||
137 | /* | |
138 | * Decoding Capability Register | |
139 | */ | |
f1ac10c2 | 140 | #define cap_5lp_support(c) (((c) >> 60) & 1) |
07c09787 | 141 | #define cap_pi_support(c) (((c) >> 59) & 1) |
59103caa | 142 | #define cap_fl1gp_support(c) (((c) >> 56) & 1) |
ba395927 KA |
143 | #define cap_read_drain(c) (((c) >> 55) & 1) |
144 | #define cap_write_drain(c) (((c) >> 54) & 1) | |
145 | #define cap_max_amask_val(c) (((c) >> 48) & 0x3f) | |
146 | #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1) | |
147 | #define cap_pgsel_inv(c) (((c) >> 39) & 1) | |
148 | ||
149 | #define cap_super_page_val(c) (((c) >> 34) & 0xf) | |
150 | #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \ | |
151 | * OFFSET_STRIDE) + 21) | |
152 | ||
153 | #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16) | |
154 | #define cap_max_fault_reg_offset(c) \ | |
155 | (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16) | |
156 | ||
157 | #define cap_zlr(c) (((c) >> 22) & 1) | |
158 | #define cap_isoch(c) (((c) >> 23) & 1) | |
159 | #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1) | |
160 | #define cap_sagaw(c) (((c) >> 8) & 0x1f) | |
161 | #define cap_caching_mode(c) (((c) >> 7) & 1) | |
162 | #define cap_phmr(c) (((c) >> 6) & 1) | |
163 | #define cap_plmr(c) (((c) >> 5) & 1) | |
164 | #define cap_rwbf(c) (((c) >> 4) & 1) | |
165 | #define cap_afl(c) (((c) >> 3) & 1) | |
166 | #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7))) | |
167 | /* | |
168 | * Extended Capability Register | |
169 | */ | |
170 | ||
6f7db75e | 171 | #define ecap_smpwc(e) (((e) >> 48) & 0x1) |
437f35e1 | 172 | #define ecap_flts(e) (((e) >> 47) & 0x1) |
6f7db75e | 173 | #define ecap_slts(e) (((e) >> 46) & 0x1) |
24f27d32 | 174 | #define ecap_vcs(e) (((e) >> 44) & 0x1) |
765b6a98 | 175 | #define ecap_smts(e) (((e) >> 43) & 0x1) |
0f725561 | 176 | #define ecap_dit(e) ((e >> 41) & 0x1) |
bd00c606 | 177 | #define ecap_pasid(e) ((e >> 40) & 0x1) |
4423f5e7 DW |
178 | #define ecap_pss(e) ((e >> 35) & 0x1f) |
179 | #define ecap_eafs(e) ((e >> 34) & 0x1) | |
180 | #define ecap_nwfs(e) ((e >> 33) & 0x1) | |
181 | #define ecap_srs(e) ((e >> 31) & 0x1) | |
182 | #define ecap_ers(e) ((e >> 30) & 0x1) | |
183 | #define ecap_prs(e) ((e >> 29) & 0x1) | |
2db1581e | 184 | #define ecap_broken_pasid(e) ((e >> 28) & 0x1) |
4423f5e7 DW |
185 | #define ecap_dis(e) ((e >> 27) & 0x1) |
186 | #define ecap_nest(e) ((e >> 26) & 0x1) | |
187 | #define ecap_mts(e) ((e >> 25) & 0x1) | |
188 | #define ecap_ecs(e) ((e >> 24) & 0x1) | |
ba395927 | 189 | #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16) |
44caf2f3 | 190 | #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16) |
ba395927 | 191 | #define ecap_coherent(e) ((e) & 0x1) |
fe962e90 | 192 | #define ecap_qis(e) ((e) & 0x2) |
4ed0d3e6 | 193 | #define ecap_pass_through(e) ((e >> 6) & 0x1) |
ad3ad3f6 SS |
194 | #define ecap_eim_support(e) ((e >> 4) & 0x1) |
195 | #define ecap_ir_support(e) ((e >> 3) & 0x1) | |
93a23a72 | 196 | #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1) |
b6fcb33a | 197 | #define ecap_max_handle_mask(e) ((e >> 20) & 0xf) |
58c610bd | 198 | #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */ |
ba395927 | 199 | |
3375303e JP |
200 | /* Virtual command interface capability */ |
201 | #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */ | |
202 | ||
ba395927 | 203 | /* IOTLB_REG */ |
3481f210 | 204 | #define DMA_TLB_FLUSH_GRANU_OFFSET 60 |
ba395927 KA |
205 | #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
206 | #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) | |
207 | #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) | |
aaa59306 CT |
208 | #define DMA_TLB_IIRG(type) ((type >> 60) & 3) |
209 | #define DMA_TLB_IAIG(val) (((val) >> 57) & 3) | |
ba395927 KA |
210 | #define DMA_TLB_READ_DRAIN (((u64)1) << 49) |
211 | #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) | |
212 | #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) | |
213 | #define DMA_TLB_IVT (((u64)1) << 63) | |
214 | #define DMA_TLB_IH_NONLEAF (((u64)1) << 6) | |
215 | #define DMA_TLB_MAX_SIZE (0x3f) | |
216 | ||
fe962e90 | 217 | /* INVALID_DESC */ |
3481f210 | 218 | #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
aaa59306 CT |
219 | #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) |
220 | #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) | |
221 | #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) | |
fe962e90 SS |
222 | #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) |
223 | #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) | |
224 | #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) | |
225 | #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6) | |
226 | #define DMA_ID_TLB_ADDR(addr) (addr) | |
227 | #define DMA_ID_TLB_ADDR_MASK(mask) (mask) | |
228 | ||
f8bab735 | 229 | /* PMEN_REG */ |
230 | #define DMA_PMEN_EPM (((u32)1)<<31) | |
231 | #define DMA_PMEN_PRS (((u32)1)<<0) | |
232 | ||
ba395927 KA |
233 | /* GCMD_REG */ |
234 | #define DMA_GCMD_TE (((u32)1) << 31) | |
235 | #define DMA_GCMD_SRTP (((u32)1) << 30) | |
236 | #define DMA_GCMD_SFL (((u32)1) << 29) | |
237 | #define DMA_GCMD_EAFL (((u32)1) << 28) | |
238 | #define DMA_GCMD_WBF (((u32)1) << 27) | |
2ae21010 SS |
239 | #define DMA_GCMD_QIE (((u32)1) << 26) |
240 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | |
241 | #define DMA_GCMD_IRE (((u32) 1) << 25) | |
161fde08 | 242 | #define DMA_GCMD_CFI (((u32) 1) << 23) |
ba395927 KA |
243 | |
244 | /* GSTS_REG */ | |
245 | #define DMA_GSTS_TES (((u32)1) << 31) | |
246 | #define DMA_GSTS_RTPS (((u32)1) << 30) | |
247 | #define DMA_GSTS_FLS (((u32)1) << 29) | |
248 | #define DMA_GSTS_AFLS (((u32)1) << 28) | |
249 | #define DMA_GSTS_WBFS (((u32)1) << 27) | |
2ae21010 SS |
250 | #define DMA_GSTS_QIES (((u32)1) << 26) |
251 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | |
252 | #define DMA_GSTS_IRES (((u32)1) << 25) | |
161fde08 | 253 | #define DMA_GSTS_CFIS (((u32)1) << 23) |
ba395927 | 254 | |
4423f5e7 DW |
255 | /* DMA_RTADDR_REG */ |
256 | #define DMA_RTADDR_RTT (((u64)1) << 11) | |
7373a8cc | 257 | #define DMA_RTADDR_SMT (((u64)1) << 10) |
4423f5e7 | 258 | |
ba395927 KA |
259 | /* CCMD_REG */ |
260 | #define DMA_CCMD_ICC (((u64)1) << 63) | |
261 | #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61) | |
262 | #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61) | |
263 | #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61) | |
264 | #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32) | |
265 | #define DMA_CCMD_MASK_NOBIT 0 | |
266 | #define DMA_CCMD_MASK_1BIT 1 | |
267 | #define DMA_CCMD_MASK_2BIT 2 | |
268 | #define DMA_CCMD_MASK_3BIT 3 | |
269 | #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16) | |
270 | #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff)) | |
271 | ||
272 | /* FECTL_REG */ | |
273 | #define DMA_FECTL_IM (((u32)1) << 31) | |
274 | ||
275 | /* FSTS_REG */ | |
b1d03c1d DS |
276 | #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */ |
277 | #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */ | |
278 | #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */ | |
279 | #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */ | |
280 | #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */ | |
281 | #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */ | |
ba395927 KA |
282 | #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff) |
283 | ||
284 | /* FRCD_REG, 32 bits access */ | |
285 | #define DMA_FRCD_F (((u32)1) << 31) | |
286 | #define dma_frcd_type(d) ((d >> 30) & 1) | |
287 | #define dma_frcd_fault_reason(c) (c & 0xff) | |
288 | #define dma_frcd_source_id(c) (c & 0xffff) | |
fd730007 KMP |
289 | #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff) |
290 | #define dma_frcd_pasid_present(c) (((c) >> 31) & 1) | |
5b6985ce FY |
291 | /* low 64 bit */ |
292 | #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT)) | |
293 | ||
46924008 DW |
294 | /* PRS_REG */ |
295 | #define DMA_PRS_PPR ((u32)1) | |
66ac4db3 LB |
296 | #define DMA_PRS_PRO ((u32)2) |
297 | ||
3375303e | 298 | #define DMA_VCS_PAS ((u64)1) |
46924008 | 299 | |
5b6985ce FY |
300 | #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \ |
301 | do { \ | |
302 | cycles_t start_time = get_cycles(); \ | |
303 | while (1) { \ | |
304 | sts = op(iommu->reg + offset); \ | |
305 | if (cond) \ | |
306 | break; \ | |
cf1337f0 | 307 | if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\ |
5b6985ce FY |
308 | panic("DMAR hardware is malfunctioning\n"); \ |
309 | cpu_relax(); \ | |
310 | } \ | |
311 | } while (0) | |
cf1337f0 | 312 | |
fe962e90 SS |
313 | #define QI_LENGTH 256 /* queue length */ |
314 | ||
315 | enum { | |
316 | QI_FREE, | |
317 | QI_IN_USE, | |
6ba6c3a4 YZ |
318 | QI_DONE, |
319 | QI_ABORT | |
fe962e90 SS |
320 | }; |
321 | ||
322 | #define QI_CC_TYPE 0x1 | |
323 | #define QI_IOTLB_TYPE 0x2 | |
324 | #define QI_DIOTLB_TYPE 0x3 | |
325 | #define QI_IEC_TYPE 0x4 | |
326 | #define QI_IWD_TYPE 0x5 | |
2f26e0a9 DW |
327 | #define QI_EIOTLB_TYPE 0x6 |
328 | #define QI_PC_TYPE 0x7 | |
329 | #define QI_DEIOTLB_TYPE 0x8 | |
a222a7f0 DW |
330 | #define QI_PGRP_RESP_TYPE 0x9 |
331 | #define QI_PSTRM_RESP_TYPE 0xa | |
fe962e90 SS |
332 | |
333 | #define QI_IEC_SELECTIVE (((u64)1) << 4) | |
334 | #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32)) | |
335 | #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27)) | |
336 | ||
337 | #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32) | |
338 | #define QI_IWD_STATUS_WRITE (((u64)1) << 5) | |
66ac4db3 | 339 | #define QI_IWD_FENCE (((u64)1) << 6) |
8a1d8246 | 340 | #define QI_IWD_PRQ_DRAIN (((u64)1) << 7) |
fe962e90 | 341 | |
3481f210 YS |
342 | #define QI_IOTLB_DID(did) (((u64)did) << 16) |
343 | #define QI_IOTLB_DR(dr) (((u64)dr) << 7) | |
344 | #define QI_IOTLB_DW(dw) (((u64)dw) << 6) | |
345 | #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4)) | |
5b6985ce | 346 | #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK) |
3481f210 | 347 | #define QI_IOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 348 | #define QI_IOTLB_AM(am) (((u8)am) & 0x3f) |
3481f210 YS |
349 | |
350 | #define QI_CC_FM(fm) (((u64)fm) << 48) | |
351 | #define QI_CC_SID(sid) (((u64)sid) << 32) | |
352 | #define QI_CC_DID(did) (((u64)did) << 16) | |
353 | #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4)) | |
354 | ||
6ba6c3a4 YZ |
355 | #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
356 | #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16) | |
357 | #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
4e7120d7 EA |
358 | #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
359 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
6ba6c3a4 YZ |
360 | #define QI_DEV_IOTLB_SIZE 1 |
361 | #define QI_DEV_IOTLB_MAX_INVS 32 | |
362 | ||
2f26e0a9 DW |
363 | #define QI_PC_PASID(pasid) (((u64)pasid) << 32) |
364 | #define QI_PC_DID(did) (((u64)did) << 16) | |
365 | #define QI_PC_GRAN(gran) (((u64)gran) << 4) | |
366 | ||
61a06a16 JP |
367 | /* PASID cache invalidation granu */ |
368 | #define QI_PC_ALL_PASIDS 0 | |
369 | #define QI_PC_PASID_SEL 1 | |
2f26e0a9 DW |
370 | |
371 | #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK) | |
2f26e0a9 | 372 | #define QI_EIOTLB_IH(ih) (((u64)ih) << 6) |
61a06a16 | 373 | #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f) |
2f26e0a9 DW |
374 | #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32) |
375 | #define QI_EIOTLB_DID(did) (((u64)did) << 16) | |
376 | #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4) | |
377 | ||
61a06a16 JP |
378 | /* QI Dev-IOTLB inv granu */ |
379 | #define QI_DEV_IOTLB_GRAN_ALL 1 | |
380 | #define QI_DEV_IOTLB_GRAN_PASID_SEL 0 | |
381 | ||
2f26e0a9 DW |
382 | #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) |
383 | #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) | |
5f77d6ca | 384 | #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) |
aaa59306 CT |
385 | #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
386 | #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) | |
4e7120d7 EA |
387 | #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ |
388 | ((u64)((pfsid >> 4) & 0xfff) << 52)) | |
2f26e0a9 DW |
389 | #define QI_DEV_EIOTLB_MAX_INVS 32 |
390 | ||
5b438f4b | 391 | /* Page group response descriptor QW0 */ |
a222a7f0 | 392 | #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4) |
5b438f4b JP |
393 | #define QI_PGRP_PDP(p) (((u64)(p)) << 5) |
394 | #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12) | |
395 | #define QI_PGRP_DID(rid) (((u64)(rid)) << 16) | |
396 | #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32) | |
397 | ||
398 | /* Page group response descriptor QW1 */ | |
399 | #define QI_PGRP_LPIG(x) (((u64)(x)) << 2) | |
400 | #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3) | |
a222a7f0 | 401 | |
a222a7f0 DW |
402 | |
403 | #define QI_RESP_SUCCESS 0x0 | |
404 | #define QI_RESP_INVALID 0x1 | |
405 | #define QI_RESP_FAILURE 0xf | |
406 | ||
2f26e0a9 DW |
407 | #define QI_GRAN_NONG_PASID 2 |
408 | #define QI_GRAN_PSI_PASID 3 | |
409 | ||
5d308fc1 LB |
410 | #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap)) |
411 | ||
fe962e90 | 412 | struct qi_desc { |
5d308fc1 LB |
413 | u64 qw0; |
414 | u64 qw1; | |
415 | u64 qw2; | |
416 | u64 qw3; | |
fe962e90 SS |
417 | }; |
418 | ||
419 | struct q_inval { | |
3b8f4048 | 420 | raw_spinlock_t q_lock; |
5d308fc1 | 421 | void *desc; /* invalidation queue */ |
fe962e90 SS |
422 | int *desc_status; /* desc status */ |
423 | int free_head; /* first free entry */ | |
424 | int free_tail; /* last free entry */ | |
425 | int free_cnt; | |
426 | }; | |
427 | ||
d3f13810 | 428 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 SS |
429 | /* 1MB - maximum possible interrupt remapping table size */ |
430 | #define INTR_REMAP_PAGE_ORDER 8 | |
431 | #define INTR_REMAP_TABLE_REG_SIZE 0xf | |
af3b358e | 432 | #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf |
2ae21010 | 433 | |
b6fcb33a SS |
434 | #define INTR_REMAP_TABLE_ENTRIES 65536 |
435 | ||
b106ee63 JL |
436 | struct irq_domain; |
437 | ||
2ae21010 SS |
438 | struct ir_table { |
439 | struct irte *base; | |
360eb3c5 | 440 | unsigned long *bitmap; |
2ae21010 SS |
441 | }; |
442 | #endif | |
443 | ||
a77b67d4 | 444 | struct iommu_flush { |
4c25a2c1 DW |
445 | void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid, |
446 | u8 fm, u64 type); | |
1f0ef2aa DW |
447 | void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr, |
448 | unsigned int size_order, u64 type); | |
a77b67d4 YS |
449 | }; |
450 | ||
f59c7b69 FY |
451 | enum { |
452 | SR_DMAR_FECTL_REG, | |
453 | SR_DMAR_FEDATA_REG, | |
454 | SR_DMAR_FEADDR_REG, | |
455 | SR_DMAR_FEUADDR_REG, | |
456 | MAX_SR_DMAR_REGS | |
457 | }; | |
458 | ||
4158c2ec JR |
459 | #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0) |
460 | #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1) | |
ff3dc652 | 461 | #define VTD_FLAG_SVM_CAPABLE (1 << 2) |
4158c2ec | 462 | |
cdd3a249 | 463 | extern int intel_iommu_sm; |
e2726dae | 464 | extern spinlock_t device_domain_lock; |
cdd3a249 SPP |
465 | |
466 | #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap)) | |
467 | #define pasid_supported(iommu) (sm_supported(iommu) && \ | |
468 | ecap_pasid((iommu)->ecap)) | |
469 | ||
8a94ade4 DW |
470 | struct pasid_entry; |
471 | struct pasid_state_entry; | |
a222a7f0 | 472 | struct page_req_dsc; |
8a94ade4 | 473 | |
26b86092 SM |
474 | /* |
475 | * 0: Present | |
476 | * 1-11: Reserved | |
477 | * 12-63: Context Ptr (12 - (haw-1)) | |
478 | * 64-127: Reserved | |
479 | */ | |
480 | struct root_entry { | |
481 | u64 lo; | |
482 | u64 hi; | |
483 | }; | |
484 | ||
485 | /* | |
486 | * low 64 bits: | |
487 | * 0: present | |
488 | * 1: fault processing disable | |
489 | * 2-3: translation type | |
490 | * 12-63: address space root | |
491 | * high 64 bits: | |
492 | * 0-2: address width | |
493 | * 3-6: aval | |
494 | * 8-23: domain id | |
495 | */ | |
496 | struct context_entry { | |
497 | u64 lo; | |
498 | u64 hi; | |
499 | }; | |
500 | ||
b0d1f874 JP |
501 | /* si_domain contains mulitple devices */ |
502 | #define DOMAIN_FLAG_STATIC_IDENTITY BIT(0) | |
503 | ||
504 | /* | |
505 | * When VT-d works in the scalable mode, it allows DMA translation to | |
506 | * happen through either first level or second level page table. This | |
507 | * bit marks that the DMA translation for the domain goes through the | |
508 | * first level page table, otherwise, it goes through the second level. | |
509 | */ | |
510 | #define DOMAIN_FLAG_USE_FIRST_LEVEL BIT(1) | |
511 | ||
512 | /* | |
513 | * Domain represents a virtual machine which demands iommu nested | |
514 | * translation mode support. | |
515 | */ | |
516 | #define DOMAIN_FLAG_NESTING_MODE BIT(2) | |
517 | ||
9ddbfb42 LB |
518 | struct dmar_domain { |
519 | int nid; /* node id */ | |
520 | ||
521 | unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED]; | |
522 | /* Refcount of devices per iommu */ | |
523 | ||
524 | ||
525 | u16 iommu_did[DMAR_UNITS_SUPPORTED]; | |
526 | /* Domain ids per IOMMU. Use u16 since | |
527 | * domain ids are 16 bit wide according | |
528 | * to VT-d spec, section 9.3 */ | |
67b8e02b | 529 | unsigned int auxd_refcnt; /* Refcount of auxiliary attaching */ |
9ddbfb42 LB |
530 | |
531 | bool has_iotlb_device; | |
532 | struct list_head devices; /* all devices' list */ | |
67b8e02b | 533 | struct list_head auxd; /* link to device's auxiliary list */ |
9ddbfb42 LB |
534 | struct iova_domain iovad; /* iova's that belong to this domain */ |
535 | ||
536 | struct dma_pte *pgd; /* virtual address */ | |
537 | int gaw; /* max guest address width */ | |
538 | ||
539 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
540 | int agaw; | |
541 | ||
542 | int flags; /* flags to find out type of domain */ | |
543 | ||
544 | int iommu_coherency;/* indicate coherency of iommu access */ | |
545 | int iommu_snooping; /* indicate snooping control feature*/ | |
546 | int iommu_count; /* reference count of iommu */ | |
547 | int iommu_superpage;/* Level of superpages supported: | |
548 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
549 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
550 | u64 max_addr; /* maximum mapped address */ | |
551 | ||
67b8e02b LB |
552 | int default_pasid; /* |
553 | * The default pasid used for non-SVM | |
554 | * traffic on mediated devices. | |
555 | */ | |
556 | ||
9ddbfb42 LB |
557 | struct iommu_domain domain; /* generic domain data structure for |
558 | iommu core */ | |
559 | }; | |
560 | ||
ba395927 KA |
561 | struct intel_iommu { |
562 | void __iomem *reg; /* Pointer to hardware regs, virtual addr */ | |
6f5cf521 DD |
563 | u64 reg_phys; /* physical address of hw register set */ |
564 | u64 reg_size; /* size of hw register set */ | |
ba395927 KA |
565 | u64 cap; |
566 | u64 ecap; | |
3375303e | 567 | u64 vccap; |
ba395927 | 568 | u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */ |
1f5b3c3f | 569 | raw_spinlock_t register_lock; /* protect register handling */ |
c42d9f32 | 570 | int seq_id; /* sequence id of the iommu */ |
1b573683 | 571 | int agaw; /* agaw of this iommu */ |
4ed0d3e6 | 572 | int msagaw; /* max sagaw of this iommu */ |
1208225c | 573 | unsigned int irq, pr_irq; |
67ccac41 | 574 | u16 segment; /* PCI segment# */ |
9d783ba0 | 575 | unsigned char name[13]; /* Device Name */ |
e61d98d8 | 576 | |
d3f13810 | 577 | #ifdef CONFIG_INTEL_IOMMU |
e61d98d8 | 578 | unsigned long *domain_ids; /* bitmap of domains */ |
8bf47816 | 579 | struct dmar_domain ***domains; /* ptr to domains */ |
e61d98d8 | 580 | spinlock_t lock; /* protect context, domain ids */ |
ba395927 KA |
581 | struct root_entry *root_entry; /* virtual address */ |
582 | ||
a77b67d4 | 583 | struct iommu_flush flush; |
8a94ade4 DW |
584 | #endif |
585 | #ifdef CONFIG_INTEL_IOMMU_SVM | |
a222a7f0 DW |
586 | struct page_req_dsc *prq; |
587 | unsigned char prq_name[16]; /* Name for PRQ interrupt */ | |
66ac4db3 | 588 | struct completion prq_complete; |
3375303e | 589 | struct ioasid_allocator_ops pasid_allocator; /* Custom allocator for PASIDs */ |
e61d98d8 | 590 | #endif |
fe962e90 | 591 | struct q_inval *qi; /* Queued invalidation info */ |
f59c7b69 FY |
592 | u32 *iommu_state; /* Store iommu states between suspend and resume.*/ |
593 | ||
d3f13810 | 594 | #ifdef CONFIG_IRQ_REMAP |
2ae21010 | 595 | struct ir_table *ir_table; /* Interrupt remapping info */ |
b106ee63 JL |
596 | struct irq_domain *ir_domain; |
597 | struct irq_domain *ir_msi_domain; | |
2ae21010 | 598 | #endif |
b0119e87 | 599 | struct iommu_device iommu; /* IOMMU core code handle */ |
ee34b32d | 600 | int node; |
4158c2ec | 601 | u32 flags; /* Software defined flags */ |
b1012ca8 LB |
602 | |
603 | struct dmar_drhd_unit *drhd; | |
ba395927 KA |
604 | }; |
605 | ||
9ddbfb42 LB |
606 | /* PCI domain-device relationship */ |
607 | struct device_domain_info { | |
608 | struct list_head link; /* link to domain siblings */ | |
609 | struct list_head global; /* link to global list */ | |
cc580e41 | 610 | struct list_head table; /* link to pasid table */ |
67b8e02b LB |
611 | struct list_head auxiliary_domains; /* auxiliary domains |
612 | * attached to this device | |
613 | */ | |
4fda230e | 614 | u32 segment; /* PCI segment number */ |
9ddbfb42 LB |
615 | u8 bus; /* PCI bus number */ |
616 | u8 devfn; /* PCI devfn number */ | |
617 | u16 pfsid; /* SRIOV physical function source ID */ | |
618 | u8 pasid_supported:3; | |
619 | u8 pasid_enabled:1; | |
620 | u8 pri_supported:1; | |
621 | u8 pri_enabled:1; | |
622 | u8 ats_supported:1; | |
623 | u8 ats_enabled:1; | |
95587a75 | 624 | u8 auxd_enabled:1; /* Multiple domains per device */ |
9ddbfb42 LB |
625 | u8 ats_qdep; |
626 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ | |
627 | struct intel_iommu *iommu; /* IOMMU used by this device */ | |
628 | struct dmar_domain *domain; /* pointer to domain */ | |
cc580e41 | 629 | struct pasid_table *pasid_table; /* pasid table */ |
9ddbfb42 LB |
630 | }; |
631 | ||
fe962e90 SS |
632 | static inline void __iommu_flush_cache( |
633 | struct intel_iommu *iommu, void *addr, int size) | |
634 | { | |
635 | if (!ecap_coherent(iommu->ecap)) | |
636 | clflush_cache_range(addr, size); | |
637 | } | |
638 | ||
3db9983e JP |
639 | /* Convert generic struct iommu_domain to private struct dmar_domain */ |
640 | static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) | |
641 | { | |
642 | return container_of(dom, struct dmar_domain, domain); | |
643 | } | |
644 | ||
4f2ed183 LB |
645 | /* |
646 | * 0: readable | |
647 | * 1: writable | |
648 | * 2-6: reserved | |
649 | * 7: super page | |
650 | * 8-10: available | |
651 | * 11: snoop behavior | |
652 | * 12-63: Host physcial address | |
653 | */ | |
654 | struct dma_pte { | |
655 | u64 val; | |
656 | }; | |
657 | ||
658 | static inline void dma_clear_pte(struct dma_pte *pte) | |
659 | { | |
660 | pte->val = 0; | |
661 | } | |
662 | ||
663 | static inline u64 dma_pte_addr(struct dma_pte *pte) | |
664 | { | |
665 | #ifdef CONFIG_64BIT | |
ddf09b6d | 666 | return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD); |
4f2ed183 LB |
667 | #else |
668 | /* Must have a full atomic 64-bit read */ | |
ddf09b6d LB |
669 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & |
670 | VTD_PAGE_MASK & (~DMA_FL_PTE_XD); | |
4f2ed183 LB |
671 | #endif |
672 | } | |
673 | ||
674 | static inline bool dma_pte_present(struct dma_pte *pte) | |
675 | { | |
676 | return (pte->val & 3) != 0; | |
677 | } | |
678 | ||
679 | static inline bool dma_pte_superpage(struct dma_pte *pte) | |
680 | { | |
681 | return (pte->val & DMA_PTE_LARGE_PAGE); | |
682 | } | |
683 | ||
684 | static inline int first_pte_in_page(struct dma_pte *pte) | |
685 | { | |
686 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
687 | } | |
688 | ||
e61d98d8 | 689 | extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev); |
aa5d2b51 | 690 | extern int dmar_find_matched_atsr_unit(struct pci_dev *dev); |
e61d98d8 | 691 | |
2ae21010 | 692 | extern int dmar_enable_qi(struct intel_iommu *iommu); |
eba67e5d | 693 | extern void dmar_disable_qi(struct intel_iommu *iommu); |
f59c7b69 | 694 | extern int dmar_reenable_qi(struct intel_iommu *iommu); |
2ae21010 | 695 | extern void qi_global_iec(struct intel_iommu *iommu); |
e820482c | 696 | |
4c25a2c1 DW |
697 | extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, |
698 | u8 fm, u64 type); | |
1f0ef2aa DW |
699 | extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
700 | unsigned int size_order, u64 type); | |
1c48db44 JP |
701 | extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, |
702 | u16 qdep, u64 addr, unsigned mask); | |
61a06a16 | 703 | |
33cd6e64 LB |
704 | void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, |
705 | unsigned long npages, bool ih); | |
61a06a16 JP |
706 | |
707 | void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, | |
708 | u32 pasid, u16 qdep, u64 addr, | |
78df6c86 | 709 | unsigned int size_order); |
61a06a16 JP |
710 | void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, |
711 | int pasid); | |
712 | ||
8a1d8246 LB |
713 | int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc, |
714 | unsigned int count, unsigned long options); | |
715 | /* | |
716 | * Options used in qi_submit_sync: | |
717 | * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8. | |
718 | */ | |
719 | #define QI_OPT_WAIT_DRAIN BIT(0) | |
38717946 | 720 | |
074835f0 YS |
721 | extern int dmar_ir_support(void); |
722 | ||
9ddbfb42 LB |
723 | void *alloc_pgtable_page(int node); |
724 | void free_pgtable_page(void *vaddr); | |
725 | struct intel_iommu *domain_get_iommu(struct dmar_domain *domain); | |
85319dcc LB |
726 | int for_each_device_domain(int (*fn)(struct device_domain_info *info, |
727 | void *data), void *data); | |
6f7db75e | 728 | void iommu_flush_write_buffer(struct intel_iommu *iommu); |
d7cbc0f3 | 729 | int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev); |
e2726dae | 730 | struct dmar_domain *find_domain(struct device *dev); |
e85bb99b | 731 | struct device_domain_info *get_domain_info(struct device *dev); |
dd6692f1 | 732 | struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn); |
9ddbfb42 | 733 | |
2f26e0a9 | 734 | #ifdef CONFIG_INTEL_IOMMU_SVM |
ff3dc652 | 735 | extern void intel_svm_check(struct intel_iommu *iommu); |
a222a7f0 DW |
736 | extern int intel_svm_enable_prq(struct intel_iommu *iommu); |
737 | extern int intel_svm_finish_prq(struct intel_iommu *iommu); | |
56722a43 JP |
738 | int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev, |
739 | struct iommu_gpasid_bind_data *data); | |
740 | int intel_svm_unbind_gpasid(struct device *dev, int pasid); | |
064a57d7 JP |
741 | struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm, |
742 | void *drvdata); | |
743 | void intel_svm_unbind(struct iommu_sva *handle); | |
744 | int intel_svm_get_pasid(struct iommu_sva *handle); | |
8b737121 LB |
745 | int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt, |
746 | struct iommu_page_response *msg); | |
747 | ||
0204a496 DW |
748 | struct svm_dev_ops; |
749 | ||
2f26e0a9 DW |
750 | struct intel_svm_dev { |
751 | struct list_head list; | |
752 | struct rcu_head rcu; | |
753 | struct device *dev; | |
0204a496 | 754 | struct svm_dev_ops *ops; |
064a57d7 JP |
755 | struct iommu_sva sva; |
756 | int pasid; | |
2f26e0a9 DW |
757 | int users; |
758 | u16 did; | |
759 | u16 dev_iotlb:1; | |
760 | u16 sid, qdep; | |
761 | }; | |
762 | ||
763 | struct intel_svm { | |
764 | struct mmu_notifier notifier; | |
765 | struct mm_struct *mm; | |
56722a43 | 766 | |
2f26e0a9 | 767 | struct intel_iommu *iommu; |
569e4f77 | 768 | int flags; |
2f26e0a9 | 769 | int pasid; |
56722a43 | 770 | int gpasid; /* In case that guest PASID is different from host PASID */ |
2f26e0a9 | 771 | struct list_head devs; |
51261aac | 772 | struct list_head list; |
2f26e0a9 | 773 | }; |
ff3dc652 JP |
774 | #else |
775 | static inline void intel_svm_check(struct intel_iommu *iommu) {} | |
2f26e0a9 DW |
776 | #endif |
777 | ||
ee2636b8 SM |
778 | #ifdef CONFIG_INTEL_IOMMU_DEBUGFS |
779 | void intel_iommu_debugfs_init(void); | |
780 | #else | |
781 | static inline void intel_iommu_debugfs_init(void) {} | |
782 | #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */ | |
783 | ||
a5459cfe | 784 | extern const struct attribute_group *intel_iommu_groups[]; |
26b86092 SM |
785 | bool context_present(struct context_entry *context); |
786 | struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, | |
787 | u8 devfn, int alloc); | |
a5459cfe | 788 | |
daedaa33 LB |
789 | #ifdef CONFIG_INTEL_IOMMU |
790 | extern int iommu_calculate_agaw(struct intel_iommu *iommu); | |
791 | extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu); | |
792 | extern int dmar_disabled; | |
793 | extern int intel_iommu_enabled; | |
794 | extern int intel_iommu_tboot_noforce; | |
795 | #else | |
796 | static inline int iommu_calculate_agaw(struct intel_iommu *iommu) | |
797 | { | |
798 | return 0; | |
799 | } | |
800 | static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
801 | { | |
802 | return 0; | |
803 | } | |
804 | #define dmar_disabled (1) | |
805 | #define intel_iommu_enabled (0) | |
806 | #endif | |
807 | ||
ba395927 | 808 | #endif |