[linux-2.6-block.git] / include / linux / hisi_acc_qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

#define QM_QNUM_V1			4096
#define QM_QNUM_V2			1024
#define QM_MAX_VFS_NUM_V2		63

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* mailbox */
#define QM_MB_CMD_SQC                   0x0
#define QM_MB_CMD_CQC                   0x1
#define QM_MB_CMD_EQC                   0x2
#define QM_MB_CMD_AEQC                  0x3
#define QM_MB_CMD_SQC_BT                0x4
#define QM_MB_CMD_CQC_BT                0x5
#define QM_MB_CMD_SQC_VFT_V2            0x6
#define QM_MB_CMD_STOP_QP               0x8
#define QM_MB_CMD_SRC                   0xc
#define QM_MB_CMD_DST                   0xd

#define QM_MB_CMD_SEND_BASE		0x300
#define QM_MB_EVENT_SHIFT               8
#define QM_MB_BUSY_SHIFT		13
#define QM_MB_OP_SHIFT			14
#define QM_MB_CMD_DATA_ADDR_L		0x304
#define QM_MB_CMD_DATA_ADDR_H		0x308
#define QM_MB_MAX_WAIT_CNT		6000

/* doorbell */
#define QM_DOORBELL_CMD_SQ              0
#define QM_DOORBELL_CMD_CQ              1
#define QM_DOORBELL_CMD_EQ              2
#define QM_DOORBELL_CMD_AEQ             3

#define QM_DOORBELL_SQ_CQ_BASE_V2	0x1000
#define QM_DOORBELL_EQ_AEQ_BASE_V2	0x2000
#define QM_QP_MAX_NUM_SHIFT             11
#define QM_DB_CMD_SHIFT_V2		12
#define QM_DB_RAND_SHIFT_V2		16
#define QM_DB_INDEX_SHIFT_V2		32
#define QM_DB_PRIORITY_SHIFT_V2		48

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AM_CFG_SINGLE_PORT_MAX_TRANS	0x300014
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)
#define QM_MAILBOX_TIMEOUT		BIT(13)
#define QM_FLR_TIMEOUT			BIT(14)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
			 QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024
#define QM_MIN_QNUM                     2
#define HISI_ACC_SGL_SGE_NR_MAX		255
#define QM_SHAPER_CFG			0x100164
#define QM_SHAPER_ENABLE		BIT(30)
#define QM_SHAPER_TYPE1_OFFSET		10

/* page number for queue file region */
#define QM_DOORBELL_PAGE_NR		1

/* uacce mode of the driver */
#define UACCE_MODE_NOUACCE		0 /* don't use uacce */
#define UACCE_MODE_SVA			1 /* use uacce sva mode */
#define UACCE_MODE_DESC	"0(default) means only register to crypto, 1 means both register to crypto and uacce"

enum qm_stop_reason {
	QM_NORMAL,
	QM_SOFT_RESET,
	QM_FLR,
};

enum qm_state {
	QM_INIT = 0,
	QM_START,
	QM_CLOSE,
	QM_STOP,
};

enum qp_state {
	QP_INIT = 1,
	QP_START,
	QP_STOP,
	QP_CLOSE,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
	QM_HW_V3 = 0x30,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_QM,
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

struct qm_dfx {
	atomic64_t err_irq_cnt;
	atomic64_t aeq_irq_cnt;
	atomic64_t abnormal_irq_cnt;
	atomic64_t create_qp_err_cnt;
	atomic64_t mb_err_cnt;
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	u32 sqe_mask_offset;
	u32 sqe_mask_len;
	struct qm_dfx dfx;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
};

struct qm_shaper_factor {
	u32 func_qos;
	u64 cir_b;
	u64 cir_u;
	u64 cir_s;
	u64 cbs_s;
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	atomic_t flags;
	int stop_reason;
};

struct hisi_qm;

struct hisi_qm_err_info {
	char *acpi_rst;
	u32 msi_wr_port;
	u32 ecc_2bits_mask;
	u32 dev_ce_mask;
	u32 ce;
	u32 nfe;
	u32 fe;
};

struct hisi_qm_err_status {
	u32 is_qm_ecc_mbit;
	u32 is_dev_ecc_mbit;
};

struct hisi_qm_err_ini {
	int (*hw_init)(struct hisi_qm *qm);
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
	void (*open_axi_master_ooo)(struct hisi_qm *qm);
	void (*close_axi_master_ooo)(struct hisi_qm *qm);
	void (*open_sva_prefetch)(struct hisi_qm *qm);
	void (*close_sva_prefetch)(struct hisi_qm *qm);
	void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
	void (*err_info_init)(struct hisi_qm *qm);
};

struct hisi_qm_list {
	struct mutex lock;
	struct list_head list;
	int (*register_to_crypto)(struct hisi_qm *qm);
	void (*unregister_from_crypto)(struct hisi_qm *qm);
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	void __iomem *db_io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;
	u32 max_qp_num;
	u32 vfs_num;
	u32 db_interval;
	struct list_head list;
	struct hisi_qm_list *qm_list;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;
	struct hisi_qm_err_info err_info;
	struct hisi_qm_err_status err_status;
	unsigned long misc_ctl; /* driver removing and reset sched */

	struct rw_semaphore qps_lock;
	struct idr qp_idr;
	struct hisi_qp *qp_array;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;

	struct workqueue_struct *wq;
	struct work_struct work;
	struct work_struct rst_work;
	struct work_struct cmd_process;

	const char *algs;
	bool use_sva;
	bool is_frozen;

	/* doorbell isolation enable */
	bool use_db_isolation;
	resource_size_t phys_base;
	resource_size_t db_phys_base;
	struct uacce_device *uacce;
	int mode;
	struct qm_shaper_factor *factor;
	u32 mb_qos;
	u32 type_rate;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	atomic_t flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	void (*event_cb)(struct hisi_qp *qp);

	struct hisi_qm *qm;
	bool is_resetting;
	bool is_in_kernel;
	u16 pasid;
	struct uacce_queue *uacce_q;
};

static inline int q_num_set(const char *val, const struct kernel_param *kp,
			    unsigned int device)
{
	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
					      device, NULL);
	u32 n, q_num;
	int ret;

	if (!val)
		return -EINVAL;

	if (!pdev) {
		q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
		pr_info("No device found currently, suppose queue number is %u\n",
			q_num);
	} else {
		if (pdev->revision == QM_HW_V1)
			q_num = QM_QNUM_V1;
		else
			q_num = QM_QNUM_V2;
	}

	ret = kstrtou32(val, 10, &n);
	if (ret || n < QM_MIN_QNUM || n > q_num)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret < 0)
		return ret;

	if (n > QM_MAX_VFS_NUM_V2)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int mode_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret != 0 || (n != UACCE_MODE_SVA &&
			 n != UACCE_MODE_NOUACCE))
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
	return mode_set(val, kp);
}

static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{
	INIT_LIST_HEAD(&qm_list->list);
	mutex_init(&qm_list->lock);
}

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
void hisi_qm_release_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
void hisi_qm_debug_init(struct hisi_qm *qm);
enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
void hisi_qm_reset_prepare(struct pci_dev *pdev);
void hisi_qm_reset_done(struct pci_dev *pdev);

int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	       bool op);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
			   u8 alg_type, int node, struct hisi_qp **qps);
void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
void hisi_qm_dev_shutdown(struct pci_dev *pdev);
void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_resume(struct device *dev);
int hisi_qm_suspend(struct device *dev);
void hisi_qm_pm_uninit(struct hisi_qm *qm);
void hisi_qm_pm_init(struct hisi_qm *qm);
int hisi_qm_get_dfx_access(struct hisi_qm *qm);
void hisi_qm_put_dfx_access(struct hisi_qm *qm);
void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);

/* Used by VFIO ACC live migration driver */
struct pci_driver *hisi_sec_get_pf_driver(void);
struct pci_driver *hisi_hpre_get_pf_driver(void);
struct pci_driver *hisi_zip_get_pf_driver(void);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
1295292d	7	#include <linux/debugfs.h>
263c9959 ZW	8	#include <linux/iopoll.h>
	9	#include <linux/module.h>
	10	#include <linux/pci.h>
	11
20b291f5 ST	12	#define QM_QNUM_V1 4096
20b291f5 ST	13	#define QM_QNUM_V2 1024
35ee280f HF	14	#define QM_MAX_VFS_NUM_V2 63
35ee280f HF	15
263c9959 ZW	16	/* qm user domain */
	17	#define QM_ARUSER_M_CFG_1 0x100088
	18	#define AXUSER_SNOOP_ENABLE BIT(30)
	19	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	20	#define AXUSER_CMD_SMMU_NORMAL 1
	21	#define AXUSER_NS BIT(6)
	22	#define AXUSER_NO BIT(5)
	23	#define AXUSER_FP BIT(4)
	24	#define AXUSER_SSV BIT(0)
	25	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	26	FIELD_PREP(AXUSER_CMD_TYPE, \
	27	AXUSER_CMD_SMMU_NORMAL) \| \
	28	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	29	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	30	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	31	#define QM_AWUSER_M_CFG_1 0x100098
	32	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	33	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	34	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	35	#define WUSER_M_CFG_ENABLE 0xffffffff
	36
b4b084d7 LL	37	/* mailbox */
	38	#define QM_MB_CMD_SQC 0x0
	39	#define QM_MB_CMD_CQC 0x1
	40	#define QM_MB_CMD_EQC 0x2
	41	#define QM_MB_CMD_AEQC 0x3
	42	#define QM_MB_CMD_SQC_BT 0x4
	43	#define QM_MB_CMD_CQC_BT 0x5
	44	#define QM_MB_CMD_SQC_VFT_V2 0x6
	45	#define QM_MB_CMD_STOP_QP 0x8
	46	#define QM_MB_CMD_SRC 0xc
	47	#define QM_MB_CMD_DST 0xd
	48
	49	#define QM_MB_CMD_SEND_BASE 0x300
	50	#define QM_MB_EVENT_SHIFT 8
	51	#define QM_MB_BUSY_SHIFT 13
	52	#define QM_MB_OP_SHIFT 14
	53	#define QM_MB_CMD_DATA_ADDR_L 0x304
	54	#define QM_MB_CMD_DATA_ADDR_H 0x308
	55	#define QM_MB_MAX_WAIT_CNT 6000
	56
	57	/* doorbell */
	58	#define QM_DOORBELL_CMD_SQ 0
	59	#define QM_DOORBELL_CMD_CQ 1
	60	#define QM_DOORBELL_CMD_EQ 2
	61	#define QM_DOORBELL_CMD_AEQ 3
	62
	63	#define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
	64	#define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
	65	#define QM_QP_MAX_NUM_SHIFT 11
	66	#define QM_DB_CMD_SHIFT_V2 12
	67	#define QM_DB_RAND_SHIFT_V2 16
	68	#define QM_DB_INDEX_SHIFT_V2 32
	69	#define QM_DB_PRIORITY_SHIFT_V2 48
	70
263c9959 ZW	71	/* qm cache */
	72	#define QM_CACHE_CTL 0x100050
	73	#define SQC_CACHE_ENABLE BIT(0)
	74	#define CQC_CACHE_ENABLE BIT(1)
	75	#define SQC_CACHE_WB_ENABLE BIT(4)
	76	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	77	#define CQC_CACHE_WB_ENABLE BIT(11)
	78	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	79	#define QM_AXI_M_CFG 0x1000ac
	80	#define AXI_M_CFG 0xffff
	81	#define QM_AXI_M_CFG_ENABLE 0x1000b0
d0228aeb	82	#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
263c9959 ZW	83	#define AXI_M_CFG_ENABLE 0xffffffff
	84	#define QM_PEH_AXUSER_CFG 0x1000cc
	85	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	86	#define PEH_AXUSER_CFG 0x401001
	87	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	88
263c9959 ZW	89	#define QM_AXI_RRESP BIT(0)
	90	#define QM_AXI_BRESP BIT(1)
	91	#define QM_ECC_MBIT BIT(2)
	92	#define QM_ECC_1BIT BIT(3)
	93	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	94	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	95	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	96	#define QM_SQ_CQ_VF_INVALID BIT(7)
	97	#define QM_CQ_VF_INVALID BIT(8)
	98	#define QM_SQ_VF_INVALID BIT(9)
	99	#define QM_DB_TIMEOUT BIT(10)
	100	#define QM_OF_FIFO_OF BIT(11)
	101	#define QM_DB_RANDOM_INVALID BIT(12)
c4aab244 WQ	102	#define QM_MAILBOX_TIMEOUT BIT(13)
c4aab244 WQ	103	#define QM_FLR_TIMEOUT BIT(14)
263c9959 ZW	104
	105	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
	106	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
c4aab244 WQ	107	QM_OF_FIFO_OF \| QM_DB_RANDOM_INVALID \| \
c4aab244 WQ	108	QM_MAILBOX_TIMEOUT \| QM_FLR_TIMEOUT)
263c9959 ZW	109	#define QM_BASE_CE QM_ECC_1BIT
	110
	111	#define QM_Q_DEPTH 1024
c4f8f62f	112	#define QM_MIN_QNUM 2
f081fda2	113	#define HISI_ACC_SGL_SGE_NR_MAX 255
72b010dc KY	114	#define QM_SHAPER_CFG 0x100164
	115	#define QM_SHAPER_ENABLE BIT(30)
	116	#define QM_SHAPER_TYPE1_OFFSET 10
f081fda2	117
9e00df71 ZG	118	/* page number for queue file region */
	119	#define QM_DOORBELL_PAGE_NR 1
	120
f8408d2b KY	121	/* uacce mode of the driver */
	122	#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
	123	#define UACCE_MODE_SVA 1 /* use uacce sva mode */
	124	#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
	125
b67202e8 ZW	126	enum qm_stop_reason {
	127	QM_NORMAL,
	128	QM_SOFT_RESET,
	129	QM_FLR,
	130	};
	131
	132	enum qm_state {
	133	QM_INIT = 0,
	134	QM_START,
	135	QM_CLOSE,
	136	QM_STOP,
	137	};
	138
263c9959	139	enum qp_state {
b67202e8 ZW	140	QP_INIT = 1,
b67202e8 ZW	141	QP_START,
263c9959	142	QP_STOP,
b67202e8	143	QP_CLOSE,
263c9959 ZW	144	};
	145
	146	enum qm_hw_ver {
	147	QM_HW_UNKNOWN = -1,
	148	QM_HW_V1 = 0x20,
	149	QM_HW_V2 = 0x21,
58ca0060	150	QM_HW_V3 = 0x30,
263c9959 ZW	151	};
	152
	153	enum qm_fun_type {
	154	QM_HW_PF,
79e09f30	155	QM_HW_VF,
263c9959 ZW	156	};
263c9959 ZW	157
72c7a68d	158	enum qm_debug_file {
c4392b46	159	CURRENT_QM,
72c7a68d ZW	160	CURRENT_Q,
	161	CLEAR_ENABLE,
	162	DEBUG_FILE_NUM,
	163	};
	164
85026525 LL	165	struct qm_dfx {
	166	atomic64_t err_irq_cnt;
	167	atomic64_t aeq_irq_cnt;
	168	atomic64_t abnormal_irq_cnt;
	169	atomic64_t create_qp_err_cnt;
	170	atomic64_t mb_err_cnt;
	171	};
	172
72c7a68d ZW	173	struct debugfs_file {
	174	enum qm_debug_file index;
	175	struct mutex lock;
	176	struct qm_debug *debug;
	177	};
	178
	179	struct qm_debug {
	180	u32 curr_qm_qp_num;
c31dc9fe ST	181	u32 sqe_mask_offset;
c31dc9fe ST	182	u32 sqe_mask_len;
85026525	183	struct qm_dfx dfx;
72c7a68d ZW	184	struct dentry *debug_root;
	185	struct dentry *qm_d;
	186	struct debugfs_file files[DEBUG_FILE_NUM];
	187	};
	188
72b010dc KY	189	struct qm_shaper_factor {
	190	u32 func_qos;
	191	u64 cir_b;
	192	u64 cir_u;
	193	u64 cir_s;
	194	u64 cbs_s;
	195	};
	196
263c9959 ZW	197	struct qm_dma {
	198	void *va;
	199	dma_addr_t dma;
	200	size_t size;
	201	};
	202
	203	struct hisi_qm_status {
	204	u32 eq_head;
	205	bool eqc_phase;
	206	u32 aeq_head;
	207	bool aeqc_phase;
b67202e8 ZW	208	atomic_t flags;
b67202e8 ZW	209	int stop_reason;
263c9959 ZW	210	};
263c9959 ZW	211
eaebf4c3 ST	212	struct hisi_qm;
	213
	214	struct hisi_qm_err_info {
6c6dd580 ST	215	char *acpi_rst;
	216	u32 msi_wr_port;
	217	u32 ecc_2bits_mask;
1db0016e	218	u32 dev_ce_mask;
eaebf4c3 ST	219	u32 ce;
	220	u32 nfe;
	221	u32 fe;
eaebf4c3 ST	222	};
eaebf4c3 ST	223
6c6dd580 ST	224	struct hisi_qm_err_status {
	225	u32 is_qm_ecc_mbit;
	226	u32 is_dev_ecc_mbit;
	227	};
	228
eaebf4c3	229	struct hisi_qm_err_ini {
6c6dd580	230	int (hw_init)(struct hisi_qm qm);
eaebf4c3 ST	231	void (hw_err_enable)(struct hisi_qm qm);
eaebf4c3 ST	232	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef	233	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
6c6dd580 ST	234	void (clear_dev_hw_err_status)(struct hisi_qm qm, u32 err_sts);
	235	void (open_axi_master_ooo)(struct hisi_qm qm);
	236	void (close_axi_master_ooo)(struct hisi_qm qm);
a5c164b1 LL	237	void (open_sva_prefetch)(struct hisi_qm qm);
a5c164b1 LL	238	void (close_sva_prefetch)(struct hisi_qm qm);
f826e6ef	239	void (log_dev_hw_err)(struct hisi_qm qm, u32 err_sts);
d9e21600	240	void (err_info_init)(struct hisi_qm qm);
eaebf4c3 ST	241	};
eaebf4c3 ST	242
3f1ec97a WQ	243	struct hisi_qm_list {
	244	struct mutex lock;
	245	struct list_head list;
8123455a MY	246	int (register_to_crypto)(struct hisi_qm qm);
8123455a MY	247	void (unregister_from_crypto)(struct hisi_qm qm);
3f1ec97a WQ	248	};
3f1ec97a WQ	249
263c9959 ZW	250	struct hisi_qm {
263c9959 ZW	251	enum qm_hw_ver ver;
79e09f30	252	enum qm_fun_type fun_type;
263c9959 ZW	253	const char *dev_name;
	254	struct pci_dev *pdev;
	255	void __iomem *io_base;
8bbecfb4	256	void __iomem *db_io_base;
263c9959 ZW	257	u32 sqe_size;
	258	u32 qp_base;
	259	u32 qp_num;
700f7d0d	260	u32 qp_in_used;
263c9959	261	u32 ctrl_qp_num;
6250383a	262	u32 max_qp_num;
619e464a	263	u32 vfs_num;
8bbecfb4	264	u32 db_interval;
3f1ec97a	265	struct list_head list;
6c6dd580	266	struct hisi_qm_list *qm_list;
263c9959 ZW	267
	268	struct qm_dma qdma;
	269	struct qm_sqc *sqc;
	270	struct qm_cqc *cqc;
	271	struct qm_eqe *eqe;
	272	struct qm_aeqe *aeqe;
	273	dma_addr_t sqc_dma;
	274	dma_addr_t cqc_dma;
	275	dma_addr_t eqe_dma;
	276	dma_addr_t aeqe_dma;
	277
	278	struct hisi_qm_status status;
eaebf4c3	279	const struct hisi_qm_err_ini *err_ini;
d9e21600	280	struct hisi_qm_err_info err_info;
6c6dd580	281	struct hisi_qm_err_status err_status;
3e9954fe	282	unsigned long misc_ctl; /* driver removing and reset sched */
263c9959	283
b67202e8	284	struct rw_semaphore qps_lock;
5308f660 WQ	285	struct idr qp_idr;
5308f660 WQ	286	struct hisi_qp *qp_array;
263c9959 ZW	287
	288	struct mutex mailbox_lock;
	289
	290	const struct hisi_qm_hw_ops *ops;
	291
72c7a68d ZW	292	struct qm_debug debug;
72c7a68d ZW	293
263c9959	294	u32 error_mask;
263c9959	295
57ca8124 ST	296	struct workqueue_struct *wq;
57ca8124 ST	297	struct work_struct work;
dbdc1ec3	298	struct work_struct rst_work;
e3ac4d20	299	struct work_struct cmd_process;
57ca8124	300
9e00df71	301	const char *algs;
9e00df71	302	bool use_sva;
daa31783	303	bool is_frozen;
6250383a WQ	304
	305	/* doorbell isolation enable */
	306	bool use_db_isolation;
9e00df71	307	resource_size_t phys_base;
8bbecfb4	308	resource_size_t db_phys_base;
9e00df71	309	struct uacce_device *uacce;
f8408d2b	310	int mode;
72b010dc KY	311	struct qm_shaper_factor *factor;
	312	u32 mb_qos;
	313	u32 type_rate;
263c9959 ZW	314	};
	315
	316	struct hisi_qp_status {
	317	atomic_t used;
	318	u16 sq_tail;
	319	u16 cq_head;
	320	bool cqc_phase;
b67202e8	321	atomic_t flags;
263c9959 ZW	322	};
	323
	324	struct hisi_qp_ops {
	325	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	326	};
	327
	328	struct hisi_qp {
	329	u32 qp_id;
	330	u8 alg_type;
	331	u8 req_type;
	332
	333	struct qm_dma qdma;
	334	void *sqe;
	335	struct qm_cqe *cqe;
	336	dma_addr_t sqe_dma;
	337	dma_addr_t cqe_dma;
	338
	339	struct hisi_qp_status qp_status;
	340	struct hisi_qp_ops *hw_ops;
	341	void *qp_ctx;
	342	void (req_cb)(struct hisi_qp qp, void *data);
9e00df71	343	void (event_cb)(struct hisi_qp qp);
263c9959 ZW	344
263c9959 ZW	345	struct hisi_qm *qm;
b67202e8	346	bool is_resetting;
cc3292d1	347	bool is_in_kernel;
9e00df71 ZG	348	u16 pasid;
9e00df71 ZG	349	struct uacce_queue *uacce_q;
263c9959 ZW	350	};
263c9959 ZW	351
20b291f5 ST	352	static inline int q_num_set(const char val, const struct kernel_param kp,
	353	unsigned int device)
	354	{
	355	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
	356	device, NULL);
	357	u32 n, q_num;
20b291f5 ST	358	int ret;
	359
	360	if (!val)
	361	return -EINVAL;
	362
	363	if (!pdev) {
	364	q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
4cf0806e	365	pr_info("No device found currently, suppose queue number is %u\n",
20b291f5 ST	366	q_num);
20b291f5 ST	367	} else {
58ca0060	368	if (pdev->revision == QM_HW_V1)
20b291f5	369	q_num = QM_QNUM_V1;
58ca0060	370	else
20b291f5	371	q_num = QM_QNUM_V2;
20b291f5 ST	372	}
	373
	374	ret = kstrtou32(val, 10, &n);
c4f8f62f	375	if (ret \|\| n < QM_MIN_QNUM \|\| n > q_num)
20b291f5 ST	376	return -EINVAL;
	377
	378	return param_set_int(val, kp);
	379	}
	380
35ee280f HF	381	static inline int vfs_num_set(const char val, const struct kernel_param kp)
	382	{
	383	u32 n;
	384	int ret;
	385
	386	if (!val)
	387	return -EINVAL;
	388
	389	ret = kstrtou32(val, 10, &n);
	390	if (ret < 0)
	391	return ret;
	392
	393	if (n > QM_MAX_VFS_NUM_V2)
	394	return -EINVAL;
	395
	396	return param_set_int(val, kp);
	397	}
	398
f8408d2b KY	399	static inline int mode_set(const char val, const struct kernel_param kp)
	400	{
	401	u32 n;
	402	int ret;
	403
	404	if (!val)
	405	return -EINVAL;
	406
	407	ret = kstrtou32(val, 10, &n);
	408	if (ret != 0 \|\| (n != UACCE_MODE_SVA &&
	409	n != UACCE_MODE_NOUACCE))
	410	return -EINVAL;
	411
	412	return param_set_int(val, kp);
	413	}
	414
	415	static inline int uacce_mode_set(const char val, const struct kernel_param kp)
	416	{
	417	return mode_set(val, kp);
	418	}
	419
3f1ec97a WQ	420	static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
	421	{
	422	INIT_LIST_HEAD(&qm_list->list);
	423	mutex_init(&qm_list->lock);
	424	}
	425
263c9959 ZW	426	int hisi_qm_init(struct hisi_qm *qm);
	427	void hisi_qm_uninit(struct hisi_qm *qm);
	428	int hisi_qm_start(struct hisi_qm *qm);
e88dd6e1	429	int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
263c9959 ZW	430	struct hisi_qp hisi_qm_create_qp(struct hisi_qm qm, u8 alg_type);
	431	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
	432	int hisi_qm_stop_qp(struct hisi_qp *qp);
	433	void hisi_qm_release_qp(struct hisi_qp *qp);
	434	int hisi_qp_send(struct hisi_qp qp, const void msg);
700f7d0d	435	int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
79e09f30	436	int hisi_qm_get_vft(struct hisi_qm qm, u32 base, u32 *number);
a8ff38bd	437	void hisi_qm_debug_init(struct hisi_qm *qm);
263c9959	438	enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
72c7a68d	439	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
cd1b7ae3	440	int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
daa31783	441	int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
cd1b7ae3	442	int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
eaebf4c3 ST	443	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	444	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
f826e6ef ST	445	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	446	pci_channel_state_t state);
6c6dd580	447	pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
7ce396fa ST	448	void hisi_qm_reset_prepare(struct pci_dev *pdev);
7ce396fa ST	449	void hisi_qm_reset_done(struct pci_dev *pdev);
48c1cd40	450
b4b084d7 LL	451	int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
	452	int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	453	bool op);
	454
48c1cd40 ZW	455	struct hisi_acc_sgl_pool;
	456	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	457	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	458	u32 index, dma_addr_t *hw_sgl_dma);
	459	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	460	struct hisi_acc_hw_sgl *hw_sgl);
	461	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	462	u32 count, u32 sge_nr);
	463	void hisi_acc_free_sgl_pool(struct device *dev,
	464	struct hisi_acc_sgl_pool *pool);
3f1ec97a WQ	465	int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
	466	u8 alg_type, int node, struct hisi_qp **qps);
	467	void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
64dfe495	468	void hisi_qm_dev_shutdown(struct pci_dev *pdev);
daa31783	469	void hisi_qm_wait_task_finish(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	470	int hisi_qm_alg_register(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	471	void hisi_qm_alg_unregister(struct hisi_qm qm, struct hisi_qm_list qm_list);
d7ea5339 WQ	472	int hisi_qm_resume(struct device *dev);
d7ea5339 WQ	473	int hisi_qm_suspend(struct device *dev);
607c191b WQ	474	void hisi_qm_pm_uninit(struct hisi_qm *qm);
	475	void hisi_qm_pm_init(struct hisi_qm *qm);
	476	int hisi_qm_get_dfx_access(struct hisi_qm *qm);
	477	void hisi_qm_put_dfx_access(struct hisi_qm *qm);
1295292d	478	void hisi_qm_regs_dump(struct seq_file s, struct debugfs_regset32 regset);
442fbc09 SK	479
	480	/* Used by VFIO ACC live migration driver */
	481	struct pci_driver *hisi_sec_get_pf_driver(void);
	482	struct pci_driver *hisi_hpre_get_pf_driver(void);
	483	struct pci_driver *hisi_zip_get_pf_driver(void);
263c9959	484	#endif