[linux-2.6-block.git] / include / linux / hisi_acc_qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

#define QM_QNUM_V1			4096
#define QM_QNUM_V2			1024
#define QM_MAX_VFS_NUM_V2		63

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* mailbox */
#define QM_MB_CMD_SQC                   0x0
#define QM_MB_CMD_CQC                   0x1
#define QM_MB_CMD_EQC                   0x2
#define QM_MB_CMD_AEQC                  0x3
#define QM_MB_CMD_SQC_BT                0x4
#define QM_MB_CMD_CQC_BT                0x5
#define QM_MB_CMD_SQC_VFT_V2            0x6
#define QM_MB_CMD_STOP_QP               0x8
#define QM_MB_CMD_FLUSH_QM		0x9
#define QM_MB_CMD_SRC                   0xc
#define QM_MB_CMD_DST                   0xd

#define QM_MB_CMD_SEND_BASE		0x300
#define QM_MB_EVENT_SHIFT               8
#define QM_MB_BUSY_SHIFT		13
#define QM_MB_OP_SHIFT			14
#define QM_MB_CMD_DATA_ADDR_L		0x304
#define QM_MB_CMD_DATA_ADDR_H		0x308
#define QM_MB_MAX_WAIT_CNT		6000

/* doorbell */
#define QM_DOORBELL_CMD_SQ              0
#define QM_DOORBELL_CMD_CQ              1
#define QM_DOORBELL_CMD_EQ              2
#define QM_DOORBELL_CMD_AEQ             3

#define QM_DOORBELL_SQ_CQ_BASE_V2	0x1000
#define QM_DOORBELL_EQ_AEQ_BASE_V2	0x2000
#define QM_QP_MAX_NUM_SHIFT             11
#define QM_DB_CMD_SHIFT_V2		12
#define QM_DB_RAND_SHIFT_V2		16
#define QM_DB_INDEX_SHIFT_V2		32
#define QM_DB_PRIORITY_SHIFT_V2		48
#define QM_VF_STATE			0x60

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AM_CFG_SINGLE_PORT_MAX_TRANS	0x300014
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_MIN_QNUM                     2
#define HISI_ACC_SGL_SGE_NR_MAX		255
#define QM_SHAPER_CFG			0x100164
#define QM_SHAPER_ENABLE		BIT(30)
#define QM_SHAPER_TYPE1_OFFSET		10

/* page number for queue file region */
#define QM_DOORBELL_PAGE_NR		1

#define QM_DEV_ALG_MAX_LEN		256

/* uacce mode of the driver */
#define UACCE_MODE_NOUACCE		0 /* don't use uacce */
#define UACCE_MODE_SVA			1 /* use uacce sva mode */
#define UACCE_MODE_DESC	"0(default) means only register to crypto, 1 means both register to crypto and uacce"

enum qm_stop_reason {
	QM_NORMAL,
	QM_SOFT_RESET,
	QM_DOWN,
};

enum qm_state {
	QM_WORK = 0,
	QM_STOP,
};

enum qp_state {
	QP_START = 1,
	QP_STOP,
};

enum qm_hw_ver {
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
	QM_HW_V3 = 0x30,
	QM_HW_V4 = 0x50,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_QM,
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

enum qm_vf_state {
	QM_READY = 0,
	QM_NOT_READY,
};

enum qm_misc_ctl_bits {
	QM_DRIVER_REMOVING = 0x0,
	QM_RST_SCHED,
	QM_RESETTING,
	QM_MODULE_PARAM,
};

enum qm_cap_bits {
	QM_SUPPORT_DB_ISOLATION = 0x0,
	QM_SUPPORT_FUNC_QOS,
	QM_SUPPORT_STOP_QP,
	QM_SUPPORT_STOP_FUNC,
	QM_SUPPORT_MB_COMMAND,
	QM_SUPPORT_SVA_PREFETCH,
	QM_SUPPORT_RPM,
	QM_SUPPORT_DAE,
};

struct qm_dev_alg {
	u64 alg_msk;
	const char *alg;
};

struct qm_dev_dfx {
	u32 dev_state;
	u32 dev_timeout;
};

struct dfx_diff_registers {
	u32 *regs;
	u32 reg_offset;
	u32 reg_len;
};

struct qm_dfx {
	atomic64_t err_irq_cnt;
	atomic64_t aeq_irq_cnt;
	atomic64_t abnormal_irq_cnt;
	atomic64_t create_qp_err_cnt;
	atomic64_t mb_err_cnt;
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	u32 sqe_mask_offset;
	u32 sqe_mask_len;
	struct qm_dfx dfx;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
	struct qm_dev_dfx dev_dfx;
	unsigned int *qm_last_words;
	/* ACC engines recoreding last regs */
	unsigned int *last_words;
	struct dfx_diff_registers *qm_diff_regs;
	struct dfx_diff_registers *acc_diff_regs;
};

struct qm_shaper_factor {
	u32 func_qos;
	u64 cir_b;
	u64 cir_u;
	u64 cir_s;
	u64 cbs_s;
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	atomic_t flags;
	int stop_reason;
};

struct hisi_qm;

enum acc_err_result {
	ACC_ERR_NONE,
	ACC_ERR_NEED_RESET,
	ACC_ERR_RECOVERED,
};

struct hisi_qm_err_info {
	char *acpi_rst;
	u32 msi_wr_port;
	u32 ecc_2bits_mask;
	u32 qm_shutdown_mask;
	u32 dev_shutdown_mask;
	u32 qm_reset_mask;
	u32 dev_reset_mask;
	u32 ce;
	u32 nfe;
	u32 fe;
};

struct hisi_qm_err_status {
	u32 is_qm_ecc_mbit;
	u32 is_dev_ecc_mbit;
};

struct hisi_qm_err_ini {
	int (*hw_init)(struct hisi_qm *qm);
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
	void (*open_axi_master_ooo)(struct hisi_qm *qm);
	void (*close_axi_master_ooo)(struct hisi_qm *qm);
	void (*open_sva_prefetch)(struct hisi_qm *qm);
	void (*close_sva_prefetch)(struct hisi_qm *qm);
	void (*show_last_dfx_regs)(struct hisi_qm *qm);
	void (*err_info_init)(struct hisi_qm *qm);
	enum acc_err_result (*get_err_result)(struct hisi_qm *qm);
	bool (*dev_is_abnormal)(struct hisi_qm *qm);
	int (*set_priv_status)(struct hisi_qm *qm);
};

struct hisi_qm_cap_info {
	u32 type;
	/* Register offset */
	u32 offset;
	/* Bit offset in register */
	u32 shift;
	u32 mask;
	u32 v1_val;
	u32 v2_val;
	u32 v3_val;
};

struct hisi_qm_cap_query_info {
	u32 type;
	const char *name;
	u32 offset;
	u32 v1_val;
	u32 v2_val;
	u32 v3_val;
};

struct hisi_qm_cap_record {
	u32 type;
	const char *name;
	u32 cap_val;
};

struct hisi_qm_cap_tables {
	u32 qm_cap_size;
	struct hisi_qm_cap_record *qm_cap_table;
	u32 dev_cap_size;
	struct hisi_qm_cap_record *dev_cap_table;
};

struct hisi_qm_list {
	struct mutex lock;
	struct list_head list;
	int (*register_to_crypto)(struct hisi_qm *qm);
	void (*unregister_from_crypto)(struct hisi_qm *qm);
};

struct hisi_qm_poll_data {
	struct hisi_qm *qm;
	struct work_struct work;
	u16 *qp_finish_id;
	u16 eqe_num;
};

/**
 * struct qm_err_isolate
 * @isolate_lock: protects device error log
 * @err_threshold: user config error threshold which triggers isolation
 * @is_isolate: device isolation state
 * @uacce_hw_errs: index into qm device error list
 */
struct qm_err_isolate {
	struct mutex isolate_lock;
	u32 err_threshold;
	bool is_isolate;
	struct list_head qm_hw_errs;
};

struct qm_rsv_buf {
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqc *eqc;
	struct qm_aeqc *aeqc;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqc_dma;
	dma_addr_t aeqc_dma;
	struct qm_dma qcdma;
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	void __iomem *db_io_base;

	/* Capbility version, 0: not supports */
	u32 cap_ver;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;
	u32 max_qp_num;
	u32 vfs_num;
	u32 db_interval;
	u16 eq_depth;
	u16 aeq_depth;
	struct list_head list;
	struct hisi_qm_list *qm_list;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;
	struct qm_rsv_buf xqc_buf;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;
	struct hisi_qm_err_info err_info;
	struct hisi_qm_err_status err_status;
	/* driver removing and reset sched */
	unsigned long misc_ctl;
	/* Device capability bit */
	unsigned long caps;

	struct rw_semaphore qps_lock;
	struct idr qp_idr;
	struct hisi_qp *qp_array;
	struct hisi_qm_poll_data *poll_data;

	struct mutex mailbox_lock;

	struct mutex ifc_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;

	struct workqueue_struct *wq;
	struct work_struct rst_work;
	struct work_struct cmd_process;

	bool use_sva;

	resource_size_t phys_base;
	resource_size_t db_phys_base;
	struct uacce_device *uacce;
	int mode;
	struct qm_shaper_factor *factor;
	u32 mb_qos;
	u32 type_rate;
	struct qm_err_isolate isolate_data;

	struct hisi_qm_cap_tables cap_tables;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	atomic_t flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u16 sq_depth;
	u16 cq_depth;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	void (*event_cb)(struct hisi_qp *qp);

	struct hisi_qm *qm;
	bool is_resetting;
	bool is_in_kernel;
	u16 pasid;
	struct uacce_queue *uacce_q;
};

static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret < 0)
		return ret;

	if (n > QM_MAX_VFS_NUM_V2)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int mode_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret != 0 || (n != UACCE_MODE_SVA &&
			 n != UACCE_MODE_NOUACCE))
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
	return mode_set(val, kp);
}

static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{
	INIT_LIST_HEAD(&qm_list->list);
	mutex_init(&qm_list->lock);
}

static inline void hisi_qm_add_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
{
	mutex_lock(&qm_list->lock);
	list_add_tail(&qm->list, &qm_list->list);
	mutex_unlock(&qm_list->lock);
}

static inline void hisi_qm_del_list(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
{
	mutex_lock(&qm_list->lock);
	list_del(&qm->list);
	mutex_unlock(&qm_list->lock);
}

int hisi_qm_q_num_set(const char *val, const struct kernel_param *kp,
		      unsigned int device);
int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
void hisi_qm_stop_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
void hisi_qm_debug_init(struct hisi_qm *qm);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
			  struct dfx_diff_registers *dregs, u32 reg_len);
void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
				struct dfx_diff_registers *dregs, u32 regs_len);

pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
void hisi_qm_reset_prepare(struct pci_dev *pdev);
void hisi_qm_reset_done(struct pci_dev *pdev);

int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	       bool op);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
			   u8 alg_type, int node, struct hisi_qp **qps);
void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
void hisi_qm_dev_shutdown(struct pci_dev *pdev);
void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list, int guard);
int hisi_qm_resume(struct device *dev);
int hisi_qm_suspend(struct device *dev);
void hisi_qm_pm_uninit(struct hisi_qm *qm);
void hisi_qm_pm_init(struct hisi_qm *qm);
int hisi_qm_get_dfx_access(struct hisi_qm *qm);
void hisi_qm_put_dfx_access(struct hisi_qm *qm);
void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
			const struct hisi_qm_cap_info *info_table,
			u32 index, bool is_read);
u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
			const struct hisi_qm_cap_query_info *info_table,
			u32 index, bool is_read);
int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
		     u32 dev_algs_size);

/* Used by VFIO ACC live migration driver */
struct pci_driver *hisi_sec_get_pf_driver(void);
struct pci_driver *hisi_hpre_get_pf_driver(void);
struct pci_driver *hisi_zip_get_pf_driver(void);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
1295292d	7	#include <linux/debugfs.h>
263c9959 ZW	8	#include <linux/iopoll.h>
	9	#include <linux/module.h>
	10	#include <linux/pci.h>
	11
20b291f5 ST	12	#define QM_QNUM_V1 4096
20b291f5 ST	13	#define QM_QNUM_V2 1024
35ee280f HF	14	#define QM_MAX_VFS_NUM_V2 63
35ee280f HF	15
263c9959 ZW	16	/* qm user domain */
	17	#define QM_ARUSER_M_CFG_1 0x100088
	18	#define AXUSER_SNOOP_ENABLE BIT(30)
	19	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	20	#define AXUSER_CMD_SMMU_NORMAL 1
	21	#define AXUSER_NS BIT(6)
	22	#define AXUSER_NO BIT(5)
	23	#define AXUSER_FP BIT(4)
	24	#define AXUSER_SSV BIT(0)
	25	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	26	FIELD_PREP(AXUSER_CMD_TYPE, \
	27	AXUSER_CMD_SMMU_NORMAL) \| \
	28	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	29	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	30	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	31	#define QM_AWUSER_M_CFG_1 0x100098
	32	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	33	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	34	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	35	#define WUSER_M_CFG_ENABLE 0xffffffff
	36
b4b084d7 LL	37	/* mailbox */
	38	#define QM_MB_CMD_SQC 0x0
	39	#define QM_MB_CMD_CQC 0x1
	40	#define QM_MB_CMD_EQC 0x2
	41	#define QM_MB_CMD_AEQC 0x3
	42	#define QM_MB_CMD_SQC_BT 0x4
	43	#define QM_MB_CMD_CQC_BT 0x5
	44	#define QM_MB_CMD_SQC_VFT_V2 0x6
	45	#define QM_MB_CMD_STOP_QP 0x8
12b8ae68	46	#define QM_MB_CMD_FLUSH_QM 0x9
b4b084d7 LL	47	#define QM_MB_CMD_SRC 0xc
	48	#define QM_MB_CMD_DST 0xd
	49
	50	#define QM_MB_CMD_SEND_BASE 0x300
	51	#define QM_MB_EVENT_SHIFT 8
	52	#define QM_MB_BUSY_SHIFT 13
	53	#define QM_MB_OP_SHIFT 14
	54	#define QM_MB_CMD_DATA_ADDR_L 0x304
	55	#define QM_MB_CMD_DATA_ADDR_H 0x308
	56	#define QM_MB_MAX_WAIT_CNT 6000
	57
	58	/* doorbell */
	59	#define QM_DOORBELL_CMD_SQ 0
	60	#define QM_DOORBELL_CMD_CQ 1
	61	#define QM_DOORBELL_CMD_EQ 2
	62	#define QM_DOORBELL_CMD_AEQ 3
	63
	64	#define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
	65	#define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
	66	#define QM_QP_MAX_NUM_SHIFT 11
	67	#define QM_DB_CMD_SHIFT_V2 12
	68	#define QM_DB_RAND_SHIFT_V2 16
	69	#define QM_DB_INDEX_SHIFT_V2 32
	70	#define QM_DB_PRIORITY_SHIFT_V2 48
1e459b25	71	#define QM_VF_STATE 0x60
b4b084d7	72
263c9959 ZW	73	/* qm cache */
	74	#define QM_CACHE_CTL 0x100050
	75	#define SQC_CACHE_ENABLE BIT(0)
	76	#define CQC_CACHE_ENABLE BIT(1)
	77	#define SQC_CACHE_WB_ENABLE BIT(4)
	78	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	79	#define CQC_CACHE_WB_ENABLE BIT(11)
	80	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	81	#define QM_AXI_M_CFG 0x1000ac
	82	#define AXI_M_CFG 0xffff
	83	#define QM_AXI_M_CFG_ENABLE 0x1000b0
d0228aeb	84	#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
263c9959 ZW	85	#define AXI_M_CFG_ENABLE 0xffffffff
	86	#define QM_PEH_AXUSER_CFG 0x1000cc
	87	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	88	#define PEH_AXUSER_CFG 0x401001
	89	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	90
c4f8f62f	91	#define QM_MIN_QNUM 2
f081fda2	92	#define HISI_ACC_SGL_SGE_NR_MAX 255
72b010dc KY	93	#define QM_SHAPER_CFG 0x100164
	94	#define QM_SHAPER_ENABLE BIT(30)
	95	#define QM_SHAPER_TYPE1_OFFSET 10
f081fda2	96
9e00df71 ZG	97	/* page number for queue file region */
	98	#define QM_DOORBELL_PAGE_NR 1
	99
09463346 WQ	100	#define QM_DEV_ALG_MAX_LEN 256
09463346 WQ	101
f8408d2b KY	102	/* uacce mode of the driver */
	103	#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
	104	#define UACCE_MODE_SVA 1 /* use uacce sva mode */
	105	#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
	106
b67202e8 ZW	107	enum qm_stop_reason {
	108	QM_NORMAL,
	109	QM_SOFT_RESET,
4b3ee3ff	110	QM_DOWN,
b67202e8 ZW	111	};
	112
	113	enum qm_state {
c66272a4	114	QM_WORK = 0,
b67202e8 ZW	115	QM_STOP,
	116	};
	117
263c9959	118	enum qp_state {
c66272a4	119	QP_START = 1,
263c9959 ZW	120	QP_STOP,
	121	};
	122
	123	enum qm_hw_ver {
263c9959 ZW	124	QM_HW_V1 = 0x20,
263c9959 ZW	125	QM_HW_V2 = 0x21,
58ca0060	126	QM_HW_V3 = 0x30,
061b27e3	127	QM_HW_V4 = 0x50,
263c9959 ZW	128	};
	129
	130	enum qm_fun_type {
	131	QM_HW_PF,
79e09f30	132	QM_HW_VF,
263c9959 ZW	133	};
263c9959 ZW	134
72c7a68d	135	enum qm_debug_file {
c4392b46	136	CURRENT_QM,
72c7a68d ZW	137	CURRENT_Q,
	138	CLEAR_ENABLE,
	139	DEBUG_FILE_NUM,
	140	};
	141
1e459b25 LL	142	enum qm_vf_state {
	143	QM_READY = 0,
	144	QM_NOT_READY,
	145	};
	146
5831fc1f LL	147	enum qm_misc_ctl_bits {
	148	QM_DRIVER_REMOVING = 0x0,
	149	QM_RST_SCHED,
	150	QM_RESETTING,
	151	QM_MODULE_PARAM,
	152	};
	153
82f00b24 WQ	154	enum qm_cap_bits {
	155	QM_SUPPORT_DB_ISOLATION = 0x0,
	156	QM_SUPPORT_FUNC_QOS,
	157	QM_SUPPORT_STOP_QP,
12b8ae68	158	QM_SUPPORT_STOP_FUNC,
82f00b24 WQ	159	QM_SUPPORT_MB_COMMAND,
	160	QM_SUPPORT_SVA_PREFETCH,
	161	QM_SUPPORT_RPM,
09463346	162	QM_SUPPORT_DAE,
82f00b24 WQ	163	};
82f00b24 WQ	164
f76f0d7f WL	165	struct qm_dev_alg {
	166	u64 alg_msk;
	167	const char *alg;
	168	};
	169
ce133a22 WQ	170	struct qm_dev_dfx {
	171	u32 dev_state;
	172	u32 dev_timeout;
	173	};
	174
f1724d39 KY	175	struct dfx_diff_registers {
	176	u32 *regs;
	177	u32 reg_offset;
	178	u32 reg_len;
	179	};
	180
85026525 LL	181	struct qm_dfx {
	182	atomic64_t err_irq_cnt;
	183	atomic64_t aeq_irq_cnt;
	184	atomic64_t abnormal_irq_cnt;
	185	atomic64_t create_qp_err_cnt;
	186	atomic64_t mb_err_cnt;
	187	};
	188
72c7a68d ZW	189	struct debugfs_file {
	190	enum qm_debug_file index;
	191	struct mutex lock;
	192	struct qm_debug *debug;
	193	};
	194
	195	struct qm_debug {
	196	u32 curr_qm_qp_num;
c31dc9fe ST	197	u32 sqe_mask_offset;
c31dc9fe ST	198	u32 sqe_mask_len;
85026525	199	struct qm_dfx dfx;
72c7a68d ZW	200	struct dentry *debug_root;
	201	struct dentry *qm_d;
	202	struct debugfs_file files[DEBUG_FILE_NUM];
ce133a22	203	struct qm_dev_dfx dev_dfx;
a888ccd6 KY	204	unsigned int *qm_last_words;
	205	/* ACC engines recoreding last regs */
	206	unsigned int *last_words;
f1724d39 KY	207	struct dfx_diff_registers *qm_diff_regs;
f1724d39 KY	208	struct dfx_diff_registers *acc_diff_regs;
72c7a68d ZW	209	};
72c7a68d ZW	210
72b010dc KY	211	struct qm_shaper_factor {
	212	u32 func_qos;
	213	u64 cir_b;
	214	u64 cir_u;
	215	u64 cir_s;
	216	u64 cbs_s;
	217	};
	218
263c9959 ZW	219	struct qm_dma {
	220	void *va;
	221	dma_addr_t dma;
	222	size_t size;
	223	};
	224
	225	struct hisi_qm_status {
	226	u32 eq_head;
	227	bool eqc_phase;
	228	u32 aeq_head;
	229	bool aeqc_phase;
b67202e8 ZW	230	atomic_t flags;
b67202e8 ZW	231	int stop_reason;
263c9959 ZW	232	};
263c9959 ZW	233
eaebf4c3 ST	234	struct hisi_qm;
eaebf4c3 ST	235
c418ba6b WQ	236	enum acc_err_result {
	237	ACC_ERR_NONE,
	238	ACC_ERR_NEED_RESET,
	239	ACC_ERR_RECOVERED,
	240	};
	241
eaebf4c3	242	struct hisi_qm_err_info {
6c6dd580 ST	243	char *acpi_rst;
	244	u32 msi_wr_port;
	245	u32 ecc_2bits_mask;
d90fab0d WQ	246	u32 qm_shutdown_mask;
	247	u32 dev_shutdown_mask;
	248	u32 qm_reset_mask;
	249	u32 dev_reset_mask;
eaebf4c3 ST	250	u32 ce;
	251	u32 nfe;
	252	u32 fe;
eaebf4c3 ST	253	};
eaebf4c3 ST	254
6c6dd580 ST	255	struct hisi_qm_err_status {
	256	u32 is_qm_ecc_mbit;
	257	u32 is_dev_ecc_mbit;
	258	};
	259
eaebf4c3	260	struct hisi_qm_err_ini {
6c6dd580	261	int (hw_init)(struct hisi_qm qm);
eaebf4c3 ST	262	void (hw_err_enable)(struct hisi_qm qm);
eaebf4c3 ST	263	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef	264	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
6c6dd580 ST	265	void (clear_dev_hw_err_status)(struct hisi_qm qm, u32 err_sts);
	266	void (open_axi_master_ooo)(struct hisi_qm qm);
	267	void (close_axi_master_ooo)(struct hisi_qm qm);
a5c164b1 LL	268	void (open_sva_prefetch)(struct hisi_qm qm);
a5c164b1 LL	269	void (close_sva_prefetch)(struct hisi_qm qm);
a888ccd6	270	void (show_last_dfx_regs)(struct hisi_qm qm);
d9e21600	271	void (err_info_init)(struct hisi_qm qm);
c418ba6b	272	enum acc_err_result (get_err_result)(struct hisi_qm qm);
771ba5c9 WQ	273	bool (dev_is_abnormal)(struct hisi_qm qm);
771ba5c9 WQ	274	int (set_priv_status)(struct hisi_qm qm);
eaebf4c3 ST	275	};
eaebf4c3 ST	276
82f00b24 WQ	277	struct hisi_qm_cap_info {
	278	u32 type;
	279	/* Register offset */
	280	u32 offset;
	281	/* Bit offset in register */
	282	u32 shift;
	283	u32 mask;
	284	u32 v1_val;
	285	u32 v2_val;
	286	u32 v3_val;
	287	};
	288
2a69297e QT	289	struct hisi_qm_cap_query_info {
	290	u32 type;
	291	const char *name;
	292	u32 offset;
	293	u32 v1_val;
	294	u32 v2_val;
	295	u32 v3_val;
	296	};
	297
cabe13d0 ZS	298	struct hisi_qm_cap_record {
cabe13d0 ZS	299	u32 type;
2a69297e	300	const char *name;
cabe13d0 ZS	301	u32 cap_val;
	302	};
	303
	304	struct hisi_qm_cap_tables {
2a69297e	305	u32 qm_cap_size;
cabe13d0	306	struct hisi_qm_cap_record *qm_cap_table;
2a69297e	307	u32 dev_cap_size;
cabe13d0 ZS	308	struct hisi_qm_cap_record *dev_cap_table;
	309	};
	310
3f1ec97a WQ	311	struct hisi_qm_list {
	312	struct mutex lock;
	313	struct list_head list;
8123455a MY	314	int (register_to_crypto)(struct hisi_qm qm);
8123455a MY	315	void (unregister_from_crypto)(struct hisi_qm qm);
3f1ec97a WQ	316	};
3f1ec97a WQ	317
d64de977 WQ	318	struct hisi_qm_poll_data {
	319	struct hisi_qm *qm;
	320	struct work_struct work;
	321	u16 *qp_finish_id;
5acab6eb	322	u16 eqe_num;
d64de977 WQ	323	};
d64de977 WQ	324
cd0ac51c KY	325	/**
	326	* struct qm_err_isolate
	327	* @isolate_lock: protects device error log
	328	* @err_threshold: user config error threshold which triggers isolation
	329	* @is_isolate: device isolation state
	330	* @uacce_hw_errs: index into qm device error list
	331	*/
	332	struct qm_err_isolate {
	333	struct mutex isolate_lock;
	334	u32 err_threshold;
	335	bool is_isolate;
	336	struct list_head qm_hw_errs;
	337	};
	338
5b90073d WQ	339	struct qm_rsv_buf {
	340	struct qm_sqc *sqc;
	341	struct qm_cqc *cqc;
	342	struct qm_eqc *eqc;
	343	struct qm_aeqc *aeqc;
	344	dma_addr_t sqc_dma;
	345	dma_addr_t cqc_dma;
	346	dma_addr_t eqc_dma;
	347	dma_addr_t aeqc_dma;
	348	struct qm_dma qcdma;
	349	};
	350
263c9959 ZW	351	struct hisi_qm {
263c9959 ZW	352	enum qm_hw_ver ver;
79e09f30	353	enum qm_fun_type fun_type;
263c9959 ZW	354	const char *dev_name;
	355	struct pci_dev *pdev;
	356	void __iomem *io_base;
8bbecfb4	357	void __iomem *db_io_base;
82f00b24 WQ	358
	359	/* Capbility version, 0: not supports */
	360	u32 cap_ver;
263c9959 ZW	361	u32 sqe_size;
	362	u32 qp_base;
	363	u32 qp_num;
700f7d0d	364	u32 qp_in_used;
263c9959	365	u32 ctrl_qp_num;
6250383a	366	u32 max_qp_num;
619e464a	367	u32 vfs_num;
8bbecfb4	368	u32 db_interval;
129a9f34 WQ	369	u16 eq_depth;
129a9f34 WQ	370	u16 aeq_depth;
3f1ec97a	371	struct list_head list;
6c6dd580	372	struct hisi_qm_list *qm_list;
263c9959 ZW	373
	374	struct qm_dma qdma;
	375	struct qm_sqc *sqc;
	376	struct qm_cqc *cqc;
	377	struct qm_eqe *eqe;
	378	struct qm_aeqe *aeqe;
	379	dma_addr_t sqc_dma;
	380	dma_addr_t cqc_dma;
	381	dma_addr_t eqe_dma;
	382	dma_addr_t aeqe_dma;
5b90073d	383	struct qm_rsv_buf xqc_buf;
263c9959 ZW	384
263c9959 ZW	385	struct hisi_qm_status status;
eaebf4c3	386	const struct hisi_qm_err_ini *err_ini;
d9e21600	387	struct hisi_qm_err_info err_info;
6c6dd580	388	struct hisi_qm_err_status err_status;
9b4eb8f8 WQ	389	/* driver removing and reset sched */
9b4eb8f8 WQ	390	unsigned long misc_ctl;
82f00b24 WQ	391	/* Device capability bit */
82f00b24 WQ	392	unsigned long caps;
263c9959	393
b67202e8	394	struct rw_semaphore qps_lock;
5308f660 WQ	395	struct idr qp_idr;
5308f660 WQ	396	struct hisi_qp *qp_array;
d64de977	397	struct hisi_qm_poll_data *poll_data;
263c9959 ZW	398
	399	struct mutex mailbox_lock;
	400
061b27e3 YS	401	struct mutex ifc_lock;
061b27e3 YS	402
263c9959 ZW	403	const struct hisi_qm_hw_ops *ops;
263c9959 ZW	404
72c7a68d ZW	405	struct qm_debug debug;
72c7a68d ZW	406
263c9959	407	u32 error_mask;
263c9959	408
57ca8124	409	struct workqueue_struct *wq;
dbdc1ec3	410	struct work_struct rst_work;
e3ac4d20	411	struct work_struct cmd_process;
57ca8124	412
9e00df71	413	bool use_sva;
6250383a	414
9e00df71	415	resource_size_t phys_base;
8bbecfb4	416	resource_size_t db_phys_base;
9e00df71	417	struct uacce_device *uacce;
f8408d2b	418	int mode;
72b010dc KY	419	struct qm_shaper_factor *factor;
	420	u32 mb_qos;
	421	u32 type_rate;
cd0ac51c	422	struct qm_err_isolate isolate_data;
cabe13d0 ZS	423
cabe13d0 ZS	424	struct hisi_qm_cap_tables cap_tables;
263c9959 ZW	425	};
	426
	427	struct hisi_qp_status {
	428	atomic_t used;
	429	u16 sq_tail;
	430	u16 cq_head;
	431	bool cqc_phase;
b67202e8	432	atomic_t flags;
263c9959 ZW	433	};
	434
	435	struct hisi_qp_ops {
	436	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	437	};
	438
	439	struct hisi_qp {
	440	u32 qp_id;
129a9f34 WQ	441	u16 sq_depth;
129a9f34 WQ	442	u16 cq_depth;
263c9959 ZW	443	u8 alg_type;
	444	u8 req_type;
	445
	446	struct qm_dma qdma;
	447	void *sqe;
	448	struct qm_cqe *cqe;
	449	dma_addr_t sqe_dma;
	450	dma_addr_t cqe_dma;
	451
	452	struct hisi_qp_status qp_status;
	453	struct hisi_qp_ops *hw_ops;
	454	void *qp_ctx;
	455	void (req_cb)(struct hisi_qp qp, void *data);
9e00df71	456	void (event_cb)(struct hisi_qp qp);
263c9959 ZW	457
263c9959 ZW	458	struct hisi_qm *qm;
b67202e8	459	bool is_resetting;
cc3292d1	460	bool is_in_kernel;
9e00df71 ZG	461	u16 pasid;
9e00df71 ZG	462	struct uacce_queue *uacce_q;
263c9959 ZW	463	};
263c9959 ZW	464
35ee280f HF	465	static inline int vfs_num_set(const char val, const struct kernel_param kp)
	466	{
	467	u32 n;
	468	int ret;
	469
	470	if (!val)
	471	return -EINVAL;
	472
	473	ret = kstrtou32(val, 10, &n);
	474	if (ret < 0)
	475	return ret;
	476
	477	if (n > QM_MAX_VFS_NUM_V2)
	478	return -EINVAL;
	479
	480	return param_set_int(val, kp);
	481	}
	482
f8408d2b KY	483	static inline int mode_set(const char val, const struct kernel_param kp)
	484	{
	485	u32 n;
	486	int ret;
	487
	488	if (!val)
	489	return -EINVAL;
	490
	491	ret = kstrtou32(val, 10, &n);
	492	if (ret != 0 \|\| (n != UACCE_MODE_SVA &&
	493	n != UACCE_MODE_NOUACCE))
	494	return -EINVAL;
	495
	496	return param_set_int(val, kp);
	497	}
	498
	499	static inline int uacce_mode_set(const char val, const struct kernel_param kp)
	500	{
	501	return mode_set(val, kp);
	502	}
	503
3f1ec97a WQ	504	static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
	505	{
	506	INIT_LIST_HEAD(&qm_list->list);
	507	mutex_init(&qm_list->lock);
	508	}
	509
b42ab1c6 WQ	510	static inline void hisi_qm_add_list(struct hisi_qm qm, struct hisi_qm_list qm_list)
	511	{
	512	mutex_lock(&qm_list->lock);
	513	list_add_tail(&qm->list, &qm_list->list);
	514	mutex_unlock(&qm_list->lock);
	515	}
	516
	517	static inline void hisi_qm_del_list(struct hisi_qm qm, struct hisi_qm_list qm_list)
	518	{
	519	mutex_lock(&qm_list->lock);
	520	list_del(&qm->list);
	521	mutex_unlock(&qm_list->lock);
	522	}
	523
452c55dc CH	524	int hisi_qm_q_num_set(const char val, const struct kernel_param kp,
452c55dc CH	525	unsigned int device);
263c9959 ZW	526	int hisi_qm_init(struct hisi_qm *qm);
	527	void hisi_qm_uninit(struct hisi_qm *qm);
	528	int hisi_qm_start(struct hisi_qm *qm);
e88dd6e1	529	int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
263c9959	530	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
9066ac36	531	void hisi_qm_stop_qp(struct hisi_qp *qp);
263c9959	532	int hisi_qp_send(struct hisi_qp qp, const void msg);
a8ff38bd	533	void hisi_qm_debug_init(struct hisi_qm *qm);
72c7a68d	534	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
cd1b7ae3	535	int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
daa31783	536	int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
cd1b7ae3	537	int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
eaebf4c3 ST	538	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	539	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
b40b62ed KY	540	int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
	541	struct dfx_diff_registers *dregs, u32 reg_len);
	542	void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
f1724d39	543	void hisi_qm_acc_diff_regs_dump(struct hisi_qm qm, struct seq_file s,
b40b62ed	544	struct dfx_diff_registers *dregs, u32 regs_len);
f1724d39	545
f826e6ef ST	546	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	547	pci_channel_state_t state);
6c6dd580	548	pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
7ce396fa ST	549	void hisi_qm_reset_prepare(struct pci_dev *pdev);
7ce396fa ST	550	void hisi_qm_reset_done(struct pci_dev *pdev);
48c1cd40	551
b4b084d7 LL	552	int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
	553	int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	554	bool op);
	555
48c1cd40 ZW	556	struct hisi_acc_sgl_pool;
	557	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	558	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	559	u32 index, dma_addr_t *hw_sgl_dma);
	560	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	561	struct hisi_acc_hw_sgl *hw_sgl);
	562	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	563	u32 count, u32 sge_nr);
	564	void hisi_acc_free_sgl_pool(struct device *dev,
	565	struct hisi_acc_sgl_pool *pool);
3f1ec97a WQ	566	int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
	567	u8 alg_type, int node, struct hisi_qp **qps);
	568	void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
64dfe495	569	void hisi_qm_dev_shutdown(struct pci_dev *pdev);
daa31783	570	void hisi_qm_wait_task_finish(struct hisi_qm qm, struct hisi_qm_list qm_list);
b42ab1c6 WQ	571	int hisi_qm_alg_register(struct hisi_qm qm, struct hisi_qm_list qm_list, int guard);
b42ab1c6 WQ	572	void hisi_qm_alg_unregister(struct hisi_qm qm, struct hisi_qm_list qm_list, int guard);
d7ea5339 WQ	573	int hisi_qm_resume(struct device *dev);
d7ea5339 WQ	574	int hisi_qm_suspend(struct device *dev);
607c191b WQ	575	void hisi_qm_pm_uninit(struct hisi_qm *qm);
	576	void hisi_qm_pm_init(struct hisi_qm *qm);
	577	int hisi_qm_get_dfx_access(struct hisi_qm *qm);
	578	void hisi_qm_put_dfx_access(struct hisi_qm *qm);
1295292d	579	void hisi_qm_regs_dump(struct seq_file s, struct debugfs_regset32 regset);
82f00b24 WQ	580	u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
	581	const struct hisi_qm_cap_info *info_table,
	582	u32 index, bool is_read);
2a69297e QT	583	u32 hisi_qm_get_cap_value(struct hisi_qm *qm,
	584	const struct hisi_qm_cap_query_info *info_table,
	585	u32 index, bool is_read);
f76f0d7f WL	586	int hisi_qm_set_algs(struct hisi_qm qm, u64 alg_msk, const struct qm_dev_alg dev_algs,
f76f0d7f WL	587	u32 dev_algs_size);
442fbc09 SK	588
	589	/* Used by VFIO ACC live migration driver */
	590	struct pci_driver *hisi_sec_get_pf_driver(void);
	591	struct pci_driver *hisi_hpre_get_pf_driver(void);
	592	struct pci_driver *hisi_zip_get_pf_driver(void);
263c9959	593	#endif