[linux-block.git] / include / linux / hisi_acc_qm.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2019 HiSilicon Limited. */
#ifndef HISI_ACC_QM_H
#define HISI_ACC_QM_H

#include <linux/bitfield.h>
#include <linux/debugfs.h>
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/pci.h>

#define QM_QNUM_V1			4096
#define QM_QNUM_V2			1024
#define QM_MAX_VFS_NUM_V2		63

/* qm user domain */
#define QM_ARUSER_M_CFG_1		0x100088
#define AXUSER_SNOOP_ENABLE		BIT(30)
#define AXUSER_CMD_TYPE			GENMASK(14, 12)
#define AXUSER_CMD_SMMU_NORMAL		1
#define AXUSER_NS			BIT(6)
#define AXUSER_NO			BIT(5)
#define AXUSER_FP			BIT(4)
#define AXUSER_SSV			BIT(0)
#define AXUSER_BASE			(AXUSER_SNOOP_ENABLE |		\
					FIELD_PREP(AXUSER_CMD_TYPE,	\
					AXUSER_CMD_SMMU_NORMAL) |	\
					AXUSER_NS | AXUSER_NO | AXUSER_FP)
#define QM_ARUSER_M_CFG_ENABLE		0x100090
#define ARUSER_M_CFG_ENABLE		0xfffffffe
#define QM_AWUSER_M_CFG_1		0x100098
#define QM_AWUSER_M_CFG_ENABLE		0x1000a0
#define AWUSER_M_CFG_ENABLE		0xfffffffe
#define QM_WUSER_M_CFG_ENABLE		0x1000a8
#define WUSER_M_CFG_ENABLE		0xffffffff

/* mailbox */
#define QM_MB_CMD_SQC                   0x0
#define QM_MB_CMD_CQC                   0x1
#define QM_MB_CMD_EQC                   0x2
#define QM_MB_CMD_AEQC                  0x3
#define QM_MB_CMD_SQC_BT                0x4
#define QM_MB_CMD_CQC_BT                0x5
#define QM_MB_CMD_SQC_VFT_V2            0x6
#define QM_MB_CMD_STOP_QP               0x8
#define QM_MB_CMD_SRC                   0xc
#define QM_MB_CMD_DST                   0xd

#define QM_MB_CMD_SEND_BASE		0x300
#define QM_MB_EVENT_SHIFT               8
#define QM_MB_BUSY_SHIFT		13
#define QM_MB_OP_SHIFT			14
#define QM_MB_CMD_DATA_ADDR_L		0x304
#define QM_MB_CMD_DATA_ADDR_H		0x308
#define QM_MB_MAX_WAIT_CNT		6000

/* doorbell */
#define QM_DOORBELL_CMD_SQ              0
#define QM_DOORBELL_CMD_CQ              1
#define QM_DOORBELL_CMD_EQ              2
#define QM_DOORBELL_CMD_AEQ             3

#define QM_DOORBELL_SQ_CQ_BASE_V2	0x1000
#define QM_DOORBELL_EQ_AEQ_BASE_V2	0x2000
#define QM_QP_MAX_NUM_SHIFT             11
#define QM_DB_CMD_SHIFT_V2		12
#define QM_DB_RAND_SHIFT_V2		16
#define QM_DB_INDEX_SHIFT_V2		32
#define QM_DB_PRIORITY_SHIFT_V2		48
#define QM_VF_STATE			0x60

/* qm cache */
#define QM_CACHE_CTL			0x100050
#define SQC_CACHE_ENABLE		BIT(0)
#define CQC_CACHE_ENABLE		BIT(1)
#define SQC_CACHE_WB_ENABLE		BIT(4)
#define SQC_CACHE_WB_THRD		GENMASK(10, 5)
#define CQC_CACHE_WB_ENABLE		BIT(11)
#define CQC_CACHE_WB_THRD		GENMASK(17, 12)
#define QM_AXI_M_CFG			0x1000ac
#define AXI_M_CFG			0xffff
#define QM_AXI_M_CFG_ENABLE		0x1000b0
#define AM_CFG_SINGLE_PORT_MAX_TRANS	0x300014
#define AXI_M_CFG_ENABLE		0xffffffff
#define QM_PEH_AXUSER_CFG		0x1000cc
#define QM_PEH_AXUSER_CFG_ENABLE	0x1000d0
#define PEH_AXUSER_CFG			0x401001
#define PEH_AXUSER_CFG_ENABLE		0xffffffff

#define QM_AXI_RRESP			BIT(0)
#define QM_AXI_BRESP			BIT(1)
#define QM_ECC_MBIT			BIT(2)
#define QM_ECC_1BIT			BIT(3)
#define QM_ACC_GET_TASK_TIMEOUT		BIT(4)
#define QM_ACC_DO_TASK_TIMEOUT		BIT(5)
#define QM_ACC_WB_NOT_READY_TIMEOUT	BIT(6)
#define QM_SQ_CQ_VF_INVALID		BIT(7)
#define QM_CQ_VF_INVALID		BIT(8)
#define QM_SQ_VF_INVALID		BIT(9)
#define QM_DB_TIMEOUT			BIT(10)
#define QM_OF_FIFO_OF			BIT(11)
#define QM_DB_RANDOM_INVALID		BIT(12)
#define QM_MAILBOX_TIMEOUT		BIT(13)
#define QM_FLR_TIMEOUT			BIT(14)

#define QM_BASE_NFE	(QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
			 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
			 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID | \
			 QM_MAILBOX_TIMEOUT | QM_FLR_TIMEOUT)
#define QM_BASE_CE			QM_ECC_1BIT

#define QM_Q_DEPTH			1024
#define QM_MIN_QNUM                     2
#define HISI_ACC_SGL_SGE_NR_MAX		255
#define QM_SHAPER_CFG			0x100164
#define QM_SHAPER_ENABLE		BIT(30)
#define QM_SHAPER_TYPE1_OFFSET		10

/* page number for queue file region */
#define QM_DOORBELL_PAGE_NR		1

/* uacce mode of the driver */
#define UACCE_MODE_NOUACCE		0 /* don't use uacce */
#define UACCE_MODE_SVA			1 /* use uacce sva mode */
#define UACCE_MODE_DESC	"0(default) means only register to crypto, 1 means both register to crypto and uacce"

enum qm_stop_reason {
	QM_NORMAL,
	QM_SOFT_RESET,
	QM_FLR,
};

enum qm_state {
	QM_INIT = 0,
	QM_START,
	QM_CLOSE,
	QM_STOP,
};

enum qp_state {
	QP_INIT = 1,
	QP_START,
	QP_STOP,
	QP_CLOSE,
};

enum qm_hw_ver {
	QM_HW_UNKNOWN = -1,
	QM_HW_V1 = 0x20,
	QM_HW_V2 = 0x21,
	QM_HW_V3 = 0x30,
};

enum qm_fun_type {
	QM_HW_PF,
	QM_HW_VF,
};

enum qm_debug_file {
	CURRENT_QM,
	CURRENT_Q,
	CLEAR_ENABLE,
	DEBUG_FILE_NUM,
};

enum qm_vf_state {
	QM_READY = 0,
	QM_NOT_READY,
};

struct dfx_diff_registers {
	u32 *regs;
	u32 reg_offset;
	u32 reg_len;
};

struct qm_dfx {
	atomic64_t err_irq_cnt;
	atomic64_t aeq_irq_cnt;
	atomic64_t abnormal_irq_cnt;
	atomic64_t create_qp_err_cnt;
	atomic64_t mb_err_cnt;
};

struct debugfs_file {
	enum qm_debug_file index;
	struct mutex lock;
	struct qm_debug *debug;
};

struct qm_debug {
	u32 curr_qm_qp_num;
	u32 sqe_mask_offset;
	u32 sqe_mask_len;
	struct qm_dfx dfx;
	struct dentry *debug_root;
	struct dentry *qm_d;
	struct debugfs_file files[DEBUG_FILE_NUM];
	unsigned int *qm_last_words;
	/* ACC engines recoreding last regs */
	unsigned int *last_words;
	struct dfx_diff_registers *qm_diff_regs;
	struct dfx_diff_registers *acc_diff_regs;
};

struct qm_shaper_factor {
	u32 func_qos;
	u64 cir_b;
	u64 cir_u;
	u64 cir_s;
	u64 cbs_s;
};

struct qm_dma {
	void *va;
	dma_addr_t dma;
	size_t size;
};

struct hisi_qm_status {
	u32 eq_head;
	bool eqc_phase;
	u32 aeq_head;
	bool aeqc_phase;
	atomic_t flags;
	int stop_reason;
};

struct hisi_qm;

struct hisi_qm_err_info {
	char *acpi_rst;
	u32 msi_wr_port;
	u32 ecc_2bits_mask;
	u32 dev_ce_mask;
	u32 ce;
	u32 nfe;
	u32 fe;
};

struct hisi_qm_err_status {
	u32 is_qm_ecc_mbit;
	u32 is_dev_ecc_mbit;
};

struct hisi_qm_err_ini {
	int (*hw_init)(struct hisi_qm *qm);
	void (*hw_err_enable)(struct hisi_qm *qm);
	void (*hw_err_disable)(struct hisi_qm *qm);
	u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
	void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
	void (*open_axi_master_ooo)(struct hisi_qm *qm);
	void (*close_axi_master_ooo)(struct hisi_qm *qm);
	void (*open_sva_prefetch)(struct hisi_qm *qm);
	void (*close_sva_prefetch)(struct hisi_qm *qm);
	void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
	void (*show_last_dfx_regs)(struct hisi_qm *qm);
	void (*err_info_init)(struct hisi_qm *qm);
};

struct hisi_qm_list {
	struct mutex lock;
	struct list_head list;
	int (*register_to_crypto)(struct hisi_qm *qm);
	void (*unregister_from_crypto)(struct hisi_qm *qm);
};

struct hisi_qm_poll_data {
	struct hisi_qm *qm;
	struct work_struct work;
	u16 *qp_finish_id;
};

struct hisi_qm {
	enum qm_hw_ver ver;
	enum qm_fun_type fun_type;
	const char *dev_name;
	struct pci_dev *pdev;
	void __iomem *io_base;
	void __iomem *db_io_base;
	u32 sqe_size;
	u32 qp_base;
	u32 qp_num;
	u32 qp_in_used;
	u32 ctrl_qp_num;
	u32 max_qp_num;
	u32 vfs_num;
	u32 db_interval;
	struct list_head list;
	struct hisi_qm_list *qm_list;

	struct qm_dma qdma;
	struct qm_sqc *sqc;
	struct qm_cqc *cqc;
	struct qm_eqe *eqe;
	struct qm_aeqe *aeqe;
	dma_addr_t sqc_dma;
	dma_addr_t cqc_dma;
	dma_addr_t eqe_dma;
	dma_addr_t aeqe_dma;

	struct hisi_qm_status status;
	const struct hisi_qm_err_ini *err_ini;
	struct hisi_qm_err_info err_info;
	struct hisi_qm_err_status err_status;
	unsigned long misc_ctl; /* driver removing and reset sched */

	struct rw_semaphore qps_lock;
	struct idr qp_idr;
	struct hisi_qp *qp_array;
	struct hisi_qm_poll_data *poll_data;

	struct mutex mailbox_lock;

	const struct hisi_qm_hw_ops *ops;

	struct qm_debug debug;

	u32 error_mask;

	struct workqueue_struct *wq;
	struct work_struct rst_work;
	struct work_struct cmd_process;

	const char *algs;
	bool use_sva;
	bool is_frozen;

	/* doorbell isolation enable */
	bool use_db_isolation;
	resource_size_t phys_base;
	resource_size_t db_phys_base;
	struct uacce_device *uacce;
	int mode;
	struct qm_shaper_factor *factor;
	u32 mb_qos;
	u32 type_rate;
};

struct hisi_qp_status {
	atomic_t used;
	u16 sq_tail;
	u16 cq_head;
	bool cqc_phase;
	atomic_t flags;
};

struct hisi_qp_ops {
	int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
};

struct hisi_qp {
	u32 qp_id;
	u8 alg_type;
	u8 req_type;

	struct qm_dma qdma;
	void *sqe;
	struct qm_cqe *cqe;
	dma_addr_t sqe_dma;
	dma_addr_t cqe_dma;

	struct hisi_qp_status qp_status;
	struct hisi_qp_ops *hw_ops;
	void *qp_ctx;
	void (*req_cb)(struct hisi_qp *qp, void *data);
	void (*event_cb)(struct hisi_qp *qp);

	struct hisi_qm *qm;
	bool is_resetting;
	bool is_in_kernel;
	u16 pasid;
	struct uacce_queue *uacce_q;
};

static inline int q_num_set(const char *val, const struct kernel_param *kp,
			    unsigned int device)
{
	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
					      device, NULL);
	u32 n, q_num;
	int ret;

	if (!val)
		return -EINVAL;

	if (!pdev) {
		q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
		pr_info("No device found currently, suppose queue number is %u\n",
			q_num);
	} else {
		if (pdev->revision == QM_HW_V1)
			q_num = QM_QNUM_V1;
		else
			q_num = QM_QNUM_V2;
	}

	ret = kstrtou32(val, 10, &n);
	if (ret || n < QM_MIN_QNUM || n > q_num)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret < 0)
		return ret;

	if (n > QM_MAX_VFS_NUM_V2)
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int mode_set(const char *val, const struct kernel_param *kp)
{
	u32 n;
	int ret;

	if (!val)
		return -EINVAL;

	ret = kstrtou32(val, 10, &n);
	if (ret != 0 || (n != UACCE_MODE_SVA &&
			 n != UACCE_MODE_NOUACCE))
		return -EINVAL;

	return param_set_int(val, kp);
}

static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
{
	return mode_set(val, kp);
}

static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
{
	INIT_LIST_HEAD(&qm_list->list);
	mutex_init(&qm_list->lock);
}

int hisi_qm_init(struct hisi_qm *qm);
void hisi_qm_uninit(struct hisi_qm *qm);
int hisi_qm_start(struct hisi_qm *qm);
int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
int hisi_qm_stop_qp(struct hisi_qp *qp);
int hisi_qp_send(struct hisi_qp *qp, const void *msg);
void hisi_qm_debug_init(struct hisi_qm *qm);
void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
void hisi_qm_dev_err_init(struct hisi_qm *qm);
void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
int hisi_qm_diff_regs_init(struct hisi_qm *qm,
		struct dfx_diff_registers *dregs, int reg_len);
void hisi_qm_diff_regs_uninit(struct hisi_qm *qm, int reg_len);
void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
		struct dfx_diff_registers *dregs, int regs_len);

pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
					  pci_channel_state_t state);
pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
void hisi_qm_reset_prepare(struct pci_dev *pdev);
void hisi_qm_reset_done(struct pci_dev *pdev);

int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	       bool op);

struct hisi_acc_sgl_pool;
struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
	struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
	u32 index, dma_addr_t *hw_sgl_dma);
void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
			   struct hisi_acc_hw_sgl *hw_sgl);
struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
						   u32 count, u32 sge_nr);
void hisi_acc_free_sgl_pool(struct device *dev,
			    struct hisi_acc_sgl_pool *pool);
int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
			   u8 alg_type, int node, struct hisi_qp **qps);
void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
void hisi_qm_dev_shutdown(struct pci_dev *pdev);
void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
int hisi_qm_resume(struct device *dev);
int hisi_qm_suspend(struct device *dev);
void hisi_qm_pm_uninit(struct hisi_qm *qm);
void hisi_qm_pm_init(struct hisi_qm *qm);
int hisi_qm_get_dfx_access(struct hisi_qm *qm);
void hisi_qm_put_dfx_access(struct hisi_qm *qm);
void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);

/* Used by VFIO ACC live migration driver */
struct pci_driver *hisi_sec_get_pf_driver(void);
struct pci_driver *hisi_hpre_get_pf_driver(void);
struct pci_driver *hisi_zip_get_pf_driver(void);
#endif
Commit	Line	Data
263c9959 ZW	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2019 HiSilicon Limited. */
	3	#ifndef HISI_ACC_QM_H
	4	#define HISI_ACC_QM_H
	5
	6	#include <linux/bitfield.h>
1295292d	7	#include <linux/debugfs.h>
263c9959 ZW	8	#include <linux/iopoll.h>
	9	#include <linux/module.h>
	10	#include <linux/pci.h>
	11
20b291f5 ST	12	#define QM_QNUM_V1 4096
20b291f5 ST	13	#define QM_QNUM_V2 1024
35ee280f HF	14	#define QM_MAX_VFS_NUM_V2 63
35ee280f HF	15
263c9959 ZW	16	/* qm user domain */
	17	#define QM_ARUSER_M_CFG_1 0x100088
	18	#define AXUSER_SNOOP_ENABLE BIT(30)
	19	#define AXUSER_CMD_TYPE GENMASK(14, 12)
	20	#define AXUSER_CMD_SMMU_NORMAL 1
	21	#define AXUSER_NS BIT(6)
	22	#define AXUSER_NO BIT(5)
	23	#define AXUSER_FP BIT(4)
	24	#define AXUSER_SSV BIT(0)
	25	#define AXUSER_BASE (AXUSER_SNOOP_ENABLE \| \
	26	FIELD_PREP(AXUSER_CMD_TYPE, \
	27	AXUSER_CMD_SMMU_NORMAL) \| \
	28	AXUSER_NS \| AXUSER_NO \| AXUSER_FP)
	29	#define QM_ARUSER_M_CFG_ENABLE 0x100090
	30	#define ARUSER_M_CFG_ENABLE 0xfffffffe
	31	#define QM_AWUSER_M_CFG_1 0x100098
	32	#define QM_AWUSER_M_CFG_ENABLE 0x1000a0
	33	#define AWUSER_M_CFG_ENABLE 0xfffffffe
	34	#define QM_WUSER_M_CFG_ENABLE 0x1000a8
	35	#define WUSER_M_CFG_ENABLE 0xffffffff
	36
b4b084d7 LL	37	/* mailbox */
	38	#define QM_MB_CMD_SQC 0x0
	39	#define QM_MB_CMD_CQC 0x1
	40	#define QM_MB_CMD_EQC 0x2
	41	#define QM_MB_CMD_AEQC 0x3
	42	#define QM_MB_CMD_SQC_BT 0x4
	43	#define QM_MB_CMD_CQC_BT 0x5
	44	#define QM_MB_CMD_SQC_VFT_V2 0x6
	45	#define QM_MB_CMD_STOP_QP 0x8
	46	#define QM_MB_CMD_SRC 0xc
	47	#define QM_MB_CMD_DST 0xd
	48
	49	#define QM_MB_CMD_SEND_BASE 0x300
	50	#define QM_MB_EVENT_SHIFT 8
	51	#define QM_MB_BUSY_SHIFT 13
	52	#define QM_MB_OP_SHIFT 14
	53	#define QM_MB_CMD_DATA_ADDR_L 0x304
	54	#define QM_MB_CMD_DATA_ADDR_H 0x308
	55	#define QM_MB_MAX_WAIT_CNT 6000
	56
	57	/* doorbell */
	58	#define QM_DOORBELL_CMD_SQ 0
	59	#define QM_DOORBELL_CMD_CQ 1
	60	#define QM_DOORBELL_CMD_EQ 2
	61	#define QM_DOORBELL_CMD_AEQ 3
	62
	63	#define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
	64	#define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
	65	#define QM_QP_MAX_NUM_SHIFT 11
	66	#define QM_DB_CMD_SHIFT_V2 12
	67	#define QM_DB_RAND_SHIFT_V2 16
	68	#define QM_DB_INDEX_SHIFT_V2 32
	69	#define QM_DB_PRIORITY_SHIFT_V2 48
1e459b25	70	#define QM_VF_STATE 0x60
b4b084d7	71
263c9959 ZW	72	/* qm cache */
	73	#define QM_CACHE_CTL 0x100050
	74	#define SQC_CACHE_ENABLE BIT(0)
	75	#define CQC_CACHE_ENABLE BIT(1)
	76	#define SQC_CACHE_WB_ENABLE BIT(4)
	77	#define SQC_CACHE_WB_THRD GENMASK(10, 5)
	78	#define CQC_CACHE_WB_ENABLE BIT(11)
	79	#define CQC_CACHE_WB_THRD GENMASK(17, 12)
	80	#define QM_AXI_M_CFG 0x1000ac
	81	#define AXI_M_CFG 0xffff
	82	#define QM_AXI_M_CFG_ENABLE 0x1000b0
d0228aeb	83	#define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
263c9959 ZW	84	#define AXI_M_CFG_ENABLE 0xffffffff
	85	#define QM_PEH_AXUSER_CFG 0x1000cc
	86	#define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
	87	#define PEH_AXUSER_CFG 0x401001
	88	#define PEH_AXUSER_CFG_ENABLE 0xffffffff
	89
263c9959 ZW	90	#define QM_AXI_RRESP BIT(0)
	91	#define QM_AXI_BRESP BIT(1)
	92	#define QM_ECC_MBIT BIT(2)
	93	#define QM_ECC_1BIT BIT(3)
	94	#define QM_ACC_GET_TASK_TIMEOUT BIT(4)
	95	#define QM_ACC_DO_TASK_TIMEOUT BIT(5)
	96	#define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
	97	#define QM_SQ_CQ_VF_INVALID BIT(7)
	98	#define QM_CQ_VF_INVALID BIT(8)
	99	#define QM_SQ_VF_INVALID BIT(9)
	100	#define QM_DB_TIMEOUT BIT(10)
	101	#define QM_OF_FIFO_OF BIT(11)
	102	#define QM_DB_RANDOM_INVALID BIT(12)
c4aab244 WQ	103	#define QM_MAILBOX_TIMEOUT BIT(13)
c4aab244 WQ	104	#define QM_FLR_TIMEOUT BIT(14)
263c9959 ZW	105
	106	#define QM_BASE_NFE (QM_AXI_RRESP \| QM_AXI_BRESP \| QM_ECC_MBIT \| \
	107	QM_ACC_GET_TASK_TIMEOUT \| QM_DB_TIMEOUT \| \
c4aab244 WQ	108	QM_OF_FIFO_OF \| QM_DB_RANDOM_INVALID \| \
c4aab244 WQ	109	QM_MAILBOX_TIMEOUT \| QM_FLR_TIMEOUT)
263c9959 ZW	110	#define QM_BASE_CE QM_ECC_1BIT
	111
	112	#define QM_Q_DEPTH 1024
c4f8f62f	113	#define QM_MIN_QNUM 2
f081fda2	114	#define HISI_ACC_SGL_SGE_NR_MAX 255
72b010dc KY	115	#define QM_SHAPER_CFG 0x100164
	116	#define QM_SHAPER_ENABLE BIT(30)
	117	#define QM_SHAPER_TYPE1_OFFSET 10
f081fda2	118
9e00df71 ZG	119	/* page number for queue file region */
	120	#define QM_DOORBELL_PAGE_NR 1
	121
f8408d2b KY	122	/* uacce mode of the driver */
	123	#define UACCE_MODE_NOUACCE 0 /* don't use uacce */
	124	#define UACCE_MODE_SVA 1 /* use uacce sva mode */
	125	#define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
	126
b67202e8 ZW	127	enum qm_stop_reason {
	128	QM_NORMAL,
	129	QM_SOFT_RESET,
	130	QM_FLR,
	131	};
	132
	133	enum qm_state {
	134	QM_INIT = 0,
	135	QM_START,
	136	QM_CLOSE,
	137	QM_STOP,
	138	};
	139
263c9959	140	enum qp_state {
b67202e8 ZW	141	QP_INIT = 1,
b67202e8 ZW	142	QP_START,
263c9959	143	QP_STOP,
b67202e8	144	QP_CLOSE,
263c9959 ZW	145	};
	146
	147	enum qm_hw_ver {
	148	QM_HW_UNKNOWN = -1,
	149	QM_HW_V1 = 0x20,
	150	QM_HW_V2 = 0x21,
58ca0060	151	QM_HW_V3 = 0x30,
263c9959 ZW	152	};
	153
	154	enum qm_fun_type {
	155	QM_HW_PF,
79e09f30	156	QM_HW_VF,
263c9959 ZW	157	};
263c9959 ZW	158
72c7a68d	159	enum qm_debug_file {
c4392b46	160	CURRENT_QM,
72c7a68d ZW	161	CURRENT_Q,
	162	CLEAR_ENABLE,
	163	DEBUG_FILE_NUM,
	164	};
	165
1e459b25 LL	166	enum qm_vf_state {
	167	QM_READY = 0,
	168	QM_NOT_READY,
	169	};
	170
f1724d39 KY	171	struct dfx_diff_registers {
	172	u32 *regs;
	173	u32 reg_offset;
	174	u32 reg_len;
	175	};
	176
85026525 LL	177	struct qm_dfx {
	178	atomic64_t err_irq_cnt;
	179	atomic64_t aeq_irq_cnt;
	180	atomic64_t abnormal_irq_cnt;
	181	atomic64_t create_qp_err_cnt;
	182	atomic64_t mb_err_cnt;
	183	};
	184
72c7a68d ZW	185	struct debugfs_file {
	186	enum qm_debug_file index;
	187	struct mutex lock;
	188	struct qm_debug *debug;
	189	};
	190
	191	struct qm_debug {
	192	u32 curr_qm_qp_num;
c31dc9fe ST	193	u32 sqe_mask_offset;
c31dc9fe ST	194	u32 sqe_mask_len;
85026525	195	struct qm_dfx dfx;
72c7a68d ZW	196	struct dentry *debug_root;
	197	struct dentry *qm_d;
	198	struct debugfs_file files[DEBUG_FILE_NUM];
a888ccd6 KY	199	unsigned int *qm_last_words;
	200	/* ACC engines recoreding last regs */
	201	unsigned int *last_words;
f1724d39 KY	202	struct dfx_diff_registers *qm_diff_regs;
f1724d39 KY	203	struct dfx_diff_registers *acc_diff_regs;
72c7a68d ZW	204	};
72c7a68d ZW	205
72b010dc KY	206	struct qm_shaper_factor {
	207	u32 func_qos;
	208	u64 cir_b;
	209	u64 cir_u;
	210	u64 cir_s;
	211	u64 cbs_s;
	212	};
	213
263c9959 ZW	214	struct qm_dma {
	215	void *va;
	216	dma_addr_t dma;
	217	size_t size;
	218	};
	219
	220	struct hisi_qm_status {
	221	u32 eq_head;
	222	bool eqc_phase;
	223	u32 aeq_head;
	224	bool aeqc_phase;
b67202e8 ZW	225	atomic_t flags;
b67202e8 ZW	226	int stop_reason;
263c9959 ZW	227	};
263c9959 ZW	228
eaebf4c3 ST	229	struct hisi_qm;
	230
	231	struct hisi_qm_err_info {
6c6dd580 ST	232	char *acpi_rst;
	233	u32 msi_wr_port;
	234	u32 ecc_2bits_mask;
1db0016e	235	u32 dev_ce_mask;
eaebf4c3 ST	236	u32 ce;
	237	u32 nfe;
	238	u32 fe;
eaebf4c3 ST	239	};
eaebf4c3 ST	240
6c6dd580 ST	241	struct hisi_qm_err_status {
	242	u32 is_qm_ecc_mbit;
	243	u32 is_dev_ecc_mbit;
	244	};
	245
eaebf4c3	246	struct hisi_qm_err_ini {
6c6dd580	247	int (hw_init)(struct hisi_qm qm);
eaebf4c3 ST	248	void (hw_err_enable)(struct hisi_qm qm);
eaebf4c3 ST	249	void (hw_err_disable)(struct hisi_qm qm);
f826e6ef	250	u32 (get_dev_hw_err_status)(struct hisi_qm qm);
6c6dd580 ST	251	void (clear_dev_hw_err_status)(struct hisi_qm qm, u32 err_sts);
	252	void (open_axi_master_ooo)(struct hisi_qm qm);
	253	void (close_axi_master_ooo)(struct hisi_qm qm);
a5c164b1 LL	254	void (open_sva_prefetch)(struct hisi_qm qm);
a5c164b1 LL	255	void (close_sva_prefetch)(struct hisi_qm qm);
f826e6ef	256	void (log_dev_hw_err)(struct hisi_qm qm, u32 err_sts);
a888ccd6	257	void (show_last_dfx_regs)(struct hisi_qm qm);
d9e21600	258	void (err_info_init)(struct hisi_qm qm);
eaebf4c3 ST	259	};
eaebf4c3 ST	260
3f1ec97a WQ	261	struct hisi_qm_list {
	262	struct mutex lock;
	263	struct list_head list;
8123455a MY	264	int (register_to_crypto)(struct hisi_qm qm);
8123455a MY	265	void (unregister_from_crypto)(struct hisi_qm qm);
3f1ec97a WQ	266	};
3f1ec97a WQ	267
d64de977 WQ	268	struct hisi_qm_poll_data {
	269	struct hisi_qm *qm;
	270	struct work_struct work;
	271	u16 *qp_finish_id;
	272	};
	273
263c9959 ZW	274	struct hisi_qm {
263c9959 ZW	275	enum qm_hw_ver ver;
79e09f30	276	enum qm_fun_type fun_type;
263c9959 ZW	277	const char *dev_name;
	278	struct pci_dev *pdev;
	279	void __iomem *io_base;
8bbecfb4	280	void __iomem *db_io_base;
263c9959 ZW	281	u32 sqe_size;
	282	u32 qp_base;
	283	u32 qp_num;
700f7d0d	284	u32 qp_in_used;
263c9959	285	u32 ctrl_qp_num;
6250383a	286	u32 max_qp_num;
619e464a	287	u32 vfs_num;
8bbecfb4	288	u32 db_interval;
3f1ec97a	289	struct list_head list;
6c6dd580	290	struct hisi_qm_list *qm_list;
263c9959 ZW	291
	292	struct qm_dma qdma;
	293	struct qm_sqc *sqc;
	294	struct qm_cqc *cqc;
	295	struct qm_eqe *eqe;
	296	struct qm_aeqe *aeqe;
	297	dma_addr_t sqc_dma;
	298	dma_addr_t cqc_dma;
	299	dma_addr_t eqe_dma;
	300	dma_addr_t aeqe_dma;
	301
	302	struct hisi_qm_status status;
eaebf4c3	303	const struct hisi_qm_err_ini *err_ini;
d9e21600	304	struct hisi_qm_err_info err_info;
6c6dd580	305	struct hisi_qm_err_status err_status;
3e9954fe	306	unsigned long misc_ctl; /* driver removing and reset sched */
263c9959	307
b67202e8	308	struct rw_semaphore qps_lock;
5308f660 WQ	309	struct idr qp_idr;
5308f660 WQ	310	struct hisi_qp *qp_array;
d64de977	311	struct hisi_qm_poll_data *poll_data;
263c9959 ZW	312
	313	struct mutex mailbox_lock;
	314
	315	const struct hisi_qm_hw_ops *ops;
	316
72c7a68d ZW	317	struct qm_debug debug;
72c7a68d ZW	318
263c9959	319	u32 error_mask;
263c9959	320
57ca8124	321	struct workqueue_struct *wq;
dbdc1ec3	322	struct work_struct rst_work;
e3ac4d20	323	struct work_struct cmd_process;
57ca8124	324
9e00df71	325	const char *algs;
9e00df71	326	bool use_sva;
daa31783	327	bool is_frozen;
6250383a WQ	328
	329	/* doorbell isolation enable */
	330	bool use_db_isolation;
9e00df71	331	resource_size_t phys_base;
8bbecfb4	332	resource_size_t db_phys_base;
9e00df71	333	struct uacce_device *uacce;
f8408d2b	334	int mode;
72b010dc KY	335	struct qm_shaper_factor *factor;
	336	u32 mb_qos;
	337	u32 type_rate;
263c9959 ZW	338	};
	339
	340	struct hisi_qp_status {
	341	atomic_t used;
	342	u16 sq_tail;
	343	u16 cq_head;
	344	bool cqc_phase;
b67202e8	345	atomic_t flags;
263c9959 ZW	346	};
	347
	348	struct hisi_qp_ops {
	349	int (fill_sqe)(void sqe, void q_parm, void d_parm);
	350	};
	351
	352	struct hisi_qp {
	353	u32 qp_id;
	354	u8 alg_type;
	355	u8 req_type;
	356
	357	struct qm_dma qdma;
	358	void *sqe;
	359	struct qm_cqe *cqe;
	360	dma_addr_t sqe_dma;
	361	dma_addr_t cqe_dma;
	362
	363	struct hisi_qp_status qp_status;
	364	struct hisi_qp_ops *hw_ops;
	365	void *qp_ctx;
	366	void (req_cb)(struct hisi_qp qp, void *data);
9e00df71	367	void (event_cb)(struct hisi_qp qp);
263c9959 ZW	368
263c9959 ZW	369	struct hisi_qm *qm;
b67202e8	370	bool is_resetting;
cc3292d1	371	bool is_in_kernel;
9e00df71 ZG	372	u16 pasid;
9e00df71 ZG	373	struct uacce_queue *uacce_q;
263c9959 ZW	374	};
263c9959 ZW	375
20b291f5 ST	376	static inline int q_num_set(const char val, const struct kernel_param kp,
	377	unsigned int device)
	378	{
	379	struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI,
	380	device, NULL);
	381	u32 n, q_num;
20b291f5 ST	382	int ret;
	383
	384	if (!val)
	385	return -EINVAL;
	386
	387	if (!pdev) {
	388	q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
4cf0806e	389	pr_info("No device found currently, suppose queue number is %u\n",
20b291f5 ST	390	q_num);
20b291f5 ST	391	} else {
58ca0060	392	if (pdev->revision == QM_HW_V1)
20b291f5	393	q_num = QM_QNUM_V1;
58ca0060	394	else
20b291f5	395	q_num = QM_QNUM_V2;
20b291f5 ST	396	}
	397
	398	ret = kstrtou32(val, 10, &n);
c4f8f62f	399	if (ret \|\| n < QM_MIN_QNUM \|\| n > q_num)
20b291f5 ST	400	return -EINVAL;
	401
	402	return param_set_int(val, kp);
	403	}
	404
35ee280f HF	405	static inline int vfs_num_set(const char val, const struct kernel_param kp)
	406	{
	407	u32 n;
	408	int ret;
	409
	410	if (!val)
	411	return -EINVAL;
	412
	413	ret = kstrtou32(val, 10, &n);
	414	if (ret < 0)
	415	return ret;
	416
	417	if (n > QM_MAX_VFS_NUM_V2)
	418	return -EINVAL;
	419
	420	return param_set_int(val, kp);
	421	}
	422
f8408d2b KY	423	static inline int mode_set(const char val, const struct kernel_param kp)
	424	{
	425	u32 n;
	426	int ret;
	427
	428	if (!val)
	429	return -EINVAL;
	430
	431	ret = kstrtou32(val, 10, &n);
	432	if (ret != 0 \|\| (n != UACCE_MODE_SVA &&
	433	n != UACCE_MODE_NOUACCE))
	434	return -EINVAL;
	435
	436	return param_set_int(val, kp);
	437	}
	438
	439	static inline int uacce_mode_set(const char val, const struct kernel_param kp)
	440	{
	441	return mode_set(val, kp);
	442	}
	443
3f1ec97a WQ	444	static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
	445	{
	446	INIT_LIST_HEAD(&qm_list->list);
	447	mutex_init(&qm_list->lock);
	448	}
	449
263c9959 ZW	450	int hisi_qm_init(struct hisi_qm *qm);
	451	void hisi_qm_uninit(struct hisi_qm *qm);
	452	int hisi_qm_start(struct hisi_qm *qm);
e88dd6e1	453	int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
263c9959 ZW	454	int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
263c9959 ZW	455	int hisi_qm_stop_qp(struct hisi_qp *qp);
263c9959	456	int hisi_qp_send(struct hisi_qp qp, const void msg);
a8ff38bd	457	void hisi_qm_debug_init(struct hisi_qm *qm);
72c7a68d	458	void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
cd1b7ae3	459	int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
daa31783	460	int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
cd1b7ae3	461	int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
eaebf4c3 ST	462	void hisi_qm_dev_err_init(struct hisi_qm *qm);
eaebf4c3 ST	463	void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
f1724d39 KY	464	int hisi_qm_diff_regs_init(struct hisi_qm *qm,
	465	struct dfx_diff_registers *dregs, int reg_len);
	466	void hisi_qm_diff_regs_uninit(struct hisi_qm *qm, int reg_len);
	467	void hisi_qm_acc_diff_regs_dump(struct hisi_qm qm, struct seq_file s,
	468	struct dfx_diff_registers *dregs, int regs_len);
	469
f826e6ef ST	470	pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
f826e6ef ST	471	pci_channel_state_t state);
6c6dd580	472	pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
7ce396fa ST	473	void hisi_qm_reset_prepare(struct pci_dev *pdev);
7ce396fa ST	474	void hisi_qm_reset_done(struct pci_dev *pdev);
48c1cd40	475
b4b084d7 LL	476	int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
	477	int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
	478	bool op);
	479
48c1cd40 ZW	480	struct hisi_acc_sgl_pool;
	481	struct hisi_acc_hw_sgl hisi_acc_sg_buf_map_to_hw_sgl(struct device dev,
	482	struct scatterlist sgl, struct hisi_acc_sgl_pool pool,
	483	u32 index, dma_addr_t *hw_sgl_dma);
	484	void hisi_acc_sg_buf_unmap(struct device dev, struct scatterlist sgl,
	485	struct hisi_acc_hw_sgl *hw_sgl);
	486	struct hisi_acc_sgl_pool hisi_acc_create_sgl_pool(struct device dev,
	487	u32 count, u32 sge_nr);
	488	void hisi_acc_free_sgl_pool(struct device *dev,
	489	struct hisi_acc_sgl_pool *pool);
3f1ec97a WQ	490	int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
	491	u8 alg_type, int node, struct hisi_qp **qps);
	492	void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
64dfe495	493	void hisi_qm_dev_shutdown(struct pci_dev *pdev);
daa31783	494	void hisi_qm_wait_task_finish(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	495	int hisi_qm_alg_register(struct hisi_qm qm, struct hisi_qm_list qm_list);
3d29e98d YS	496	void hisi_qm_alg_unregister(struct hisi_qm qm, struct hisi_qm_list qm_list);
d7ea5339 WQ	497	int hisi_qm_resume(struct device *dev);
d7ea5339 WQ	498	int hisi_qm_suspend(struct device *dev);
607c191b WQ	499	void hisi_qm_pm_uninit(struct hisi_qm *qm);
	500	void hisi_qm_pm_init(struct hisi_qm *qm);
	501	int hisi_qm_get_dfx_access(struct hisi_qm *qm);
	502	void hisi_qm_put_dfx_access(struct hisi_qm *qm);
1295292d	503	void hisi_qm_regs_dump(struct seq_file s, struct debugfs_regset32 regset);
442fbc09 SK	504
	505	/* Used by VFIO ACC live migration driver */
	506	struct pci_driver *hisi_sec_get_pf_driver(void);
	507	struct pci_driver *hisi_hpre_get_pf_driver(void);
	508	struct pci_driver *hisi_zip_get_pf_driver(void);
263c9959	509	#endif