[linux-block.git] / include / linux / gpio / driver.h

#ifndef __LINUX_GPIO_DRIVER_H
#define __LINUX_GPIO_DRIVER_H

#include <linux/device.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>

struct gpio_desc;
struct of_phandle_args;
struct device_node;
struct seq_file;
struct gpio_device;
struct module;

#ifdef CONFIG_GPIOLIB

#ifdef CONFIG_GPIOLIB_IRQCHIP
/**
 * struct gpio_irq_chip - GPIO interrupt controller
 */
struct gpio_irq_chip {
	/**
	 * @chip:
	 *
	 * GPIO IRQ chip implementation, provided by GPIO driver.
	 */
	struct irq_chip *chip;

	/**
	 * @domain:
	 *
	 * Interrupt translation domain; responsible for mapping between GPIO
	 * hwirq number and Linux IRQ number.
	 */
	struct irq_domain *domain;

	/**
	 * @domain_ops:
	 *
	 * Table of interrupt domain operations for this IRQ chip.
	 */
	const struct irq_domain_ops *domain_ops;

	/**
	 * @handler:
	 *
	 * The IRQ handler to use (often a predefined IRQ core function) for
	 * GPIO IRQs, provided by GPIO driver.
	 */
	irq_flow_handler_t handler;

	/**
	 * @default_type:
	 *
	 * Default IRQ triggering type applied during GPIO driver
	 * initialization, provided by GPIO driver.
	 */
	unsigned int default_type;

	/**
	 * @parent_handler:
	 *
	 * The interrupt handler for the GPIO chip's parent interrupts, may be
	 * NULL if the parent interrupts are nested rather than cascaded.
	 */
	irq_flow_handler_t parent_handler;

	/**
	 * @parent_handler_data:
	 *
	 * Data associated, and passed to, the handler for the parent
	 * interrupt.
	 */
	void *parent_handler_data;

	/**
	 * @num_parents:
	 *
	 * The number of interrupt parents of a GPIO chip.
	 */
	unsigned int num_parents;

	/**
	 * @parents:
	 *
	 * A list of interrupt parents of a GPIO chip. This is owned by the
	 * driver, so the core will only reference this list, not modify it.
	 */
	unsigned int *parents;

	/**
	 * @nested:
	 *
	 * True if set the interrupt handling is nested.
	 */
	bool nested;

	/**
	 * @need_valid_mask:
	 *
	 * If set core allocates @valid_mask with all bits set to one.
	 */
	bool need_valid_mask;

	/**
	 * @valid_mask:
	 *
	 * If not %NULL holds bitmask of GPIOs which are valid to be included
	 * in IRQ domain of the chip.
	 */
	unsigned long *valid_mask;
};

static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
{
	return container_of(chip, struct gpio_irq_chip, chip);
}
#endif

/**
 * struct gpio_chip - abstract a GPIO controller
 * @label: a functional name for the GPIO device, such as a part
 *	number or the name of the SoC IP-block implementing it.
 * @gpiodev: the internal state holder, opaque struct
 * @parent: optional parent device providing the GPIOs
 * @owner: helps prevent removal of modules exporting active GPIOs
 * @request: optional hook for chip-specific activation, such as
 *	enabling module power and clock; may sleep
 * @free: optional hook for chip-specific deactivation, such as
 *	disabling module power and clock; may sleep
 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 *	(same as GPIOF_DIR_XXX), or negative error
 * @direction_input: configures signal "offset" as input, or returns error
 * @direction_output: configures signal "offset" as output, or returns error
 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 * @get_multiple: reads values for multiple signals defined by "mask" and
 *	stores them in "bits", returns 0 on success or negative error
 * @set: assigns output value for signal "offset"
 * @set_multiple: assigns output values for multiple signals defined by "mask"
 * @set_config: optional hook for all kinds of settings. Uses the same
 *	packed config format as generic pinconf.
 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 *	implementation may not sleep
 * @dbg_show: optional routine to show contents in debugfs; default code
 *	will be used when this is omitted, but custom code can show extra
 *	state (such as pullup/pulldown configuration).
 * @base: identifies the first GPIO number handled by this chip;
 *	or, if negative during registration, requests dynamic ID allocation.
 *	DEPRECATION: providing anything non-negative and nailing the base
 *	offset of GPIO chips is deprecated. Please pass -1 as base to
 *	let gpiolib select the chip base in all possible cases. We want to
 *	get rid of the static GPIO number space in the long run.
 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 *	handled is (base + ngpio - 1).
 * @names: if set, must be an array of strings to use as alternative
 *      names for the GPIOs in this chip. Any entry in the array
 *      may be NULL if there is no alias for the GPIO, however the
 *      array must be @ngpio entries long.  A name can include a single printk
 *      format specifier for an unsigned int.  It is substituted by the actual
 *      number of the gpio.
 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 *	must while accessing GPIO expander chips over I2C or SPI. This
 *	implies that if the chip supports IRQs, these IRQs need to be threaded
 *	as the chip access may sleep when e.g. reading out the IRQ status
 *	registers.
 * @read_reg: reader function for generic GPIO
 * @write_reg: writer function for generic GPIO
 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
 *	line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
 *	generic GPIO core. It is for internal housekeeping only.
 * @reg_dat: data (in) register for generic GPIO
 * @reg_set: output set register (out=high) for generic GPIO
 * @reg_clr: output clear register (out=low) for generic GPIO
 * @reg_dir: direction setting register for generic GPIO
 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 *	<register width> * 8
 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 *	shadowed and real data registers writes together.
 * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
 *	safely.
 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 *	direction safely.
 * @lock_key: per GPIO IRQ chip lockdep class
 *
 * A gpio_chip can help platforms abstract various sources of GPIOs so
 * they can all be accessed through a common programing interface.
 * Example sources would be SOC controllers, FPGAs, multifunction
 * chips, dedicated GPIO expanders, and so on.
 *
 * Each chip controls a number of signals, identified in method calls
 * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 * are referenced through calls like gpio_get_value(gpio), the offset
 * is calculated by subtracting @base from the gpio number.
 */
struct gpio_chip {
	const char		*label;
	struct gpio_device	*gpiodev;
	struct device		*parent;
	struct module		*owner;

	int			(*request)(struct gpio_chip *chip,
						unsigned offset);
	void			(*free)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_direction)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_input)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_output)(struct gpio_chip *chip,
						unsigned offset, int value);
	int			(*get)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	void			(*set)(struct gpio_chip *chip,
						unsigned offset, int value);
	void			(*set_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	int			(*set_config)(struct gpio_chip *chip,
					      unsigned offset,
					      unsigned long config);
	int			(*to_irq)(struct gpio_chip *chip,
						unsigned offset);

	void			(*dbg_show)(struct seq_file *s,
						struct gpio_chip *chip);
	int			base;
	u16			ngpio;
	const char		*const *names;
	bool			can_sleep;

#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	unsigned long (*read_reg)(void __iomem *reg);
	void (*write_reg)(void __iomem *reg, unsigned long data);
	bool be_bits;
	void __iomem *reg_dat;
	void __iomem *reg_set;
	void __iomem *reg_clr;
	void __iomem *reg_dir;
	int bgpio_bits;
	spinlock_t bgpio_lock;
	unsigned long bgpio_data;
	unsigned long bgpio_dir;
#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP
	/*
	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
	 * to handle IRQs for most practical cases.
	 */
	struct lock_class_key	*lock_key;

	/**
	 * @irq:
	 *
	 * Integrates interrupt chip functionality with the GPIO chip. Can be
	 * used to handle IRQs for most practical cases.
	 */
	struct gpio_irq_chip irq;
#endif

#if defined(CONFIG_OF_GPIO)
	/*
	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
	 * device tree automatically may have an OF translation
	 */

	/**
	 * @of_node:
	 *
	 * Pointer to a device tree node representing this GPIO controller.
	 */
	struct device_node *of_node;

	/**
	 * @of_gpio_n_cells:
	 *
	 * Number of cells used to form the GPIO specifier.
	 */
	unsigned int of_gpio_n_cells;

	/**
	 * @of_xlate:
	 *
	 * Callback to translate a device tree GPIO specifier into a chip-
	 * relative GPIO number and flags.
	 */
	int (*of_xlate)(struct gpio_chip *gc,
			const struct of_phandle_args *gpiospec, u32 *flags);
#endif
};

extern const char *gpiochip_is_requested(struct gpio_chip *chip,
			unsigned offset);

/* add/remove chips */
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
static inline int gpiochip_add(struct gpio_chip *chip)
{
	return gpiochip_add_data(chip, NULL);
}
extern void gpiochip_remove(struct gpio_chip *chip);
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
				  void *data);
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);

extern struct gpio_chip *gpiochip_find(void *data,
			      int (*match)(struct gpio_chip *chip, void *data));

/* lock/unlock as IRQ */
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);

/* Line status inquiry for drivers */
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);

/* Sleep persistence inquiry for drivers */
bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);

/* get driver data */
void *gpiochip_get_data(struct gpio_chip *chip);

struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);

struct bgpio_pdata {
	const char *label;
	int base;
	int ngpio;
};

#if IS_ENABLED(CONFIG_GPIO_GENERIC)

int bgpio_init(struct gpio_chip *gc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags);

#define BGPIOF_BIG_ENDIAN		BIT(0)
#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */

#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP

void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq,
		irq_flow_handler_t parent_handler);

void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq);

int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
			     struct irq_chip *irqchip,
			     unsigned int first_irq,
			     irq_flow_handler_t handler,
			     unsigned int type,
			     bool nested,
			     struct lock_class_key *lock_key);

#ifdef CONFIG_LOCKDEP

/*
 * Lockdep requires that each irqchip instance be created with a
 * unique key so as to avoid unnecessary warnings. This upfront
 * boilerplate static inlines provides such a key for each
 * unique instance.
 */
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, &key);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{

	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, &key);
}
#else
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, NULL);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, NULL);
}
#endif /* CONFIG_LOCKDEP */

#endif /* CONFIG_GPIOLIB_IRQCHIP */

int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
			    unsigned long config);

#ifdef CONFIG_PINCTRL

/**
 * struct gpio_pin_range - pin range controlled by a gpio chip
 * @node: list for maintaining set of pin ranges, used internally
 * @pctldev: pinctrl device which handles corresponding pins
 * @range: actual range of pins controlled by a gpio controller
 */
struct gpio_pin_range {
	struct list_head node;
	struct pinctrl_dev *pctldev;
	struct pinctrl_gpio_range range;
};

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
			   unsigned int gpio_offset, unsigned int pin_offset,
			   unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);

#else

static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
		       unsigned int gpio_offset, unsigned int pin_offset,
		       unsigned int npins)
{
	return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group)
{
	return 0;
}

static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
}

#endif /* CONFIG_PINCTRL */

struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
					    const char *label);
void gpiochip_free_own_desc(struct gpio_desc *desc);

#else /* CONFIG_GPIOLIB */

static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
{
	/* GPIO can never have been requested */
	WARN_ON(1);
	return ERR_PTR(-ENODEV);
}

#endif /* CONFIG_GPIOLIB */

#endif
Commit	Line	Data
79a9becd AC	1	#ifndef __LINUX_GPIO_DRIVER_H
	2	#define __LINUX_GPIO_DRIVER_H
	3
ff2b1359	4	#include <linux/device.h>
79a9becd	5	#include <linux/types.h>
14250520 LW	6	#include <linux/irq.h>
	7	#include <linux/irqchip/chained_irq.h>
	8	#include <linux/irqdomain.h>
a0a8bcf4	9	#include <linux/lockdep.h>
964cb341	10	#include <linux/pinctrl/pinctrl.h>
2956b5d9	11	#include <linux/pinctrl/pinconf-generic.h>
79a9becd	12
79a9becd	13	struct gpio_desc;
c9a9972b AC	14	struct of_phandle_args;
c9a9972b AC	15	struct device_node;
f3ed0b66	16	struct seq_file;
ff2b1359	17	struct gpio_device;
d47529b2	18	struct module;
79a9becd	19
bb1e88cc AC	20	#ifdef CONFIG_GPIOLIB
bb1e88cc AC	21
c44eafd7 TR	22	#ifdef CONFIG_GPIOLIB_IRQCHIP
	23	/**
	24	* struct gpio_irq_chip - GPIO interrupt controller
	25	*/
	26	struct gpio_irq_chip {
da80ff81 TR	27	/**
	28	* @chip:
	29	*
	30	* GPIO IRQ chip implementation, provided by GPIO driver.
	31	*/
	32	struct irq_chip *chip;
	33
f0fbe7bc TR	34	/**
	35	* @domain:
	36	*
	37	* Interrupt translation domain; responsible for mapping between GPIO
	38	* hwirq number and Linux IRQ number.
	39	*/
	40	struct irq_domain *domain;
	41
c44eafd7 TR	42	/**
	43	* @domain_ops:
	44	*
	45	* Table of interrupt domain operations for this IRQ chip.
	46	*/
	47	const struct irq_domain_ops *domain_ops;
	48
c7a0aa59 TR	49	/**
	50	* @handler:
	51	*
	52	* The IRQ handler to use (often a predefined IRQ core function) for
	53	* GPIO IRQs, provided by GPIO driver.
	54	*/
	55	irq_flow_handler_t handler;
	56
3634eeb0 TR	57	/**
	58	* @default_type:
	59	*
	60	* Default IRQ triggering type applied during GPIO driver
	61	* initialization, provided by GPIO driver.
	62	*/
	63	unsigned int default_type;
	64
c44eafd7 TR	65	/**
	66	* @parent_handler:
	67	*
	68	* The interrupt handler for the GPIO chip's parent interrupts, may be
	69	* NULL if the parent interrupts are nested rather than cascaded.
	70	*/
	71	irq_flow_handler_t parent_handler;
	72
	73	/**
	74	* @parent_handler_data:
	75	*
	76	* Data associated, and passed to, the handler for the parent
	77	* interrupt.
	78	*/
	79	void *parent_handler_data;
39e5f096 TR	80
	81	/**
	82	* @num_parents:
	83	*
	84	* The number of interrupt parents of a GPIO chip.
	85	*/
	86	unsigned int num_parents;
	87
	88	/**
	89	* @parents:
	90	*
	91	* A list of interrupt parents of a GPIO chip. This is owned by the
	92	* driver, so the core will only reference this list, not modify it.
	93	*/
	94	unsigned int *parents;
dc6bafee TR	95
	96	/**
	97	* @nested:
	98	*
	99	* True if set the interrupt handling is nested.
	100	*/
	101	bool nested;
dc7b0387 TR	102
	103	/**
	104	* @need_valid_mask:
	105	*
	106	* If set core allocates @valid_mask with all bits set to one.
	107	*/
	108	bool need_valid_mask;
	109
	110	/**
	111	* @valid_mask:
	112	*
	113	* If not %NULL holds bitmask of GPIOs which are valid to be included
	114	* in IRQ domain of the chip.
	115	*/
	116	unsigned long *valid_mask;
c44eafd7	117	};
da80ff81 TR	118
	119	static inline struct gpio_irq_chip to_gpio_irq_chip(struct irq_chip chip)
	120	{
	121	return container_of(chip, struct gpio_irq_chip, chip);
	122	}
c44eafd7 TR	123	#endif
c44eafd7 TR	124
79a9becd AC	125	/**
79a9becd AC	126	* struct gpio_chip - abstract a GPIO controller
df4878e9 LW	127	* @label: a functional name for the GPIO device, such as a part
df4878e9 LW	128	* number or the name of the SoC IP-block implementing it.
ff2b1359	129	* @gpiodev: the internal state holder, opaque struct
58383c78	130	* @parent: optional parent device providing the GPIOs
79a9becd	131	* @owner: helps prevent removal of modules exporting active GPIOs
79a9becd AC	132	* @request: optional hook for chip-specific activation, such as
	133	* enabling module power and clock; may sleep
	134	* @free: optional hook for chip-specific deactivation, such as
	135	* disabling module power and clock; may sleep
	136	* @get_direction: returns direction for signal "offset", 0=out, 1=in,
	137	* (same as GPIOF_DIR_XXX), or negative error
	138	* @direction_input: configures signal "offset" as input, or returns error
	139	* @direction_output: configures signal "offset" as output, or returns error
60befd2e	140	* @get: returns value for signal "offset", 0=low, 1=high, or negative error
eec1d566 LW	141	* @get_multiple: reads values for multiple signals defined by "mask" and
eec1d566 LW	142	* stores them in "bits", returns 0 on success or negative error
79a9becd	143	* @set: assigns output value for signal "offset"
5f424243	144	* @set_multiple: assigns output values for multiple signals defined by "mask"
2956b5d9 MW	145	* @set_config: optional hook for all kinds of settings. Uses the same
2956b5d9 MW	146	* packed config format as generic pinconf.
79a9becd AC	147	* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
	148	* implementation may not sleep
	149	* @dbg_show: optional routine to show contents in debugfs; default code
	150	* will be used when this is omitted, but custom code can show extra
	151	* state (such as pullup/pulldown configuration).
af6c235d LW	152	* @base: identifies the first GPIO number handled by this chip;
	153	* or, if negative during registration, requests dynamic ID allocation.
	154	* DEPRECATION: providing anything non-negative and nailing the base
30bb6fb3	155	* offset of GPIO chips is deprecated. Please pass -1 as base to
af6c235d LW	156	* let gpiolib select the chip base in all possible cases. We want to
af6c235d LW	157	* get rid of the static GPIO number space in the long run.
79a9becd AC	158	* @ngpio: the number of GPIOs handled by this controller; the last GPIO
79a9becd AC	159	* handled is (base + ngpio - 1).
79a9becd AC	160	* @names: if set, must be an array of strings to use as alternative
	161	* names for the GPIOs in this chip. Any entry in the array
	162	* may be NULL if there is no alias for the GPIO, however the
	163	* array must be @ngpio entries long. A name can include a single printk
	164	* format specifier for an unsigned int. It is substituted by the actual
	165	* number of the gpio.
9fb1f39e	166	* @can_sleep: flag must be set iff get()/set() methods sleep, as they
1c8732bb LW	167	* must while accessing GPIO expander chips over I2C or SPI. This
	168	* implies that if the chip supports IRQs, these IRQs need to be threaded
	169	* as the chip access may sleep when e.g. reading out the IRQ status
	170	* registers.
0f4630f3 LW	171	* @read_reg: reader function for generic GPIO
0f4630f3 LW	172	* @write_reg: writer function for generic GPIO
24efd94b LW	173	* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
	174	* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
	175	* generic GPIO core. It is for internal housekeeping only.
0f4630f3 LW	176	* @reg_dat: data (in) register for generic GPIO
0f4630f3 LW	177	* @reg_set: output set register (out=high) for generic GPIO
08bcd3ed	178	* @reg_clr: output clear register (out=low) for generic GPIO
0f4630f3 LW	179	* @reg_dir: direction setting register for generic GPIO
	180	* @bgpio_bits: number of register bits used for a generic GPIO i.e.
	181	* <register width> * 8
	182	* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
	183	* shadowed and real data registers writes together.
	184	* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
	185	* safely.
	186	* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
	187	* direction safely.
41d6bb4c	188	* @lock_key: per GPIO IRQ chip lockdep class
79a9becd AC	189	*
	190	* A gpio_chip can help platforms abstract various sources of GPIOs so
	191	* they can all be accessed through a common programing interface.
	192	* Example sources would be SOC controllers, FPGAs, multifunction
	193	* chips, dedicated GPIO expanders, and so on.
	194	*
	195	* Each chip controls a number of signals, identified in method calls
	196	* by "offset" values in the range 0..(@ngpio - 1). When those signals
	197	* are referenced through calls like gpio_get_value(gpio), the offset
	198	* is calculated by subtracting @base from the gpio number.
	199	*/
	200	struct gpio_chip {
	201	const char *label;
ff2b1359	202	struct gpio_device *gpiodev;
58383c78	203	struct device *parent;
79a9becd	204	struct module *owner;
79a9becd AC	205
	206	int (request)(struct gpio_chip chip,
	207	unsigned offset);
	208	void (free)(struct gpio_chip chip,
	209	unsigned offset);
	210	int (get_direction)(struct gpio_chip chip,
	211	unsigned offset);
	212	int (direction_input)(struct gpio_chip chip,
	213	unsigned offset);
	214	int (direction_output)(struct gpio_chip chip,
	215	unsigned offset, int value);
	216	int (get)(struct gpio_chip chip,
	217	unsigned offset);
eec1d566 LW	218	int (get_multiple)(struct gpio_chip chip,
	219	unsigned long *mask,
	220	unsigned long *bits);
79a9becd AC	221	void (set)(struct gpio_chip chip,
79a9becd AC	222	unsigned offset, int value);
5f424243 RI	223	void (set_multiple)(struct gpio_chip chip,
	224	unsigned long *mask,
	225	unsigned long *bits);
2956b5d9 MW	226	int (set_config)(struct gpio_chip chip,
	227	unsigned offset,
	228	unsigned long config);
79a9becd AC	229	int (to_irq)(struct gpio_chip chip,
	230	unsigned offset);
	231
	232	void (dbg_show)(struct seq_file s,
	233	struct gpio_chip *chip);
	234	int base;
	235	u16 ngpio;
79a9becd	236	const char const names;
9fb1f39e	237	bool can_sleep;
79a9becd	238
0f4630f3 LW	239	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	240	unsigned long (read_reg)(void __iomem reg);
	241	void (write_reg)(void __iomem reg, unsigned long data);
24efd94b	242	bool be_bits;
0f4630f3 LW	243	void __iomem *reg_dat;
	244	void __iomem *reg_set;
	245	void __iomem *reg_clr;
	246	void __iomem *reg_dir;
	247	int bgpio_bits;
	248	spinlock_t bgpio_lock;
	249	unsigned long bgpio_data;
	250	unsigned long bgpio_dir;
	251	#endif
	252
14250520 LW	253	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	254	/*
7d75a871	255	* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
14250520 LW	256	* to handle IRQs for most practical cases.
14250520 LW	257	*/
a0a8bcf4	258	struct lock_class_key *lock_key;
c44eafd7 TR	259
	260	/**
	261	* @irq:
	262	*
	263	* Integrates interrupt chip functionality with the GPIO chip. Can be
	264	* used to handle IRQs for most practical cases.
	265	*/
	266	struct gpio_irq_chip irq;
14250520 LW	267	#endif
14250520 LW	268
79a9becd AC	269	#if defined(CONFIG_OF_GPIO)
	270	/*
	271	* If CONFIG_OF is enabled, then all GPIO controllers described in the
	272	* device tree automatically may have an OF translation
	273	*/
67049c50 TR	274
	275	/**
	276	* @of_node:
	277	*
	278	* Pointer to a device tree node representing this GPIO controller.
	279	*/
79a9becd	280	struct device_node *of_node;
67049c50 TR	281
	282	/**
	283	* @of_gpio_n_cells:
	284	*
	285	* Number of cells used to form the GPIO specifier.
	286	*/
e3b445d7	287	unsigned int of_gpio_n_cells;
67049c50 TR	288
	289	/**
	290	* @of_xlate:
	291	*
	292	* Callback to translate a device tree GPIO specifier into a chip-
	293	* relative GPIO number and flags.
	294	*/
79a9becd AC	295	int (of_xlate)(struct gpio_chip gc,
	296	const struct of_phandle_args gpiospec, u32 flags);
	297	#endif
79a9becd AC	298	};
	299
	300	extern const char gpiochip_is_requested(struct gpio_chip chip,
	301	unsigned offset);
	302
	303	/* add/remove chips */
b08ea35a LW	304	extern int gpiochip_add_data(struct gpio_chip chip, void data);
	305	static inline int gpiochip_add(struct gpio_chip *chip)
	306	{
	307	return gpiochip_add_data(chip, NULL);
	308	}
e1db1706	309	extern void gpiochip_remove(struct gpio_chip *chip);
0cf3292c LD	310	extern int devm_gpiochip_add_data(struct device dev, struct gpio_chip chip,
	311	void *data);
	312	extern void devm_gpiochip_remove(struct device dev, struct gpio_chip chip);
	313
79a9becd AC	314	extern struct gpio_chip gpiochip_find(void data,
	315	int (match)(struct gpio_chip chip, void *data));
	316
	317	/* lock/unlock as IRQ */
e3a2e878 AC	318	int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
e3a2e878 AC	319	void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
6cee3821	320	bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
79a9becd	321
143b65d6 LW	322	/* Line status inquiry for drivers */
	323	bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
	324	bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
	325
05f479bf CK	326	/* Sleep persistence inquiry for drivers */
	327	bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
	328
b08ea35a	329	/* get driver data */
43c54eca	330	void gpiochip_get_data(struct gpio_chip chip);
b08ea35a	331
bb1e88cc AC	332	struct gpio_chip gpiod_to_chip(const struct gpio_desc desc);
bb1e88cc AC	333
0f4630f3 LW	334	struct bgpio_pdata {
	335	const char *label;
	336	int base;
	337	int ngpio;
	338	};
	339
c474e348 AB	340	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
c474e348 AB	341
0f4630f3 LW	342	int bgpio_init(struct gpio_chip gc, struct device dev,
	343	unsigned long sz, void __iomem dat, void __iomem set,
	344	void __iomem clr, void __iomem dirout, void __iomem *dirin,
	345	unsigned long flags);
	346
	347	#define BGPIOF_BIG_ENDIAN BIT(0)
	348	#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
	349	#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
	350	#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
	351	#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
	352	#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
	353
	354	#endif
	355
14250520 LW	356	#ifdef CONFIG_GPIOLIB_IRQCHIP
	357
	358	void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
	359	struct irq_chip *irqchip,
6f79309a	360	unsigned int parent_irq,
14250520 LW	361	irq_flow_handler_t parent_handler);
14250520 LW	362
d245b3f9 LW	363	void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
d245b3f9 LW	364	struct irq_chip *irqchip,
6f79309a	365	unsigned int parent_irq);
d245b3f9	366
739e6f59 LW	367	int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
	368	struct irq_chip *irqchip,
	369	unsigned int first_irq,
	370	irq_flow_handler_t handler,
	371	unsigned int type,
	372	bool nested,
	373	struct lock_class_key *lock_key);
	374
	375	#ifdef CONFIG_LOCKDEP
	376
	377	/*
	378	* Lockdep requires that each irqchip instance be created with a
	379	* unique key so as to avoid unnecessary warnings. This upfront
	380	* boilerplate static inlines provides such a key for each
	381	* unique instance.
	382	*/
	383	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	384	struct irq_chip *irqchip,
	385	unsigned int first_irq,
	386	irq_flow_handler_t handler,
	387	unsigned int type)
	388	{
	389	static struct lock_class_key key;
	390
	391	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	392	handler, type, false, &key);
	393	}
	394
	395	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
a0a8bcf4 GS	396	struct irq_chip *irqchip,
	397	unsigned int first_irq,
	398	irq_flow_handler_t handler,
739e6f59 LW	399	unsigned int type)
	400	{
	401
	402	static struct lock_class_key key;
	403
	404	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	405	handler, type, true, &key);
	406	}
	407	#else
	408	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	409	struct irq_chip *irqchip,
	410	unsigned int first_irq,
	411	irq_flow_handler_t handler,
	412	unsigned int type)
	413	{
	414	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	415	handler, type, false, NULL);
	416	}
a0a8bcf4	417
d245b3f9 LW	418	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
	419	struct irq_chip *irqchip,
	420	unsigned int first_irq,
	421	irq_flow_handler_t handler,
	422	unsigned int type)
	423	{
739e6f59 LW	424	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
739e6f59 LW	425	handler, type, true, NULL);
d245b3f9	426	}
739e6f59	427	#endif /* CONFIG_LOCKDEP */
14250520	428
7d75a871	429	#endif /* CONFIG_GPIOLIB_IRQCHIP */
14250520	430
c771c2f4 JG	431	int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
c771c2f4 JG	432	void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
2956b5d9 MW	433	int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	434	unsigned long config);
c771c2f4	435
964cb341 LW	436	#ifdef CONFIG_PINCTRL
	437
	438	/**
	439	* struct gpio_pin_range - pin range controlled by a gpio chip
950d55f5	440	* @node: list for maintaining set of pin ranges, used internally
964cb341 LW	441	* @pctldev: pinctrl device which handles corresponding pins
	442	* @range: actual range of pins controlled by a gpio controller
	443	*/
964cb341 LW	444	struct gpio_pin_range {
	445	struct list_head node;
	446	struct pinctrl_dev *pctldev;
	447	struct pinctrl_gpio_range range;
	448	};
	449
	450	int gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	451	unsigned int gpio_offset, unsigned int pin_offset,
	452	unsigned int npins);
	453	int gpiochip_add_pingroup_range(struct gpio_chip *chip,
	454	struct pinctrl_dev *pctldev,
	455	unsigned int gpio_offset, const char *pin_group);
	456	void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
	457
	458	#else
	459
	460	static inline int
	461	gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	462	unsigned int gpio_offset, unsigned int pin_offset,
	463	unsigned int npins)
	464	{
	465	return 0;
	466	}
	467	static inline int
	468	gpiochip_add_pingroup_range(struct gpio_chip *chip,
	469	struct pinctrl_dev *pctldev,
	470	unsigned int gpio_offset, const char *pin_group)
	471	{
	472	return 0;
	473	}
	474
	475	static inline void
	476	gpiochip_remove_pin_ranges(struct gpio_chip *chip)
	477	{
	478	}
	479
	480	#endif /* CONFIG_PINCTRL */
	481
abdc08a3 AC	482	struct gpio_desc gpiochip_request_own_desc(struct gpio_chip chip, u16 hwnum,
abdc08a3 AC	483	const char *label);
f7d4ad98 GR	484	void gpiochip_free_own_desc(struct gpio_desc *desc);
f7d4ad98 GR	485
bb1e88cc AC	486	#else /* CONFIG_GPIOLIB */
	487
	488	static inline struct gpio_chip gpiod_to_chip(const struct gpio_desc desc)
	489	{
	490	/* GPIO can never have been requested */
	491	WARN_ON(1);
	492	return ERR_PTR(-ENODEV);
	493	}
	494
	495	#endif /* CONFIG_GPIOLIB */
	496
79a9becd	497	#endif