[linux-block.git] / include / linux / gpio / driver.h

#ifndef __LINUX_GPIO_DRIVER_H
#define __LINUX_GPIO_DRIVER_H

#include <linux/device.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>

struct gpio_desc;
struct of_phandle_args;
struct device_node;
struct seq_file;
struct gpio_device;
struct module;

#ifdef CONFIG_GPIOLIB

#ifdef CONFIG_GPIOLIB_IRQCHIP
/**
 * struct gpio_irq_chip - GPIO interrupt controller
 */
struct gpio_irq_chip {
	/**
	 * @chip:
	 *
	 * GPIO IRQ chip implementation, provided by GPIO driver.
	 */
	struct irq_chip *chip;

	/**
	 * @domain:
	 *
	 * Interrupt translation domain; responsible for mapping between GPIO
	 * hwirq number and Linux IRQ number.
	 */
	struct irq_domain *domain;

	/**
	 * @domain_ops:
	 *
	 * Table of interrupt domain operations for this IRQ chip.
	 */
	const struct irq_domain_ops *domain_ops;

	/**
	 * @handler:
	 *
	 * The IRQ handler to use (often a predefined IRQ core function) for
	 * GPIO IRQs, provided by GPIO driver.
	 */
	irq_flow_handler_t handler;

	/**
	 * @default_type:
	 *
	 * Default IRQ triggering type applied during GPIO driver
	 * initialization, provided by GPIO driver.
	 */
	unsigned int default_type;

	/**
	 * @parent_handler:
	 *
	 * The interrupt handler for the GPIO chip's parent interrupts, may be
	 * NULL if the parent interrupts are nested rather than cascaded.
	 */
	irq_flow_handler_t parent_handler;

	/**
	 * @parent_handler_data:
	 *
	 * Data associated, and passed to, the handler for the parent
	 * interrupt.
	 */
	void *parent_handler_data;

	/**
	 * @num_parents:
	 *
	 * The number of interrupt parents of a GPIO chip.
	 */
	unsigned int num_parents;

	/**
	 * @parents:
	 *
	 * A list of interrupt parents of a GPIO chip. This is owned by the
	 * driver, so the core will only reference this list, not modify it.
	 */
	unsigned int *parents;
};

static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
{
	return container_of(chip, struct gpio_irq_chip, chip);
}
#endif

/**
 * struct gpio_chip - abstract a GPIO controller
 * @label: a functional name for the GPIO device, such as a part
 *	number or the name of the SoC IP-block implementing it.
 * @gpiodev: the internal state holder, opaque struct
 * @parent: optional parent device providing the GPIOs
 * @owner: helps prevent removal of modules exporting active GPIOs
 * @request: optional hook for chip-specific activation, such as
 *	enabling module power and clock; may sleep
 * @free: optional hook for chip-specific deactivation, such as
 *	disabling module power and clock; may sleep
 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 *	(same as GPIOF_DIR_XXX), or negative error
 * @direction_input: configures signal "offset" as input, or returns error
 * @direction_output: configures signal "offset" as output, or returns error
 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 * @get_multiple: reads values for multiple signals defined by "mask" and
 *	stores them in "bits", returns 0 on success or negative error
 * @set: assigns output value for signal "offset"
 * @set_multiple: assigns output values for multiple signals defined by "mask"
 * @set_config: optional hook for all kinds of settings. Uses the same
 *	packed config format as generic pinconf.
 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 *	implementation may not sleep
 * @dbg_show: optional routine to show contents in debugfs; default code
 *	will be used when this is omitted, but custom code can show extra
 *	state (such as pullup/pulldown configuration).
 * @base: identifies the first GPIO number handled by this chip;
 *	or, if negative during registration, requests dynamic ID allocation.
 *	DEPRECATION: providing anything non-negative and nailing the base
 *	offset of GPIO chips is deprecated. Please pass -1 as base to
 *	let gpiolib select the chip base in all possible cases. We want to
 *	get rid of the static GPIO number space in the long run.
 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 *	handled is (base + ngpio - 1).
 * @names: if set, must be an array of strings to use as alternative
 *      names for the GPIOs in this chip. Any entry in the array
 *      may be NULL if there is no alias for the GPIO, however the
 *      array must be @ngpio entries long.  A name can include a single printk
 *      format specifier for an unsigned int.  It is substituted by the actual
 *      number of the gpio.
 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 *	must while accessing GPIO expander chips over I2C or SPI. This
 *	implies that if the chip supports IRQs, these IRQs need to be threaded
 *	as the chip access may sleep when e.g. reading out the IRQ status
 *	registers.
 * @read_reg: reader function for generic GPIO
 * @write_reg: writer function for generic GPIO
 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
 *	line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
 *	generic GPIO core. It is for internal housekeeping only.
 * @reg_dat: data (in) register for generic GPIO
 * @reg_set: output set register (out=high) for generic GPIO
 * @reg_clr: output clear register (out=low) for generic GPIO
 * @reg_dir: direction setting register for generic GPIO
 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 *	<register width> * 8
 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 *	shadowed and real data registers writes together.
 * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
 *	safely.
 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 *	direction safely.
 * @irq_nested: True if set the interrupt handling is nested.
 * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
 *	bits set to one
 * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
 *	be included in IRQ domain of the chip
 * @lock_key: per GPIO IRQ chip lockdep class
 *
 * A gpio_chip can help platforms abstract various sources of GPIOs so
 * they can all be accessed through a common programing interface.
 * Example sources would be SOC controllers, FPGAs, multifunction
 * chips, dedicated GPIO expanders, and so on.
 *
 * Each chip controls a number of signals, identified in method calls
 * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 * are referenced through calls like gpio_get_value(gpio), the offset
 * is calculated by subtracting @base from the gpio number.
 */
struct gpio_chip {
	const char		*label;
	struct gpio_device	*gpiodev;
	struct device		*parent;
	struct module		*owner;

	int			(*request)(struct gpio_chip *chip,
						unsigned offset);
	void			(*free)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_direction)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_input)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_output)(struct gpio_chip *chip,
						unsigned offset, int value);
	int			(*get)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	void			(*set)(struct gpio_chip *chip,
						unsigned offset, int value);
	void			(*set_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	int			(*set_config)(struct gpio_chip *chip,
					      unsigned offset,
					      unsigned long config);
	int			(*to_irq)(struct gpio_chip *chip,
						unsigned offset);

	void			(*dbg_show)(struct seq_file *s,
						struct gpio_chip *chip);
	int			base;
	u16			ngpio;
	const char		*const *names;
	bool			can_sleep;

#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	unsigned long (*read_reg)(void __iomem *reg);
	void (*write_reg)(void __iomem *reg, unsigned long data);
	bool be_bits;
	void __iomem *reg_dat;
	void __iomem *reg_set;
	void __iomem *reg_clr;
	void __iomem *reg_dir;
	int bgpio_bits;
	spinlock_t bgpio_lock;
	unsigned long bgpio_data;
	unsigned long bgpio_dir;
#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP
	/*
	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
	 * to handle IRQs for most practical cases.
	 */
	bool			irq_nested;
	bool			irq_need_valid_mask;
	unsigned long		*irq_valid_mask;
	struct lock_class_key	*lock_key;

	/**
	 * @irq:
	 *
	 * Integrates interrupt chip functionality with the GPIO chip. Can be
	 * used to handle IRQs for most practical cases.
	 */
	struct gpio_irq_chip irq;
#endif

#if defined(CONFIG_OF_GPIO)
	/*
	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
	 * device tree automatically may have an OF translation
	 */

	/**
	 * @of_node:
	 *
	 * Pointer to a device tree node representing this GPIO controller.
	 */
	struct device_node *of_node;

	/**
	 * @of_gpio_n_cells:
	 *
	 * Number of cells used to form the GPIO specifier.
	 */
	unsigned int of_gpio_n_cells;

	/**
	 * @of_xlate:
	 *
	 * Callback to translate a device tree GPIO specifier into a chip-
	 * relative GPIO number and flags.
	 */
	int (*of_xlate)(struct gpio_chip *gc,
			const struct of_phandle_args *gpiospec, u32 *flags);
#endif
};

extern const char *gpiochip_is_requested(struct gpio_chip *chip,
			unsigned offset);

/* add/remove chips */
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
static inline int gpiochip_add(struct gpio_chip *chip)
{
	return gpiochip_add_data(chip, NULL);
}
extern void gpiochip_remove(struct gpio_chip *chip);
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
				  void *data);
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);

extern struct gpio_chip *gpiochip_find(void *data,
			      int (*match)(struct gpio_chip *chip, void *data));

/* lock/unlock as IRQ */
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);

/* Line status inquiry for drivers */
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);

/* Sleep persistence inquiry for drivers */
bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);

/* get driver data */
void *gpiochip_get_data(struct gpio_chip *chip);

struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);

struct bgpio_pdata {
	const char *label;
	int base;
	int ngpio;
};

#if IS_ENABLED(CONFIG_GPIO_GENERIC)

int bgpio_init(struct gpio_chip *gc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags);

#define BGPIOF_BIG_ENDIAN		BIT(0)
#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */

#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP

void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq,
		irq_flow_handler_t parent_handler);

void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq);

int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
			     struct irq_chip *irqchip,
			     unsigned int first_irq,
			     irq_flow_handler_t handler,
			     unsigned int type,
			     bool nested,
			     struct lock_class_key *lock_key);

#ifdef CONFIG_LOCKDEP

/*
 * Lockdep requires that each irqchip instance be created with a
 * unique key so as to avoid unnecessary warnings. This upfront
 * boilerplate static inlines provides such a key for each
 * unique instance.
 */
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, &key);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{

	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, &key);
}
#else
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, NULL);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, NULL);
}
#endif /* CONFIG_LOCKDEP */

#endif /* CONFIG_GPIOLIB_IRQCHIP */

int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
			    unsigned long config);

#ifdef CONFIG_PINCTRL

/**
 * struct gpio_pin_range - pin range controlled by a gpio chip
 * @node: list for maintaining set of pin ranges, used internally
 * @pctldev: pinctrl device which handles corresponding pins
 * @range: actual range of pins controlled by a gpio controller
 */
struct gpio_pin_range {
	struct list_head node;
	struct pinctrl_dev *pctldev;
	struct pinctrl_gpio_range range;
};

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
			   unsigned int gpio_offset, unsigned int pin_offset,
			   unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);

#else

static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
		       unsigned int gpio_offset, unsigned int pin_offset,
		       unsigned int npins)
{
	return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group)
{
	return 0;
}

static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
}

#endif /* CONFIG_PINCTRL */

struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
					    const char *label);
void gpiochip_free_own_desc(struct gpio_desc *desc);

#else /* CONFIG_GPIOLIB */

static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
{
	/* GPIO can never have been requested */
	WARN_ON(1);
	return ERR_PTR(-ENODEV);
}

#endif /* CONFIG_GPIOLIB */

#endif
Commit	Line	Data
79a9becd AC	1	#ifndef __LINUX_GPIO_DRIVER_H
	2	#define __LINUX_GPIO_DRIVER_H
	3
ff2b1359	4	#include <linux/device.h>
79a9becd	5	#include <linux/types.h>
14250520 LW	6	#include <linux/irq.h>
	7	#include <linux/irqchip/chained_irq.h>
	8	#include <linux/irqdomain.h>
a0a8bcf4	9	#include <linux/lockdep.h>
964cb341	10	#include <linux/pinctrl/pinctrl.h>
2956b5d9	11	#include <linux/pinctrl/pinconf-generic.h>
79a9becd	12
79a9becd	13	struct gpio_desc;
c9a9972b AC	14	struct of_phandle_args;
c9a9972b AC	15	struct device_node;
f3ed0b66	16	struct seq_file;
ff2b1359	17	struct gpio_device;
d47529b2	18	struct module;
79a9becd	19
bb1e88cc AC	20	#ifdef CONFIG_GPIOLIB
bb1e88cc AC	21
c44eafd7 TR	22	#ifdef CONFIG_GPIOLIB_IRQCHIP
	23	/**
	24	* struct gpio_irq_chip - GPIO interrupt controller
	25	*/
	26	struct gpio_irq_chip {
da80ff81 TR	27	/**
	28	* @chip:
	29	*
	30	* GPIO IRQ chip implementation, provided by GPIO driver.
	31	*/
	32	struct irq_chip *chip;
	33
f0fbe7bc TR	34	/**
	35	* @domain:
	36	*
	37	* Interrupt translation domain; responsible for mapping between GPIO
	38	* hwirq number and Linux IRQ number.
	39	*/
	40	struct irq_domain *domain;
	41
c44eafd7 TR	42	/**
	43	* @domain_ops:
	44	*
	45	* Table of interrupt domain operations for this IRQ chip.
	46	*/
	47	const struct irq_domain_ops *domain_ops;
	48
c7a0aa59 TR	49	/**
	50	* @handler:
	51	*
	52	* The IRQ handler to use (often a predefined IRQ core function) for
	53	* GPIO IRQs, provided by GPIO driver.
	54	*/
	55	irq_flow_handler_t handler;
	56
3634eeb0 TR	57	/**
	58	* @default_type:
	59	*
	60	* Default IRQ triggering type applied during GPIO driver
	61	* initialization, provided by GPIO driver.
	62	*/
	63	unsigned int default_type;
	64
c44eafd7 TR	65	/**
	66	* @parent_handler:
	67	*
	68	* The interrupt handler for the GPIO chip's parent interrupts, may be
	69	* NULL if the parent interrupts are nested rather than cascaded.
	70	*/
	71	irq_flow_handler_t parent_handler;
	72
	73	/**
	74	* @parent_handler_data:
	75	*
	76	* Data associated, and passed to, the handler for the parent
	77	* interrupt.
	78	*/
	79	void *parent_handler_data;
39e5f096 TR	80
	81	/**
	82	* @num_parents:
	83	*
	84	* The number of interrupt parents of a GPIO chip.
	85	*/
	86	unsigned int num_parents;
	87
	88	/**
	89	* @parents:
	90	*
	91	* A list of interrupt parents of a GPIO chip. This is owned by the
	92	* driver, so the core will only reference this list, not modify it.
	93	*/
	94	unsigned int *parents;
c44eafd7	95	};
da80ff81 TR	96
	97	static inline struct gpio_irq_chip to_gpio_irq_chip(struct irq_chip chip)
	98	{
	99	return container_of(chip, struct gpio_irq_chip, chip);
	100	}
c44eafd7 TR	101	#endif
c44eafd7 TR	102
79a9becd AC	103	/**
79a9becd AC	104	* struct gpio_chip - abstract a GPIO controller
df4878e9 LW	105	* @label: a functional name for the GPIO device, such as a part
df4878e9 LW	106	* number or the name of the SoC IP-block implementing it.
ff2b1359	107	* @gpiodev: the internal state holder, opaque struct
58383c78	108	* @parent: optional parent device providing the GPIOs
79a9becd	109	* @owner: helps prevent removal of modules exporting active GPIOs
79a9becd AC	110	* @request: optional hook for chip-specific activation, such as
	111	* enabling module power and clock; may sleep
	112	* @free: optional hook for chip-specific deactivation, such as
	113	* disabling module power and clock; may sleep
	114	* @get_direction: returns direction for signal "offset", 0=out, 1=in,
	115	* (same as GPIOF_DIR_XXX), or negative error
	116	* @direction_input: configures signal "offset" as input, or returns error
	117	* @direction_output: configures signal "offset" as output, or returns error
60befd2e	118	* @get: returns value for signal "offset", 0=low, 1=high, or negative error
eec1d566 LW	119	* @get_multiple: reads values for multiple signals defined by "mask" and
eec1d566 LW	120	* stores them in "bits", returns 0 on success or negative error
79a9becd	121	* @set: assigns output value for signal "offset"
5f424243	122	* @set_multiple: assigns output values for multiple signals defined by "mask"
2956b5d9 MW	123	* @set_config: optional hook for all kinds of settings. Uses the same
2956b5d9 MW	124	* packed config format as generic pinconf.
79a9becd AC	125	* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
	126	* implementation may not sleep
	127	* @dbg_show: optional routine to show contents in debugfs; default code
	128	* will be used when this is omitted, but custom code can show extra
	129	* state (such as pullup/pulldown configuration).
af6c235d LW	130	* @base: identifies the first GPIO number handled by this chip;
	131	* or, if negative during registration, requests dynamic ID allocation.
	132	* DEPRECATION: providing anything non-negative and nailing the base
30bb6fb3	133	* offset of GPIO chips is deprecated. Please pass -1 as base to
af6c235d LW	134	* let gpiolib select the chip base in all possible cases. We want to
af6c235d LW	135	* get rid of the static GPIO number space in the long run.
79a9becd AC	136	* @ngpio: the number of GPIOs handled by this controller; the last GPIO
79a9becd AC	137	* handled is (base + ngpio - 1).
79a9becd AC	138	* @names: if set, must be an array of strings to use as alternative
	139	* names for the GPIOs in this chip. Any entry in the array
	140	* may be NULL if there is no alias for the GPIO, however the
	141	* array must be @ngpio entries long. A name can include a single printk
	142	* format specifier for an unsigned int. It is substituted by the actual
	143	* number of the gpio.
9fb1f39e	144	* @can_sleep: flag must be set iff get()/set() methods sleep, as they
1c8732bb LW	145	* must while accessing GPIO expander chips over I2C or SPI. This
	146	* implies that if the chip supports IRQs, these IRQs need to be threaded
	147	* as the chip access may sleep when e.g. reading out the IRQ status
	148	* registers.
0f4630f3 LW	149	* @read_reg: reader function for generic GPIO
0f4630f3 LW	150	* @write_reg: writer function for generic GPIO
24efd94b LW	151	* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
	152	* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
	153	* generic GPIO core. It is for internal housekeeping only.
0f4630f3 LW	154	* @reg_dat: data (in) register for generic GPIO
0f4630f3 LW	155	* @reg_set: output set register (out=high) for generic GPIO
08bcd3ed	156	* @reg_clr: output clear register (out=low) for generic GPIO
0f4630f3 LW	157	* @reg_dir: direction setting register for generic GPIO
	158	* @bgpio_bits: number of register bits used for a generic GPIO i.e.
	159	* <register width> * 8
	160	* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
	161	* shadowed and real data registers writes together.
	162	* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
	163	* safely.
	164	* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
	165	* direction safely.
d245b3f9	166	* @irq_nested: True if set the interrupt handling is nested.
79b804cb MW	167	* @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
	168	* bits set to one
	169	* @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
	170	* be included in IRQ domain of the chip
41d6bb4c	171	* @lock_key: per GPIO IRQ chip lockdep class
79a9becd AC	172	*
	173	* A gpio_chip can help platforms abstract various sources of GPIOs so
	174	* they can all be accessed through a common programing interface.
	175	* Example sources would be SOC controllers, FPGAs, multifunction
	176	* chips, dedicated GPIO expanders, and so on.
	177	*
	178	* Each chip controls a number of signals, identified in method calls
	179	* by "offset" values in the range 0..(@ngpio - 1). When those signals
	180	* are referenced through calls like gpio_get_value(gpio), the offset
	181	* is calculated by subtracting @base from the gpio number.
	182	*/
	183	struct gpio_chip {
	184	const char *label;
ff2b1359	185	struct gpio_device *gpiodev;
58383c78	186	struct device *parent;
79a9becd	187	struct module *owner;
79a9becd AC	188
	189	int (request)(struct gpio_chip chip,
	190	unsigned offset);
	191	void (free)(struct gpio_chip chip,
	192	unsigned offset);
	193	int (get_direction)(struct gpio_chip chip,
	194	unsigned offset);
	195	int (direction_input)(struct gpio_chip chip,
	196	unsigned offset);
	197	int (direction_output)(struct gpio_chip chip,
	198	unsigned offset, int value);
	199	int (get)(struct gpio_chip chip,
	200	unsigned offset);
eec1d566 LW	201	int (get_multiple)(struct gpio_chip chip,
	202	unsigned long *mask,
	203	unsigned long *bits);
79a9becd AC	204	void (set)(struct gpio_chip chip,
79a9becd AC	205	unsigned offset, int value);
5f424243 RI	206	void (set_multiple)(struct gpio_chip chip,
	207	unsigned long *mask,
	208	unsigned long *bits);
2956b5d9 MW	209	int (set_config)(struct gpio_chip chip,
	210	unsigned offset,
	211	unsigned long config);
79a9becd AC	212	int (to_irq)(struct gpio_chip chip,
	213	unsigned offset);
	214
	215	void (dbg_show)(struct seq_file s,
	216	struct gpio_chip *chip);
	217	int base;
	218	u16 ngpio;
79a9becd	219	const char const names;
9fb1f39e	220	bool can_sleep;
79a9becd	221
0f4630f3 LW	222	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	223	unsigned long (read_reg)(void __iomem reg);
	224	void (write_reg)(void __iomem reg, unsigned long data);
24efd94b	225	bool be_bits;
0f4630f3 LW	226	void __iomem *reg_dat;
	227	void __iomem *reg_set;
	228	void __iomem *reg_clr;
	229	void __iomem *reg_dir;
	230	int bgpio_bits;
	231	spinlock_t bgpio_lock;
	232	unsigned long bgpio_data;
	233	unsigned long bgpio_dir;
	234	#endif
	235
14250520 LW	236	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	237	/*
7d75a871	238	* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
14250520 LW	239	* to handle IRQs for most practical cases.
14250520 LW	240	*/
d245b3f9	241	bool irq_nested;
79b804cb MW	242	bool irq_need_valid_mask;
79b804cb MW	243	unsigned long *irq_valid_mask;
a0a8bcf4	244	struct lock_class_key *lock_key;
c44eafd7 TR	245
	246	/**
	247	* @irq:
	248	*
	249	* Integrates interrupt chip functionality with the GPIO chip. Can be
	250	* used to handle IRQs for most practical cases.
	251	*/
	252	struct gpio_irq_chip irq;
14250520 LW	253	#endif
14250520 LW	254
79a9becd AC	255	#if defined(CONFIG_OF_GPIO)
	256	/*
	257	* If CONFIG_OF is enabled, then all GPIO controllers described in the
	258	* device tree automatically may have an OF translation
	259	*/
67049c50 TR	260
	261	/**
	262	* @of_node:
	263	*
	264	* Pointer to a device tree node representing this GPIO controller.
	265	*/
79a9becd	266	struct device_node *of_node;
67049c50 TR	267
	268	/**
	269	* @of_gpio_n_cells:
	270	*
	271	* Number of cells used to form the GPIO specifier.
	272	*/
e3b445d7	273	unsigned int of_gpio_n_cells;
67049c50 TR	274
	275	/**
	276	* @of_xlate:
	277	*
	278	* Callback to translate a device tree GPIO specifier into a chip-
	279	* relative GPIO number and flags.
	280	*/
79a9becd AC	281	int (of_xlate)(struct gpio_chip gc,
	282	const struct of_phandle_args gpiospec, u32 flags);
	283	#endif
79a9becd AC	284	};
	285
	286	extern const char gpiochip_is_requested(struct gpio_chip chip,
	287	unsigned offset);
	288
	289	/* add/remove chips */
b08ea35a LW	290	extern int gpiochip_add_data(struct gpio_chip chip, void data);
	291	static inline int gpiochip_add(struct gpio_chip *chip)
	292	{
	293	return gpiochip_add_data(chip, NULL);
	294	}
e1db1706	295	extern void gpiochip_remove(struct gpio_chip *chip);
0cf3292c LD	296	extern int devm_gpiochip_add_data(struct device dev, struct gpio_chip chip,
	297	void *data);
	298	extern void devm_gpiochip_remove(struct device dev, struct gpio_chip chip);
	299
79a9becd AC	300	extern struct gpio_chip gpiochip_find(void data,
	301	int (match)(struct gpio_chip chip, void *data));
	302
	303	/* lock/unlock as IRQ */
e3a2e878 AC	304	int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
e3a2e878 AC	305	void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
6cee3821	306	bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
79a9becd	307
143b65d6 LW	308	/* Line status inquiry for drivers */
	309	bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
	310	bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
	311
05f479bf CK	312	/* Sleep persistence inquiry for drivers */
	313	bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
	314
b08ea35a	315	/* get driver data */
43c54eca	316	void gpiochip_get_data(struct gpio_chip chip);
b08ea35a	317
bb1e88cc AC	318	struct gpio_chip gpiod_to_chip(const struct gpio_desc desc);
bb1e88cc AC	319
0f4630f3 LW	320	struct bgpio_pdata {
	321	const char *label;
	322	int base;
	323	int ngpio;
	324	};
	325
c474e348 AB	326	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
c474e348 AB	327
0f4630f3 LW	328	int bgpio_init(struct gpio_chip gc, struct device dev,
	329	unsigned long sz, void __iomem dat, void __iomem set,
	330	void __iomem clr, void __iomem dirout, void __iomem *dirin,
	331	unsigned long flags);
	332
	333	#define BGPIOF_BIG_ENDIAN BIT(0)
	334	#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
	335	#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
	336	#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
	337	#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
	338	#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
	339
	340	#endif
	341
14250520 LW	342	#ifdef CONFIG_GPIOLIB_IRQCHIP
	343
	344	void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
	345	struct irq_chip *irqchip,
6f79309a	346	unsigned int parent_irq,
14250520 LW	347	irq_flow_handler_t parent_handler);
14250520 LW	348
d245b3f9 LW	349	void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
d245b3f9 LW	350	struct irq_chip *irqchip,
6f79309a	351	unsigned int parent_irq);
d245b3f9	352
739e6f59 LW	353	int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
	354	struct irq_chip *irqchip,
	355	unsigned int first_irq,
	356	irq_flow_handler_t handler,
	357	unsigned int type,
	358	bool nested,
	359	struct lock_class_key *lock_key);
	360
	361	#ifdef CONFIG_LOCKDEP
	362
	363	/*
	364	* Lockdep requires that each irqchip instance be created with a
	365	* unique key so as to avoid unnecessary warnings. This upfront
	366	* boilerplate static inlines provides such a key for each
	367	* unique instance.
	368	*/
	369	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	370	struct irq_chip *irqchip,
	371	unsigned int first_irq,
	372	irq_flow_handler_t handler,
	373	unsigned int type)
	374	{
	375	static struct lock_class_key key;
	376
	377	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	378	handler, type, false, &key);
	379	}
	380
	381	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
a0a8bcf4 GS	382	struct irq_chip *irqchip,
	383	unsigned int first_irq,
	384	irq_flow_handler_t handler,
739e6f59 LW	385	unsigned int type)
	386	{
	387
	388	static struct lock_class_key key;
	389
	390	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	391	handler, type, true, &key);
	392	}
	393	#else
	394	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	395	struct irq_chip *irqchip,
	396	unsigned int first_irq,
	397	irq_flow_handler_t handler,
	398	unsigned int type)
	399	{
	400	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	401	handler, type, false, NULL);
	402	}
a0a8bcf4	403
d245b3f9 LW	404	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
	405	struct irq_chip *irqchip,
	406	unsigned int first_irq,
	407	irq_flow_handler_t handler,
	408	unsigned int type)
	409	{
739e6f59 LW	410	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
739e6f59 LW	411	handler, type, true, NULL);
d245b3f9	412	}
739e6f59	413	#endif /* CONFIG_LOCKDEP */
14250520	414
7d75a871	415	#endif /* CONFIG_GPIOLIB_IRQCHIP */
14250520	416
c771c2f4 JG	417	int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
c771c2f4 JG	418	void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
2956b5d9 MW	419	int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	420	unsigned long config);
c771c2f4	421
964cb341 LW	422	#ifdef CONFIG_PINCTRL
	423
	424	/**
	425	* struct gpio_pin_range - pin range controlled by a gpio chip
950d55f5	426	* @node: list for maintaining set of pin ranges, used internally
964cb341 LW	427	* @pctldev: pinctrl device which handles corresponding pins
	428	* @range: actual range of pins controlled by a gpio controller
	429	*/
964cb341 LW	430	struct gpio_pin_range {
	431	struct list_head node;
	432	struct pinctrl_dev *pctldev;
	433	struct pinctrl_gpio_range range;
	434	};
	435
	436	int gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	437	unsigned int gpio_offset, unsigned int pin_offset,
	438	unsigned int npins);
	439	int gpiochip_add_pingroup_range(struct gpio_chip *chip,
	440	struct pinctrl_dev *pctldev,
	441	unsigned int gpio_offset, const char *pin_group);
	442	void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
	443
	444	#else
	445
	446	static inline int
	447	gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	448	unsigned int gpio_offset, unsigned int pin_offset,
	449	unsigned int npins)
	450	{
	451	return 0;
	452	}
	453	static inline int
	454	gpiochip_add_pingroup_range(struct gpio_chip *chip,
	455	struct pinctrl_dev *pctldev,
	456	unsigned int gpio_offset, const char *pin_group)
	457	{
	458	return 0;
	459	}
	460
	461	static inline void
	462	gpiochip_remove_pin_ranges(struct gpio_chip *chip)
	463	{
	464	}
	465
	466	#endif /* CONFIG_PINCTRL */
	467
abdc08a3 AC	468	struct gpio_desc gpiochip_request_own_desc(struct gpio_chip chip, u16 hwnum,
abdc08a3 AC	469	const char *label);
f7d4ad98 GR	470	void gpiochip_free_own_desc(struct gpio_desc *desc);
f7d4ad98 GR	471
bb1e88cc AC	472	#else /* CONFIG_GPIOLIB */
	473
	474	static inline struct gpio_chip gpiod_to_chip(const struct gpio_desc desc)
	475	{
	476	/* GPIO can never have been requested */
	477	WARN_ON(1);
	478	return ERR_PTR(-ENODEV);
	479	}
	480
	481	#endif /* CONFIG_GPIOLIB */
	482
79a9becd	483	#endif