[linux-block.git] / include / linux / gpio / driver.h

#ifndef __LINUX_GPIO_DRIVER_H
#define __LINUX_GPIO_DRIVER_H

#include <linux/device.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>

struct gpio_desc;
struct of_phandle_args;
struct device_node;
struct seq_file;
struct gpio_device;
struct module;

#ifdef CONFIG_GPIOLIB

/**
 * enum single_ended_mode - mode for single ended operation
 * @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
 * @LINE_MODE_OPEN_DRAIN: set line to be open drain
 * @LINE_MODE_OPEN_SOURCE: set line to be open source
 */
enum single_ended_mode {
	LINE_MODE_PUSH_PULL,
	LINE_MODE_OPEN_DRAIN,
	LINE_MODE_OPEN_SOURCE,
};

/**
 * struct gpio_chip - abstract a GPIO controller
 * @label: a functional name for the GPIO device, such as a part
 *	number or the name of the SoC IP-block implementing it.
 * @gpiodev: the internal state holder, opaque struct
 * @parent: optional parent device providing the GPIOs
 * @owner: helps prevent removal of modules exporting active GPIOs
 * @request: optional hook for chip-specific activation, such as
 *	enabling module power and clock; may sleep
 * @free: optional hook for chip-specific deactivation, such as
 *	disabling module power and clock; may sleep
 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 *	(same as GPIOF_DIR_XXX), or negative error
 * @direction_input: configures signal "offset" as input, or returns error
 * @direction_output: configures signal "offset" as output, or returns error
 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 * @set: assigns output value for signal "offset"
 * @set_multiple: assigns output values for multiple signals defined by "mask"
 * @set_debounce: optional hook for setting debounce time for specified gpio in
 *	interrupt triggered gpio chips
 * @set_single_ended: optional hook for setting a line as open drain, open
 *	source, or non-single ended (restore from open drain/source to normal
 *	push-pull mode) this should be implemented if the hardware supports
 *	open drain or open source settings. The GPIOlib will otherwise try
 *	to emulate open drain/source by not actively driving lines high/low
 *	if a consumer request this. The driver may return -ENOTSUPP if e.g.
 *	it supports just open drain but not open source and is called
 *	with LINE_MODE_OPEN_SOURCE as mode argument.
 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 *	implementation may not sleep
 * @dbg_show: optional routine to show contents in debugfs; default code
 *	will be used when this is omitted, but custom code can show extra
 *	state (such as pullup/pulldown configuration).
 * @base: identifies the first GPIO number handled by this chip;
 *	or, if negative during registration, requests dynamic ID allocation.
 *	DEPRECATION: providing anything non-negative and nailing the base
 *	offset of GPIO chips is deprecated. Please pass -1 as base to
 *	let gpiolib select the chip base in all possible cases. We want to
 *	get rid of the static GPIO number space in the long run.
 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 *	handled is (base + ngpio - 1).
 * @names: if set, must be an array of strings to use as alternative
 *      names for the GPIOs in this chip. Any entry in the array
 *      may be NULL if there is no alias for the GPIO, however the
 *      array must be @ngpio entries long.  A name can include a single printk
 *      format specifier for an unsigned int.  It is substituted by the actual
 *      number of the gpio.
 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 *	must while accessing GPIO expander chips over I2C or SPI. This
 *	implies that if the chip supports IRQs, these IRQs need to be threaded
 *	as the chip access may sleep when e.g. reading out the IRQ status
 *	registers.
 * @irq_not_threaded: flag must be set if @can_sleep is set but the
 *	IRQs don't need to be threaded
 * @read_reg: reader function for generic GPIO
 * @write_reg: writer function for generic GPIO
 * @pin2mask: some generic GPIO controllers work with the big-endian bits
 *	notation, e.g. in a 8-bits register, GPIO7 is the least significant
 *	bit. This callback assigns the right bit mask.
 * @reg_dat: data (in) register for generic GPIO
 * @reg_set: output set register (out=high) for generic GPIO
 * @reg_clk: output clear register (out=low) for generic GPIO
 * @reg_dir: direction setting register for generic GPIO
 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 *	<register width> * 8
 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 *	shadowed and real data registers writes together.
 * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
 *	safely.
 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 *	direction safely.
 * @irqchip: GPIO IRQ chip impl, provided by GPIO driver
 * @irqdomain: Interrupt translation domain; responsible for mapping
 *	between GPIO hwirq number and linux irq number
 * @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
 * @irq_handler: the irq handler to use (often a predefined irq core function)
 *	for GPIO IRQs, provided by GPIO driver
 * @irq_default_type: default IRQ triggering type applied during GPIO driver
 *	initialization, provided by GPIO driver
 * @irq_parent: GPIO IRQ chip parent/bank linux irq number,
 *	provided by GPIO driver
 * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
 *	bits set to one
 * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
 *	be included in IRQ domain of the chip
 * @lock_key: per GPIO IRQ chip lockdep class
 *
 * A gpio_chip can help platforms abstract various sources of GPIOs so
 * they can all be accessed through a common programing interface.
 * Example sources would be SOC controllers, FPGAs, multifunction
 * chips, dedicated GPIO expanders, and so on.
 *
 * Each chip controls a number of signals, identified in method calls
 * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 * are referenced through calls like gpio_get_value(gpio), the offset
 * is calculated by subtracting @base from the gpio number.
 */
struct gpio_chip {
	const char		*label;
	struct gpio_device	*gpiodev;
	struct device		*parent;
	struct module		*owner;

	int			(*request)(struct gpio_chip *chip,
						unsigned offset);
	void			(*free)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_direction)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_input)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_output)(struct gpio_chip *chip,
						unsigned offset, int value);
	int			(*get)(struct gpio_chip *chip,
						unsigned offset);
	void			(*set)(struct gpio_chip *chip,
						unsigned offset, int value);
	void			(*set_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	int			(*set_debounce)(struct gpio_chip *chip,
						unsigned offset,
						unsigned debounce);
	int			(*set_single_ended)(struct gpio_chip *chip,
						unsigned offset,
						enum single_ended_mode mode);

	int			(*to_irq)(struct gpio_chip *chip,
						unsigned offset);

	void			(*dbg_show)(struct seq_file *s,
						struct gpio_chip *chip);
	int			base;
	u16			ngpio;
	const char		*const *names;
	bool			can_sleep;
	bool			irq_not_threaded;

#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	unsigned long (*read_reg)(void __iomem *reg);
	void (*write_reg)(void __iomem *reg, unsigned long data);
	unsigned long (*pin2mask)(struct gpio_chip *gc, unsigned int pin);
	void __iomem *reg_dat;
	void __iomem *reg_set;
	void __iomem *reg_clr;
	void __iomem *reg_dir;
	int bgpio_bits;
	spinlock_t bgpio_lock;
	unsigned long bgpio_data;
	unsigned long bgpio_dir;
#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP
	/*
	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
	 * to handle IRQs for most practical cases.
	 */
	struct irq_chip		*irqchip;
	struct irq_domain	*irqdomain;
	unsigned int		irq_base;
	irq_flow_handler_t	irq_handler;
	unsigned int		irq_default_type;
	int			irq_parent;
	bool			irq_need_valid_mask;
	unsigned long		*irq_valid_mask;
	struct lock_class_key	*lock_key;
#endif

#if defined(CONFIG_OF_GPIO)
	/*
	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
	 * device tree automatically may have an OF translation
	 */
	struct device_node *of_node;
	int of_gpio_n_cells;
	int (*of_xlate)(struct gpio_chip *gc,
			const struct of_phandle_args *gpiospec, u32 *flags);
#endif
};

extern const char *gpiochip_is_requested(struct gpio_chip *chip,
			unsigned offset);

/* add/remove chips */
extern int gpiochip_add_data(struct gpio_chip *chip, void *data);
static inline int gpiochip_add(struct gpio_chip *chip)
{
	return gpiochip_add_data(chip, NULL);
}
extern void gpiochip_remove(struct gpio_chip *chip);
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
				  void *data);
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);

extern struct gpio_chip *gpiochip_find(void *data,
			      int (*match)(struct gpio_chip *chip, void *data));

/* lock/unlock as IRQ */
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);

/* Line status inquiry for drivers */
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);

/* get driver data */
void *gpiochip_get_data(struct gpio_chip *chip);

struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);

struct bgpio_pdata {
	const char *label;
	int base;
	int ngpio;
};

#if IS_ENABLED(CONFIG_GPIO_GENERIC)

int bgpio_init(struct gpio_chip *gc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags);

#define BGPIOF_BIG_ENDIAN		BIT(0)
#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */

#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP

void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		int parent_irq,
		irq_flow_handler_t parent_handler);

int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type,
			  struct lock_class_key *lock_key);

#ifdef CONFIG_LOCKDEP
#define gpiochip_irqchip_add(...)				\
(								\
	({							\
		static struct lock_class_key _key;		\
		_gpiochip_irqchip_add(__VA_ARGS__, &_key);	\
	})							\
)
#else
#define gpiochip_irqchip_add(...)				\
	_gpiochip_irqchip_add(__VA_ARGS__, NULL)
#endif

#endif /* CONFIG_GPIOLIB_IRQCHIP */

int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);

#ifdef CONFIG_PINCTRL

/**
 * struct gpio_pin_range - pin range controlled by a gpio chip
 * @head: list for maintaining set of pin ranges, used internally
 * @pctldev: pinctrl device which handles corresponding pins
 * @range: actual range of pins controlled by a gpio controller
 */

struct gpio_pin_range {
	struct list_head node;
	struct pinctrl_dev *pctldev;
	struct pinctrl_gpio_range range;
};

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
			   unsigned int gpio_offset, unsigned int pin_offset,
			   unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);

#else

static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
		       unsigned int gpio_offset, unsigned int pin_offset,
		       unsigned int npins)
{
	return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group)
{
	return 0;
}

static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
}

#endif /* CONFIG_PINCTRL */

struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
					    const char *label);
void gpiochip_free_own_desc(struct gpio_desc *desc);

#else /* CONFIG_GPIOLIB */

static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
{
	/* GPIO can never have been requested */
	WARN_ON(1);
	return ERR_PTR(-ENODEV);
}

#endif /* CONFIG_GPIOLIB */

#endif
Commit	Line	Data
79a9becd AC	1	#ifndef __LINUX_GPIO_DRIVER_H
	2	#define __LINUX_GPIO_DRIVER_H
	3
ff2b1359	4	#include <linux/device.h>
79a9becd	5	#include <linux/types.h>
14250520 LW	6	#include <linux/irq.h>
	7	#include <linux/irqchip/chained_irq.h>
	8	#include <linux/irqdomain.h>
a0a8bcf4	9	#include <linux/lockdep.h>
964cb341	10	#include <linux/pinctrl/pinctrl.h>
79a9becd	11
79a9becd	12	struct gpio_desc;
c9a9972b AC	13	struct of_phandle_args;
c9a9972b AC	14	struct device_node;
f3ed0b66	15	struct seq_file;
ff2b1359	16	struct gpio_device;
d47529b2	17	struct module;
79a9becd	18
bb1e88cc AC	19	#ifdef CONFIG_GPIOLIB
bb1e88cc AC	20
c663e5f5 LW	21	/**
	22	* enum single_ended_mode - mode for single ended operation
	23	* @LINE_MODE_PUSH_PULL: normal mode for a GPIO line, drive actively high/low
	24	* @LINE_MODE_OPEN_DRAIN: set line to be open drain
	25	* @LINE_MODE_OPEN_SOURCE: set line to be open source
	26	*/
	27	enum single_ended_mode {
	28	LINE_MODE_PUSH_PULL,
	29	LINE_MODE_OPEN_DRAIN,
	30	LINE_MODE_OPEN_SOURCE,
	31	};
	32
79a9becd AC	33	/**
79a9becd AC	34	* struct gpio_chip - abstract a GPIO controller
df4878e9 LW	35	* @label: a functional name for the GPIO device, such as a part
df4878e9 LW	36	* number or the name of the SoC IP-block implementing it.
ff2b1359	37	* @gpiodev: the internal state holder, opaque struct
58383c78	38	* @parent: optional parent device providing the GPIOs
79a9becd	39	* @owner: helps prevent removal of modules exporting active GPIOs
79a9becd AC	40	* @request: optional hook for chip-specific activation, such as
	41	* enabling module power and clock; may sleep
	42	* @free: optional hook for chip-specific deactivation, such as
	43	* disabling module power and clock; may sleep
	44	* @get_direction: returns direction for signal "offset", 0=out, 1=in,
	45	* (same as GPIOF_DIR_XXX), or negative error
	46	* @direction_input: configures signal "offset" as input, or returns error
	47	* @direction_output: configures signal "offset" as output, or returns error
60befd2e	48	* @get: returns value for signal "offset", 0=low, 1=high, or negative error
79a9becd	49	* @set: assigns output value for signal "offset"
5f424243	50	* @set_multiple: assigns output values for multiple signals defined by "mask"
79a9becd	51	* @set_debounce: optional hook for setting debounce time for specified gpio in
c663e5f5 LW	52	* interrupt triggered gpio chips
	53	* @set_single_ended: optional hook for setting a line as open drain, open
	54	* source, or non-single ended (restore from open drain/source to normal
	55	* push-pull mode) this should be implemented if the hardware supports
	56	* open drain or open source settings. The GPIOlib will otherwise try
	57	* to emulate open drain/source by not actively driving lines high/low
	58	* if a consumer request this. The driver may return -ENOTSUPP if e.g.
	59	* it supports just open drain but not open source and is called
	60	* with LINE_MODE_OPEN_SOURCE as mode argument.
79a9becd AC	61	* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
	62	* implementation may not sleep
	63	* @dbg_show: optional routine to show contents in debugfs; default code
	64	* will be used when this is omitted, but custom code can show extra
	65	* state (such as pullup/pulldown configuration).
af6c235d LW	66	* @base: identifies the first GPIO number handled by this chip;
	67	* or, if negative during registration, requests dynamic ID allocation.
	68	* DEPRECATION: providing anything non-negative and nailing the base
30bb6fb3	69	* offset of GPIO chips is deprecated. Please pass -1 as base to
af6c235d LW	70	* let gpiolib select the chip base in all possible cases. We want to
af6c235d LW	71	* get rid of the static GPIO number space in the long run.
79a9becd AC	72	* @ngpio: the number of GPIOs handled by this controller; the last GPIO
79a9becd AC	73	* handled is (base + ngpio - 1).
79a9becd AC	74	* @names: if set, must be an array of strings to use as alternative
	75	* names for the GPIOs in this chip. Any entry in the array
	76	* may be NULL if there is no alias for the GPIO, however the
	77	* array must be @ngpio entries long. A name can include a single printk
	78	* format specifier for an unsigned int. It is substituted by the actual
	79	* number of the gpio.
9fb1f39e	80	* @can_sleep: flag must be set iff get()/set() methods sleep, as they
1c8732bb LW	81	* must while accessing GPIO expander chips over I2C or SPI. This
	82	* implies that if the chip supports IRQs, these IRQs need to be threaded
	83	* as the chip access may sleep when e.g. reading out the IRQ status
	84	* registers.
295494af OP	85	* @irq_not_threaded: flag must be set if @can_sleep is set but the
295494af OP	86	* IRQs don't need to be threaded
0f4630f3 LW	87	* @read_reg: reader function for generic GPIO
	88	* @write_reg: writer function for generic GPIO
	89	* @pin2mask: some generic GPIO controllers work with the big-endian bits
	90	* notation, e.g. in a 8-bits register, GPIO7 is the least significant
	91	* bit. This callback assigns the right bit mask.
	92	* @reg_dat: data (in) register for generic GPIO
	93	* @reg_set: output set register (out=high) for generic GPIO
	94	* @reg_clk: output clear register (out=low) for generic GPIO
	95	* @reg_dir: direction setting register for generic GPIO
	96	* @bgpio_bits: number of register bits used for a generic GPIO i.e.
	97	* <register width> * 8
	98	* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
	99	* shadowed and real data registers writes together.
	100	* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
	101	* safely.
	102	* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
	103	* direction safely.
41d6bb4c GS	104	* @irqchip: GPIO IRQ chip impl, provided by GPIO driver
	105	* @irqdomain: Interrupt translation domain; responsible for mapping
	106	* between GPIO hwirq number and linux irq number
	107	* @irq_base: first linux IRQ number assigned to GPIO IRQ chip (deprecated)
	108	* @irq_handler: the irq handler to use (often a predefined irq core function)
	109	* for GPIO IRQs, provided by GPIO driver
	110	* @irq_default_type: default IRQ triggering type applied during GPIO driver
	111	* initialization, provided by GPIO driver
	112	* @irq_parent: GPIO IRQ chip parent/bank linux irq number,
	113	* provided by GPIO driver
79b804cb MW	114	* @irq_need_valid_mask: If set core allocates @irq_valid_mask with all
	115	* bits set to one
	116	* @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to
	117	* be included in IRQ domain of the chip
41d6bb4c	118	* @lock_key: per GPIO IRQ chip lockdep class
79a9becd AC	119	*
	120	* A gpio_chip can help platforms abstract various sources of GPIOs so
	121	* they can all be accessed through a common programing interface.
	122	* Example sources would be SOC controllers, FPGAs, multifunction
	123	* chips, dedicated GPIO expanders, and so on.
	124	*
	125	* Each chip controls a number of signals, identified in method calls
	126	* by "offset" values in the range 0..(@ngpio - 1). When those signals
	127	* are referenced through calls like gpio_get_value(gpio), the offset
	128	* is calculated by subtracting @base from the gpio number.
	129	*/
	130	struct gpio_chip {
	131	const char *label;
ff2b1359	132	struct gpio_device *gpiodev;
58383c78	133	struct device *parent;
79a9becd	134	struct module *owner;
79a9becd AC	135
	136	int (request)(struct gpio_chip chip,
	137	unsigned offset);
	138	void (free)(struct gpio_chip chip,
	139	unsigned offset);
	140	int (get_direction)(struct gpio_chip chip,
	141	unsigned offset);
	142	int (direction_input)(struct gpio_chip chip,
	143	unsigned offset);
	144	int (direction_output)(struct gpio_chip chip,
	145	unsigned offset, int value);
	146	int (get)(struct gpio_chip chip,
	147	unsigned offset);
	148	void (set)(struct gpio_chip chip,
	149	unsigned offset, int value);
5f424243 RI	150	void (set_multiple)(struct gpio_chip chip,
	151	unsigned long *mask,
	152	unsigned long *bits);
79a9becd AC	153	int (set_debounce)(struct gpio_chip chip,
	154	unsigned offset,
	155	unsigned debounce);
c663e5f5 LW	156	int (set_single_ended)(struct gpio_chip chip,
	157	unsigned offset,
	158	enum single_ended_mode mode);
79a9becd AC	159
	160	int (to_irq)(struct gpio_chip chip,
	161	unsigned offset);
	162
	163	void (dbg_show)(struct seq_file s,
	164	struct gpio_chip *chip);
	165	int base;
	166	u16 ngpio;
79a9becd	167	const char const names;
9fb1f39e	168	bool can_sleep;
295494af	169	bool irq_not_threaded;
79a9becd	170
0f4630f3 LW	171	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	172	unsigned long (read_reg)(void __iomem reg);
	173	void (write_reg)(void __iomem reg, unsigned long data);
	174	unsigned long (pin2mask)(struct gpio_chip gc, unsigned int pin);
	175	void __iomem *reg_dat;
	176	void __iomem *reg_set;
	177	void __iomem *reg_clr;
	178	void __iomem *reg_dir;
	179	int bgpio_bits;
	180	spinlock_t bgpio_lock;
	181	unsigned long bgpio_data;
	182	unsigned long bgpio_dir;
	183	#endif
	184
14250520 LW	185	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	186	/*
7d75a871	187	* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
14250520 LW	188	* to handle IRQs for most practical cases.
	189	*/
	190	struct irq_chip *irqchip;
	191	struct irq_domain *irqdomain;
c3626fde	192	unsigned int irq_base;
14250520 LW	193	irq_flow_handler_t irq_handler;
14250520 LW	194	unsigned int irq_default_type;
25e4fe92	195	int irq_parent;
79b804cb MW	196	bool irq_need_valid_mask;
79b804cb MW	197	unsigned long *irq_valid_mask;
a0a8bcf4	198	struct lock_class_key *lock_key;
14250520 LW	199	#endif
14250520 LW	200
79a9becd AC	201	#if defined(CONFIG_OF_GPIO)
	202	/*
	203	* If CONFIG_OF is enabled, then all GPIO controllers described in the
	204	* device tree automatically may have an OF translation
	205	*/
	206	struct device_node *of_node;
	207	int of_gpio_n_cells;
	208	int (of_xlate)(struct gpio_chip gc,
	209	const struct of_phandle_args gpiospec, u32 flags);
	210	#endif
79a9becd AC	211	};
	212
	213	extern const char gpiochip_is_requested(struct gpio_chip chip,
	214	unsigned offset);
	215
	216	/* add/remove chips */
b08ea35a LW	217	extern int gpiochip_add_data(struct gpio_chip chip, void data);
	218	static inline int gpiochip_add(struct gpio_chip *chip)
	219	{
	220	return gpiochip_add_data(chip, NULL);
	221	}
e1db1706	222	extern void gpiochip_remove(struct gpio_chip *chip);
0cf3292c LD	223	extern int devm_gpiochip_add_data(struct device dev, struct gpio_chip chip,
	224	void *data);
	225	extern void devm_gpiochip_remove(struct device dev, struct gpio_chip chip);
	226
79a9becd AC	227	extern struct gpio_chip gpiochip_find(void data,
	228	int (match)(struct gpio_chip chip, void *data));
	229
	230	/* lock/unlock as IRQ */
e3a2e878 AC	231	int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
e3a2e878 AC	232	void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
6cee3821	233	bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
79a9becd	234
143b65d6 LW	235	/* Line status inquiry for drivers */
	236	bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
	237	bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
	238
b08ea35a	239	/* get driver data */
43c54eca	240	void gpiochip_get_data(struct gpio_chip chip);
b08ea35a	241
bb1e88cc AC	242	struct gpio_chip gpiod_to_chip(const struct gpio_desc desc);
bb1e88cc AC	243
0f4630f3 LW	244	struct bgpio_pdata {
	245	const char *label;
	246	int base;
	247	int ngpio;
	248	};
	249
c474e348 AB	250	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
c474e348 AB	251
0f4630f3 LW	252	int bgpio_init(struct gpio_chip gc, struct device dev,
	253	unsigned long sz, void __iomem dat, void __iomem set,
	254	void __iomem clr, void __iomem dirout, void __iomem *dirin,
	255	unsigned long flags);
	256
	257	#define BGPIOF_BIG_ENDIAN BIT(0)
	258	#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
	259	#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
	260	#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
	261	#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
	262	#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
	263
	264	#endif
	265
14250520 LW	266	#ifdef CONFIG_GPIOLIB_IRQCHIP
	267
	268	void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
	269	struct irq_chip *irqchip,
	270	int parent_irq,
	271	irq_flow_handler_t parent_handler);
	272
a0a8bcf4 GS	273	int _gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	274	struct irq_chip *irqchip,
	275	unsigned int first_irq,
	276	irq_flow_handler_t handler,
	277	unsigned int type,
	278	struct lock_class_key *lock_key);
	279
	280	#ifdef CONFIG_LOCKDEP
	281	#define gpiochip_irqchip_add(...) \
	282	( \
	283	({ \
	284	static struct lock_class_key _key; \
	285	_gpiochip_irqchip_add(__VA_ARGS__, &_key); \
	286	}) \
	287	)
	288	#else
	289	#define gpiochip_irqchip_add(...) \
	290	_gpiochip_irqchip_add(__VA_ARGS__, NULL)
	291	#endif
14250520	292
7d75a871	293	#endif /* CONFIG_GPIOLIB_IRQCHIP */
14250520	294
c771c2f4 JG	295	int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
	296	void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
	297
964cb341 LW	298	#ifdef CONFIG_PINCTRL
	299
	300	/**
	301	* struct gpio_pin_range - pin range controlled by a gpio chip
	302	* @head: list for maintaining set of pin ranges, used internally
	303	* @pctldev: pinctrl device which handles corresponding pins
	304	* @range: actual range of pins controlled by a gpio controller
	305	*/
	306
	307	struct gpio_pin_range {
	308	struct list_head node;
	309	struct pinctrl_dev *pctldev;
	310	struct pinctrl_gpio_range range;
	311	};
	312
	313	int gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	314	unsigned int gpio_offset, unsigned int pin_offset,
	315	unsigned int npins);
	316	int gpiochip_add_pingroup_range(struct gpio_chip *chip,
	317	struct pinctrl_dev *pctldev,
	318	unsigned int gpio_offset, const char *pin_group);
	319	void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
	320
	321	#else
	322
	323	static inline int
	324	gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	325	unsigned int gpio_offset, unsigned int pin_offset,
	326	unsigned int npins)
	327	{
	328	return 0;
	329	}
	330	static inline int
	331	gpiochip_add_pingroup_range(struct gpio_chip *chip,
	332	struct pinctrl_dev *pctldev,
	333	unsigned int gpio_offset, const char *pin_group)
	334	{
	335	return 0;
	336	}
	337
	338	static inline void
	339	gpiochip_remove_pin_ranges(struct gpio_chip *chip)
	340	{
	341	}
	342
	343	#endif /* CONFIG_PINCTRL */
	344
abdc08a3 AC	345	struct gpio_desc gpiochip_request_own_desc(struct gpio_chip chip, u16 hwnum,
abdc08a3 AC	346	const char *label);
f7d4ad98 GR	347	void gpiochip_free_own_desc(struct gpio_desc *desc);
f7d4ad98 GR	348
bb1e88cc AC	349	#else /* CONFIG_GPIOLIB */
	350
	351	static inline struct gpio_chip gpiod_to_chip(const struct gpio_desc desc)
	352	{
	353	/* GPIO can never have been requested */
	354	WARN_ON(1);
	355	return ERR_PTR(-ENODEV);
	356	}
	357
	358	#endif /* CONFIG_GPIOLIB */
	359
79a9becd	360	#endif