[linux-block.git] / include / linux / gpio / driver.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_GPIO_DRIVER_H
#define __LINUX_GPIO_DRIVER_H

#include <linux/device.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/lockdep.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinconf-generic.h>

struct gpio_desc;
struct of_phandle_args;
struct device_node;
struct seq_file;
struct gpio_device;
struct module;

#ifdef CONFIG_GPIOLIB

#ifdef CONFIG_GPIOLIB_IRQCHIP
/**
 * struct gpio_irq_chip - GPIO interrupt controller
 */
struct gpio_irq_chip {
	/**
	 * @chip:
	 *
	 * GPIO IRQ chip implementation, provided by GPIO driver.
	 */
	struct irq_chip *chip;

	/**
	 * @domain:
	 *
	 * Interrupt translation domain; responsible for mapping between GPIO
	 * hwirq number and Linux IRQ number.
	 */
	struct irq_domain *domain;

	/**
	 * @domain_ops:
	 *
	 * Table of interrupt domain operations for this IRQ chip.
	 */
	const struct irq_domain_ops *domain_ops;

	/**
	 * @handler:
	 *
	 * The IRQ handler to use (often a predefined IRQ core function) for
	 * GPIO IRQs, provided by GPIO driver.
	 */
	irq_flow_handler_t handler;

	/**
	 * @default_type:
	 *
	 * Default IRQ triggering type applied during GPIO driver
	 * initialization, provided by GPIO driver.
	 */
	unsigned int default_type;

	/**
	 * @lock_key:
	 *
	 * Per GPIO IRQ chip lockdep class.
	 */
	struct lock_class_key *lock_key;

	/**
	 * @parent_handler:
	 *
	 * The interrupt handler for the GPIO chip's parent interrupts, may be
	 * NULL if the parent interrupts are nested rather than cascaded.
	 */
	irq_flow_handler_t parent_handler;

	/**
	 * @parent_handler_data:
	 *
	 * Data associated, and passed to, the handler for the parent
	 * interrupt.
	 */
	void *parent_handler_data;

	/**
	 * @num_parents:
	 *
	 * The number of interrupt parents of a GPIO chip.
	 */
	unsigned int num_parents;

	/**
	 * @parents:
	 *
	 * A list of interrupt parents of a GPIO chip. This is owned by the
	 * driver, so the core will only reference this list, not modify it.
	 */
	unsigned int *parents;

	/**
	 * @map:
	 *
	 * A list of interrupt parents for each line of a GPIO chip.
	 */
	unsigned int *map;

	/**
	 * @threaded:
	 *
	 * True if set the interrupt handling uses nested threads.
	 */
	bool threaded;

	/**
	 * @need_valid_mask:
	 *
	 * If set core allocates @valid_mask with all bits set to one.
	 */
	bool need_valid_mask;

	/**
	 * @valid_mask:
	 *
	 * If not %NULL holds bitmask of GPIOs which are valid to be included
	 * in IRQ domain of the chip.
	 */
	unsigned long *valid_mask;

	/**
	 * @first:
	 *
	 * Required for static IRQ allocation. If set, irq_domain_add_simple()
	 * will allocate and map all IRQs during initialization.
	 */
	unsigned int first;
};

static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
{
	return container_of(chip, struct gpio_irq_chip, chip);
}
#endif

/**
 * struct gpio_chip - abstract a GPIO controller
 * @label: a functional name for the GPIO device, such as a part
 *	number or the name of the SoC IP-block implementing it.
 * @gpiodev: the internal state holder, opaque struct
 * @parent: optional parent device providing the GPIOs
 * @owner: helps prevent removal of modules exporting active GPIOs
 * @request: optional hook for chip-specific activation, such as
 *	enabling module power and clock; may sleep
 * @free: optional hook for chip-specific deactivation, such as
 *	disabling module power and clock; may sleep
 * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 *	(same as GPIOF_DIR_XXX), or negative error
 * @direction_input: configures signal "offset" as input, or returns error
 * @direction_output: configures signal "offset" as output, or returns error
 * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 * @get_multiple: reads values for multiple signals defined by "mask" and
 *	stores them in "bits", returns 0 on success or negative error
 * @set: assigns output value for signal "offset"
 * @set_multiple: assigns output values for multiple signals defined by "mask"
 * @set_config: optional hook for all kinds of settings. Uses the same
 *	packed config format as generic pinconf.
 * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 *	implementation may not sleep
 * @dbg_show: optional routine to show contents in debugfs; default code
 *	will be used when this is omitted, but custom code can show extra
 *	state (such as pullup/pulldown configuration).
 * @base: identifies the first GPIO number handled by this chip;
 *	or, if negative during registration, requests dynamic ID allocation.
 *	DEPRECATION: providing anything non-negative and nailing the base
 *	offset of GPIO chips is deprecated. Please pass -1 as base to
 *	let gpiolib select the chip base in all possible cases. We want to
 *	get rid of the static GPIO number space in the long run.
 * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 *	handled is (base + ngpio - 1).
 * @names: if set, must be an array of strings to use as alternative
 *      names for the GPIOs in this chip. Any entry in the array
 *      may be NULL if there is no alias for the GPIO, however the
 *      array must be @ngpio entries long.  A name can include a single printk
 *      format specifier for an unsigned int.  It is substituted by the actual
 *      number of the gpio.
 * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 *	must while accessing GPIO expander chips over I2C or SPI. This
 *	implies that if the chip supports IRQs, these IRQs need to be threaded
 *	as the chip access may sleep when e.g. reading out the IRQ status
 *	registers.
 * @read_reg: reader function for generic GPIO
 * @write_reg: writer function for generic GPIO
 * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
 *	line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
 *	generic GPIO core. It is for internal housekeeping only.
 * @reg_dat: data (in) register for generic GPIO
 * @reg_set: output set register (out=high) for generic GPIO
 * @reg_clr: output clear register (out=low) for generic GPIO
 * @reg_dir: direction setting register for generic GPIO
 * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 *	<register width> * 8
 * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 *	shadowed and real data registers writes together.
 * @bgpio_data:	shadowed data register for generic GPIO to clear/set bits
 *	safely.
 * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 *	direction safely.
 *
 * A gpio_chip can help platforms abstract various sources of GPIOs so
 * they can all be accessed through a common programing interface.
 * Example sources would be SOC controllers, FPGAs, multifunction
 * chips, dedicated GPIO expanders, and so on.
 *
 * Each chip controls a number of signals, identified in method calls
 * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 * are referenced through calls like gpio_get_value(gpio), the offset
 * is calculated by subtracting @base from the gpio number.
 */
struct gpio_chip {
	const char		*label;
	struct gpio_device	*gpiodev;
	struct device		*parent;
	struct module		*owner;

	int			(*request)(struct gpio_chip *chip,
						unsigned offset);
	void			(*free)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_direction)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_input)(struct gpio_chip *chip,
						unsigned offset);
	int			(*direction_output)(struct gpio_chip *chip,
						unsigned offset, int value);
	int			(*get)(struct gpio_chip *chip,
						unsigned offset);
	int			(*get_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	void			(*set)(struct gpio_chip *chip,
						unsigned offset, int value);
	void			(*set_multiple)(struct gpio_chip *chip,
						unsigned long *mask,
						unsigned long *bits);
	int			(*set_config)(struct gpio_chip *chip,
					      unsigned offset,
					      unsigned long config);
	int			(*to_irq)(struct gpio_chip *chip,
						unsigned offset);

	void			(*dbg_show)(struct seq_file *s,
						struct gpio_chip *chip);
	int			base;
	u16			ngpio;
	const char		*const *names;
	bool			can_sleep;

#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	unsigned long (*read_reg)(void __iomem *reg);
	void (*write_reg)(void __iomem *reg, unsigned long data);
	bool be_bits;
	void __iomem *reg_dat;
	void __iomem *reg_set;
	void __iomem *reg_clr;
	void __iomem *reg_dir;
	int bgpio_bits;
	spinlock_t bgpio_lock;
	unsigned long bgpio_data;
	unsigned long bgpio_dir;
#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP
	/*
	 * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
	 * to handle IRQs for most practical cases.
	 */

	/**
	 * @irq:
	 *
	 * Integrates interrupt chip functionality with the GPIO chip. Can be
	 * used to handle IRQs for most practical cases.
	 */
	struct gpio_irq_chip irq;
#endif

#if defined(CONFIG_OF_GPIO)
	/*
	 * If CONFIG_OF is enabled, then all GPIO controllers described in the
	 * device tree automatically may have an OF translation
	 */

	/**
	 * @of_node:
	 *
	 * Pointer to a device tree node representing this GPIO controller.
	 */
	struct device_node *of_node;

	/**
	 * @of_gpio_n_cells:
	 *
	 * Number of cells used to form the GPIO specifier.
	 */
	unsigned int of_gpio_n_cells;

	/**
	 * @of_xlate:
	 *
	 * Callback to translate a device tree GPIO specifier into a chip-
	 * relative GPIO number and flags.
	 */
	int (*of_xlate)(struct gpio_chip *gc,
			const struct of_phandle_args *gpiospec, u32 *flags);
#endif
};

extern const char *gpiochip_is_requested(struct gpio_chip *chip,
			unsigned offset);

/* add/remove chips */
extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
				      struct lock_class_key *lock_key);

/**
 * gpiochip_add_data() - register a gpio_chip
 * @chip: the chip to register, with chip->base initialized
 * @data: driver-private data associated with this chip
 *
 * Context: potentially before irqs will work
 *
 * When gpiochip_add_data() is called very early during boot, so that GPIOs
 * can be freely used, the chip->parent device must be registered before
 * the gpio framework's arch_initcall().  Otherwise sysfs initialization
 * for GPIOs will fail rudely.
 *
 * gpiochip_add_data() must only be called after gpiolib initialization,
 * ie after core_initcall().
 *
 * If chip->base is negative, this requests dynamic assignment of
 * a range of valid GPIOs.
 *
 * Returns:
 * A negative errno if the chip can't be registered, such as because the
 * chip->base is invalid or already associated with a different chip.
 * Otherwise it returns zero as a success code.
 */
#ifdef CONFIG_LOCKDEP
#define gpiochip_add_data(chip, data) ({		\
		static struct lock_class_key key;	\
		gpiochip_add_data_with_key(chip, data, &key);	\
	})
#else
#define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL)
#endif

static inline int gpiochip_add(struct gpio_chip *chip)
{
	return gpiochip_add_data(chip, NULL);
}
extern void gpiochip_remove(struct gpio_chip *chip);
extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
				  void *data);
extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);

extern struct gpio_chip *gpiochip_find(void *data,
			      int (*match)(struct gpio_chip *chip, void *data));

/* lock/unlock as IRQ */
int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);

/* Line status inquiry for drivers */
bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);

/* Sleep persistence inquiry for drivers */
bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);

/* get driver data */
void *gpiochip_get_data(struct gpio_chip *chip);

struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);

struct bgpio_pdata {
	const char *label;
	int base;
	int ngpio;
};

#if IS_ENABLED(CONFIG_GPIO_GENERIC)

int bgpio_init(struct gpio_chip *gc, struct device *dev,
	       unsigned long sz, void __iomem *dat, void __iomem *set,
	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
	       unsigned long flags);

#define BGPIOF_BIG_ENDIAN		BIT(0)
#define BGPIOF_UNREADABLE_REG_SET	BIT(1) /* reg_set is unreadable */
#define BGPIOF_UNREADABLE_REG_DIR	BIT(2) /* reg_dir is unreadable */
#define BGPIOF_BIG_ENDIAN_BYTE_ORDER	BIT(3)
#define BGPIOF_READ_OUTPUT_REG_SET	BIT(4) /* reg_set stores output value */
#define BGPIOF_NO_OUTPUT		BIT(5) /* only input */

#endif

#ifdef CONFIG_GPIOLIB_IRQCHIP

int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
		     irq_hw_number_t hwirq);
void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);

void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq,
		irq_flow_handler_t parent_handler);

void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
		struct irq_chip *irqchip,
		unsigned int parent_irq);

int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
			     struct irq_chip *irqchip,
			     unsigned int first_irq,
			     irq_flow_handler_t handler,
			     unsigned int type,
			     bool threaded,
			     struct lock_class_key *lock_key);

#ifdef CONFIG_LOCKDEP

/*
 * Lockdep requires that each irqchip instance be created with a
 * unique key so as to avoid unnecessary warnings. This upfront
 * boilerplate static inlines provides such a key for each
 * unique instance.
 */
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, &key);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{

	static struct lock_class_key key;

	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, &key);
}
#else
static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
				       struct irq_chip *irqchip,
				       unsigned int first_irq,
				       irq_flow_handler_t handler,
				       unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, false, NULL);
}

static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
			  struct irq_chip *irqchip,
			  unsigned int first_irq,
			  irq_flow_handler_t handler,
			  unsigned int type)
{
	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
					handler, type, true, NULL);
}
#endif /* CONFIG_LOCKDEP */

#endif /* CONFIG_GPIOLIB_IRQCHIP */

int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
			    unsigned long config);

#ifdef CONFIG_PINCTRL

/**
 * struct gpio_pin_range - pin range controlled by a gpio chip
 * @node: list for maintaining set of pin ranges, used internally
 * @pctldev: pinctrl device which handles corresponding pins
 * @range: actual range of pins controlled by a gpio controller
 */
struct gpio_pin_range {
	struct list_head node;
	struct pinctrl_dev *pctldev;
	struct pinctrl_gpio_range range;
};

int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
			   unsigned int gpio_offset, unsigned int pin_offset,
			   unsigned int npins);
int gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group);
void gpiochip_remove_pin_ranges(struct gpio_chip *chip);

#else

static inline int
gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
		       unsigned int gpio_offset, unsigned int pin_offset,
		       unsigned int npins)
{
	return 0;
}
static inline int
gpiochip_add_pingroup_range(struct gpio_chip *chip,
			struct pinctrl_dev *pctldev,
			unsigned int gpio_offset, const char *pin_group)
{
	return 0;
}

static inline void
gpiochip_remove_pin_ranges(struct gpio_chip *chip)
{
}

#endif /* CONFIG_PINCTRL */

struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
					    const char *label);
void gpiochip_free_own_desc(struct gpio_desc *desc);

#else /* CONFIG_GPIOLIB */

static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
{
	/* GPIO can never have been requested */
	WARN_ON(1);
	return ERR_PTR(-ENODEV);
}

#endif /* CONFIG_GPIOLIB */

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
79a9becd AC	2	#ifndef __LINUX_GPIO_DRIVER_H
	3	#define __LINUX_GPIO_DRIVER_H
	4
ff2b1359	5	#include <linux/device.h>
79a9becd	6	#include <linux/types.h>
14250520 LW	7	#include <linux/irq.h>
	8	#include <linux/irqchip/chained_irq.h>
	9	#include <linux/irqdomain.h>
a0a8bcf4	10	#include <linux/lockdep.h>
964cb341	11	#include <linux/pinctrl/pinctrl.h>
2956b5d9	12	#include <linux/pinctrl/pinconf-generic.h>
79a9becd	13
79a9becd	14	struct gpio_desc;
c9a9972b AC	15	struct of_phandle_args;
c9a9972b AC	16	struct device_node;
f3ed0b66	17	struct seq_file;
ff2b1359	18	struct gpio_device;
d47529b2	19	struct module;
79a9becd	20
bb1e88cc AC	21	#ifdef CONFIG_GPIOLIB
bb1e88cc AC	22
c44eafd7 TR	23	#ifdef CONFIG_GPIOLIB_IRQCHIP
	24	/**
	25	* struct gpio_irq_chip - GPIO interrupt controller
	26	*/
	27	struct gpio_irq_chip {
da80ff81 TR	28	/**
	29	* @chip:
	30	*
	31	* GPIO IRQ chip implementation, provided by GPIO driver.
	32	*/
	33	struct irq_chip *chip;
	34
f0fbe7bc TR	35	/**
	36	* @domain:
	37	*
	38	* Interrupt translation domain; responsible for mapping between GPIO
	39	* hwirq number and Linux IRQ number.
	40	*/
	41	struct irq_domain *domain;
	42
c44eafd7 TR	43	/**
	44	* @domain_ops:
	45	*
	46	* Table of interrupt domain operations for this IRQ chip.
	47	*/
	48	const struct irq_domain_ops *domain_ops;
	49
c7a0aa59 TR	50	/**
	51	* @handler:
	52	*
	53	* The IRQ handler to use (often a predefined IRQ core function) for
	54	* GPIO IRQs, provided by GPIO driver.
	55	*/
	56	irq_flow_handler_t handler;
	57
3634eeb0 TR	58	/**
	59	* @default_type:
	60	*
	61	* Default IRQ triggering type applied during GPIO driver
	62	* initialization, provided by GPIO driver.
	63	*/
	64	unsigned int default_type;
	65
ca9df053 TR	66	/**
	67	* @lock_key:
	68	*
	69	* Per GPIO IRQ chip lockdep class.
	70	*/
	71	struct lock_class_key *lock_key;
	72
c44eafd7 TR	73	/**
	74	* @parent_handler:
	75	*
	76	* The interrupt handler for the GPIO chip's parent interrupts, may be
	77	* NULL if the parent interrupts are nested rather than cascaded.
	78	*/
	79	irq_flow_handler_t parent_handler;
	80
	81	/**
	82	* @parent_handler_data:
	83	*
	84	* Data associated, and passed to, the handler for the parent
	85	* interrupt.
	86	*/
	87	void *parent_handler_data;
39e5f096 TR	88
	89	/**
	90	* @num_parents:
	91	*
	92	* The number of interrupt parents of a GPIO chip.
	93	*/
	94	unsigned int num_parents;
	95
	96	/**
	97	* @parents:
	98	*
	99	* A list of interrupt parents of a GPIO chip. This is owned by the
	100	* driver, so the core will only reference this list, not modify it.
	101	*/
	102	unsigned int *parents;
dc6bafee	103
e0d89728 TR	104	/**
	105	* @map:
	106	*
	107	* A list of interrupt parents for each line of a GPIO chip.
	108	*/
	109	unsigned int *map;
	110
dc6bafee	111	/**
60ed54ca	112	* @threaded:
dc6bafee	113	*
60ed54ca	114	* True if set the interrupt handling uses nested threads.
dc6bafee	115	*/
60ed54ca	116	bool threaded;
dc7b0387 TR	117
	118	/**
	119	* @need_valid_mask:
	120	*
	121	* If set core allocates @valid_mask with all bits set to one.
	122	*/
	123	bool need_valid_mask;
	124
	125	/**
	126	* @valid_mask:
	127	*
	128	* If not %NULL holds bitmask of GPIOs which are valid to be included
	129	* in IRQ domain of the chip.
	130	*/
	131	unsigned long *valid_mask;
8302cf58 TR	132
	133	/**
	134	* @first:
	135	*
	136	* Required for static IRQ allocation. If set, irq_domain_add_simple()
	137	* will allocate and map all IRQs during initialization.
	138	*/
	139	unsigned int first;
c44eafd7	140	};
da80ff81 TR	141
	142	static inline struct gpio_irq_chip to_gpio_irq_chip(struct irq_chip chip)
	143	{
	144	return container_of(chip, struct gpio_irq_chip, chip);
	145	}
c44eafd7 TR	146	#endif
c44eafd7 TR	147
79a9becd AC	148	/**
79a9becd AC	149	* struct gpio_chip - abstract a GPIO controller
df4878e9 LW	150	* @label: a functional name for the GPIO device, such as a part
df4878e9 LW	151	* number or the name of the SoC IP-block implementing it.
ff2b1359	152	* @gpiodev: the internal state holder, opaque struct
58383c78	153	* @parent: optional parent device providing the GPIOs
79a9becd	154	* @owner: helps prevent removal of modules exporting active GPIOs
79a9becd AC	155	* @request: optional hook for chip-specific activation, such as
	156	* enabling module power and clock; may sleep
	157	* @free: optional hook for chip-specific deactivation, such as
	158	* disabling module power and clock; may sleep
	159	* @get_direction: returns direction for signal "offset", 0=out, 1=in,
	160	* (same as GPIOF_DIR_XXX), or negative error
	161	* @direction_input: configures signal "offset" as input, or returns error
	162	* @direction_output: configures signal "offset" as output, or returns error
60befd2e	163	* @get: returns value for signal "offset", 0=low, 1=high, or negative error
eec1d566 LW	164	* @get_multiple: reads values for multiple signals defined by "mask" and
eec1d566 LW	165	* stores them in "bits", returns 0 on success or negative error
79a9becd	166	* @set: assigns output value for signal "offset"
5f424243	167	* @set_multiple: assigns output values for multiple signals defined by "mask"
2956b5d9 MW	168	* @set_config: optional hook for all kinds of settings. Uses the same
2956b5d9 MW	169	* packed config format as generic pinconf.
79a9becd AC	170	* @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
	171	* implementation may not sleep
	172	* @dbg_show: optional routine to show contents in debugfs; default code
	173	* will be used when this is omitted, but custom code can show extra
	174	* state (such as pullup/pulldown configuration).
af6c235d LW	175	* @base: identifies the first GPIO number handled by this chip;
	176	* or, if negative during registration, requests dynamic ID allocation.
	177	* DEPRECATION: providing anything non-negative and nailing the base
30bb6fb3	178	* offset of GPIO chips is deprecated. Please pass -1 as base to
af6c235d LW	179	* let gpiolib select the chip base in all possible cases. We want to
af6c235d LW	180	* get rid of the static GPIO number space in the long run.
79a9becd AC	181	* @ngpio: the number of GPIOs handled by this controller; the last GPIO
79a9becd AC	182	* handled is (base + ngpio - 1).
79a9becd AC	183	* @names: if set, must be an array of strings to use as alternative
	184	* names for the GPIOs in this chip. Any entry in the array
	185	* may be NULL if there is no alias for the GPIO, however the
	186	* array must be @ngpio entries long. A name can include a single printk
	187	* format specifier for an unsigned int. It is substituted by the actual
	188	* number of the gpio.
9fb1f39e	189	* @can_sleep: flag must be set iff get()/set() methods sleep, as they
1c8732bb LW	190	* must while accessing GPIO expander chips over I2C or SPI. This
	191	* implies that if the chip supports IRQs, these IRQs need to be threaded
	192	* as the chip access may sleep when e.g. reading out the IRQ status
	193	* registers.
0f4630f3 LW	194	* @read_reg: reader function for generic GPIO
0f4630f3 LW	195	* @write_reg: writer function for generic GPIO
24efd94b LW	196	* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
	197	* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
	198	* generic GPIO core. It is for internal housekeeping only.
0f4630f3 LW	199	* @reg_dat: data (in) register for generic GPIO
0f4630f3 LW	200	* @reg_set: output set register (out=high) for generic GPIO
08bcd3ed	201	* @reg_clr: output clear register (out=low) for generic GPIO
0f4630f3 LW	202	* @reg_dir: direction setting register for generic GPIO
	203	* @bgpio_bits: number of register bits used for a generic GPIO i.e.
	204	* <register width> * 8
	205	* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
	206	* shadowed and real data registers writes together.
	207	* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
	208	* safely.
	209	* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
	210	* direction safely.
79a9becd AC	211	*
	212	* A gpio_chip can help platforms abstract various sources of GPIOs so
	213	* they can all be accessed through a common programing interface.
	214	* Example sources would be SOC controllers, FPGAs, multifunction
	215	* chips, dedicated GPIO expanders, and so on.
	216	*
	217	* Each chip controls a number of signals, identified in method calls
	218	* by "offset" values in the range 0..(@ngpio - 1). When those signals
	219	* are referenced through calls like gpio_get_value(gpio), the offset
	220	* is calculated by subtracting @base from the gpio number.
	221	*/
	222	struct gpio_chip {
	223	const char *label;
ff2b1359	224	struct gpio_device *gpiodev;
58383c78	225	struct device *parent;
79a9becd	226	struct module *owner;
79a9becd AC	227
	228	int (request)(struct gpio_chip chip,
	229	unsigned offset);
	230	void (free)(struct gpio_chip chip,
	231	unsigned offset);
	232	int (get_direction)(struct gpio_chip chip,
	233	unsigned offset);
	234	int (direction_input)(struct gpio_chip chip,
	235	unsigned offset);
	236	int (direction_output)(struct gpio_chip chip,
	237	unsigned offset, int value);
	238	int (get)(struct gpio_chip chip,
	239	unsigned offset);
eec1d566 LW	240	int (get_multiple)(struct gpio_chip chip,
	241	unsigned long *mask,
	242	unsigned long *bits);
79a9becd AC	243	void (set)(struct gpio_chip chip,
79a9becd AC	244	unsigned offset, int value);
5f424243 RI	245	void (set_multiple)(struct gpio_chip chip,
	246	unsigned long *mask,
	247	unsigned long *bits);
2956b5d9 MW	248	int (set_config)(struct gpio_chip chip,
	249	unsigned offset,
	250	unsigned long config);
79a9becd AC	251	int (to_irq)(struct gpio_chip chip,
	252	unsigned offset);
	253
	254	void (dbg_show)(struct seq_file s,
	255	struct gpio_chip *chip);
	256	int base;
	257	u16 ngpio;
79a9becd	258	const char const names;
9fb1f39e	259	bool can_sleep;
79a9becd	260
0f4630f3 LW	261	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
	262	unsigned long (read_reg)(void __iomem reg);
	263	void (write_reg)(void __iomem reg, unsigned long data);
24efd94b	264	bool be_bits;
0f4630f3 LW	265	void __iomem *reg_dat;
	266	void __iomem *reg_set;
	267	void __iomem *reg_clr;
	268	void __iomem *reg_dir;
	269	int bgpio_bits;
	270	spinlock_t bgpio_lock;
	271	unsigned long bgpio_data;
	272	unsigned long bgpio_dir;
	273	#endif
	274
14250520 LW	275	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	276	/*
7d75a871	277	* With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
14250520 LW	278	* to handle IRQs for most practical cases.
14250520 LW	279	*/
c44eafd7 TR	280
	281	/**
	282	* @irq:
	283	*
	284	* Integrates interrupt chip functionality with the GPIO chip. Can be
	285	* used to handle IRQs for most practical cases.
	286	*/
	287	struct gpio_irq_chip irq;
14250520 LW	288	#endif
14250520 LW	289
79a9becd AC	290	#if defined(CONFIG_OF_GPIO)
	291	/*
	292	* If CONFIG_OF is enabled, then all GPIO controllers described in the
	293	* device tree automatically may have an OF translation
	294	*/
67049c50 TR	295
	296	/**
	297	* @of_node:
	298	*
	299	* Pointer to a device tree node representing this GPIO controller.
	300	*/
79a9becd	301	struct device_node *of_node;
67049c50 TR	302
	303	/**
	304	* @of_gpio_n_cells:
	305	*
	306	* Number of cells used to form the GPIO specifier.
	307	*/
e3b445d7	308	unsigned int of_gpio_n_cells;
67049c50 TR	309
	310	/**
	311	* @of_xlate:
	312	*
	313	* Callback to translate a device tree GPIO specifier into a chip-
	314	* relative GPIO number and flags.
	315	*/
79a9becd AC	316	int (of_xlate)(struct gpio_chip gc,
	317	const struct of_phandle_args gpiospec, u32 flags);
	318	#endif
79a9becd AC	319	};
	320
	321	extern const char gpiochip_is_requested(struct gpio_chip chip,
	322	unsigned offset);
	323
	324	/* add/remove chips */
959bc7b2 TR	325	extern int gpiochip_add_data_with_key(struct gpio_chip chip, void data,
	326	struct lock_class_key *lock_key);
	327
	328	/**
	329	* gpiochip_add_data() - register a gpio_chip
	330	* @chip: the chip to register, with chip->base initialized
	331	* @data: driver-private data associated with this chip
	332	*
	333	* Context: potentially before irqs will work
	334	*
	335	* When gpiochip_add_data() is called very early during boot, so that GPIOs
	336	* can be freely used, the chip->parent device must be registered before
	337	* the gpio framework's arch_initcall(). Otherwise sysfs initialization
	338	* for GPIOs will fail rudely.
	339	*
	340	* gpiochip_add_data() must only be called after gpiolib initialization,
	341	* ie after core_initcall().
	342	*
	343	* If chip->base is negative, this requests dynamic assignment of
	344	* a range of valid GPIOs.
	345	*
	346	* Returns:
	347	* A negative errno if the chip can't be registered, such as because the
	348	* chip->base is invalid or already associated with a different chip.
	349	* Otherwise it returns zero as a success code.
	350	*/
	351	#ifdef CONFIG_LOCKDEP
	352	#define gpiochip_add_data(chip, data) ({ \
	353	static struct lock_class_key key; \
	354	gpiochip_add_data_with_key(chip, data, &key); \
	355	})
	356	#else
	357	#define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL)
	358	#endif
	359
b08ea35a LW	360	static inline int gpiochip_add(struct gpio_chip *chip)
	361	{
	362	return gpiochip_add_data(chip, NULL);
	363	}
e1db1706	364	extern void gpiochip_remove(struct gpio_chip *chip);
0cf3292c LD	365	extern int devm_gpiochip_add_data(struct device dev, struct gpio_chip chip,
	366	void *data);
	367	extern void devm_gpiochip_remove(struct device dev, struct gpio_chip chip);
	368
79a9becd AC	369	extern struct gpio_chip gpiochip_find(void data,
	370	int (match)(struct gpio_chip chip, void *data));
	371
	372	/* lock/unlock as IRQ */
e3a2e878 AC	373	int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
e3a2e878 AC	374	void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
6cee3821	375	bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
79a9becd	376
143b65d6 LW	377	/* Line status inquiry for drivers */
	378	bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
	379	bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
	380
05f479bf CK	381	/* Sleep persistence inquiry for drivers */
	382	bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
	383
b08ea35a	384	/* get driver data */
43c54eca	385	void gpiochip_get_data(struct gpio_chip chip);
b08ea35a	386
bb1e88cc AC	387	struct gpio_chip gpiod_to_chip(const struct gpio_desc desc);
bb1e88cc AC	388
0f4630f3 LW	389	struct bgpio_pdata {
	390	const char *label;
	391	int base;
	392	int ngpio;
	393	};
	394
c474e348 AB	395	#if IS_ENABLED(CONFIG_GPIO_GENERIC)
c474e348 AB	396
0f4630f3 LW	397	int bgpio_init(struct gpio_chip gc, struct device dev,
	398	unsigned long sz, void __iomem dat, void __iomem set,
	399	void __iomem clr, void __iomem dirout, void __iomem *dirin,
	400	unsigned long flags);
	401
	402	#define BGPIOF_BIG_ENDIAN BIT(0)
	403	#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
	404	#define BGPIOF_UNREADABLE_REG_DIR BIT(2) /* reg_dir is unreadable */
	405	#define BGPIOF_BIG_ENDIAN_BYTE_ORDER BIT(3)
	406	#define BGPIOF_READ_OUTPUT_REG_SET BIT(4) /* reg_set stores output value */
	407	#define BGPIOF_NO_OUTPUT BIT(5) /* only input */
	408
	409	#endif
	410
14250520 LW	411	#ifdef CONFIG_GPIOLIB_IRQCHIP
14250520 LW	412
1b95b4eb TR	413	int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
	414	irq_hw_number_t hwirq);
	415	void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
	416
14250520 LW	417	void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
14250520 LW	418	struct irq_chip *irqchip,
6f79309a	419	unsigned int parent_irq,
14250520 LW	420	irq_flow_handler_t parent_handler);
14250520 LW	421
d245b3f9 LW	422	void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
d245b3f9 LW	423	struct irq_chip *irqchip,
6f79309a	424	unsigned int parent_irq);
d245b3f9	425
739e6f59 LW	426	int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
	427	struct irq_chip *irqchip,
	428	unsigned int first_irq,
	429	irq_flow_handler_t handler,
	430	unsigned int type,
60ed54ca	431	bool threaded,
739e6f59 LW	432	struct lock_class_key *lock_key);
	433
	434	#ifdef CONFIG_LOCKDEP
	435
	436	/*
	437	* Lockdep requires that each irqchip instance be created with a
	438	* unique key so as to avoid unnecessary warnings. This upfront
	439	* boilerplate static inlines provides such a key for each
	440	* unique instance.
	441	*/
	442	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	443	struct irq_chip *irqchip,
	444	unsigned int first_irq,
	445	irq_flow_handler_t handler,
	446	unsigned int type)
	447	{
	448	static struct lock_class_key key;
	449
	450	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	451	handler, type, false, &key);
	452	}
	453
	454	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
a0a8bcf4 GS	455	struct irq_chip *irqchip,
	456	unsigned int first_irq,
	457	irq_flow_handler_t handler,
739e6f59 LW	458	unsigned int type)
	459	{
	460
	461	static struct lock_class_key key;
	462
	463	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	464	handler, type, true, &key);
	465	}
	466	#else
	467	static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
	468	struct irq_chip *irqchip,
	469	unsigned int first_irq,
	470	irq_flow_handler_t handler,
	471	unsigned int type)
	472	{
	473	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
	474	handler, type, false, NULL);
	475	}
a0a8bcf4	476
d245b3f9 LW	477	static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
	478	struct irq_chip *irqchip,
	479	unsigned int first_irq,
	480	irq_flow_handler_t handler,
	481	unsigned int type)
	482	{
739e6f59 LW	483	return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
739e6f59 LW	484	handler, type, true, NULL);
d245b3f9	485	}
739e6f59	486	#endif /* CONFIG_LOCKDEP */
14250520	487
7d75a871	488	#endif /* CONFIG_GPIOLIB_IRQCHIP */
14250520	489
c771c2f4 JG	490	int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
c771c2f4 JG	491	void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
2956b5d9 MW	492	int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
2956b5d9 MW	493	unsigned long config);
c771c2f4	494
964cb341 LW	495	#ifdef CONFIG_PINCTRL
	496
	497	/**
	498	* struct gpio_pin_range - pin range controlled by a gpio chip
950d55f5	499	* @node: list for maintaining set of pin ranges, used internally
964cb341 LW	500	* @pctldev: pinctrl device which handles corresponding pins
	501	* @range: actual range of pins controlled by a gpio controller
	502	*/
964cb341 LW	503	struct gpio_pin_range {
	504	struct list_head node;
	505	struct pinctrl_dev *pctldev;
	506	struct pinctrl_gpio_range range;
	507	};
	508
	509	int gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	510	unsigned int gpio_offset, unsigned int pin_offset,
	511	unsigned int npins);
	512	int gpiochip_add_pingroup_range(struct gpio_chip *chip,
	513	struct pinctrl_dev *pctldev,
	514	unsigned int gpio_offset, const char *pin_group);
	515	void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
	516
	517	#else
	518
	519	static inline int
	520	gpiochip_add_pin_range(struct gpio_chip chip, const char pinctl_name,
	521	unsigned int gpio_offset, unsigned int pin_offset,
	522	unsigned int npins)
	523	{
	524	return 0;
	525	}
	526	static inline int
	527	gpiochip_add_pingroup_range(struct gpio_chip *chip,
	528	struct pinctrl_dev *pctldev,
	529	unsigned int gpio_offset, const char *pin_group)
	530	{
	531	return 0;
	532	}
	533
	534	static inline void
	535	gpiochip_remove_pin_ranges(struct gpio_chip *chip)
	536	{
	537	}
	538
	539	#endif /* CONFIG_PINCTRL */
	540
abdc08a3 AC	541	struct gpio_desc gpiochip_request_own_desc(struct gpio_chip chip, u16 hwnum,
abdc08a3 AC	542	const char *label);
f7d4ad98 GR	543	void gpiochip_free_own_desc(struct gpio_desc *desc);
f7d4ad98 GR	544
bb1e88cc AC	545	#else /* CONFIG_GPIOLIB */
	546
	547	static inline struct gpio_chip gpiod_to_chip(const struct gpio_desc desc)
	548	{
	549	/* GPIO can never have been requested */
	550	WARN_ON(1);
	551	return ERR_PTR(-ENODEV);
	552	}
	553
	554	#endif /* CONFIG_GPIOLIB */
	555
79a9becd	556	#endif