[linux-2.6-block.git] / include / linux / fsl-diu-fb.h

/*
 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 *  Freescale DIU Frame Buffer device driver
 *
 *  Authors: Hongjun Chen <hong-jun.chen@freescale.com>
 *           Paul Widmer <paul.widmer@freescale.com>
 *           Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
 *           York Sun <yorksun@freescale.com>
 *
 *   Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

#ifndef __FSL_DIU_FB_H__
#define __FSL_DIU_FB_H__

/* Arbitrary threshold to determine the allocation method
 * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
 */
#define MEM_ALLOC_THRESHOLD (1024*768*4+32)
/* Minimum value that the pixel clock can be set to in pico seconds
 * This is determined by platform clock/3 where the minimum platform
 * clock is 533MHz. This gives 5629 pico seconds.
 */
#define MIN_PIX_CLK 5629
#define MAX_PIX_CLK 96096

#include <linux/types.h>

struct mfb_alpha {
	int enable;
	int alpha;
};

struct mfb_chroma_key {
	int enable;
	__u8  red_max;
	__u8  green_max;
	__u8  blue_max;
	__u8  red_min;
	__u8  green_min;
	__u8  blue_min;
};

struct aoi_display_offset {
	int x_aoi_d;
	int y_aoi_d;
};

#define MFB_SET_CHROMA_KEY	_IOW('M', 1, struct mfb_chroma_key)
#define MFB_SET_BRIGHTNESS	_IOW('M', 3, __u8)

#define MFB_SET_ALPHA		0x80014d00
#define MFB_GET_ALPHA		0x40014d00
#define MFB_SET_AOID		0x80084d04
#define MFB_GET_AOID		0x40084d04
#define MFB_SET_PIXFMT		0x80014d08
#define MFB_GET_PIXFMT		0x40014d08

#define FBIOGET_GWINFO		0x46E0
#define FBIOPUT_GWINFO		0x46E1

#ifdef __KERNEL__
#include <linux/spinlock.h>

/*
 * These are the fields of area descriptor(in DDR memory) for every plane
 */
struct diu_ad {
	/* Word 0(32-bit) in DDR memory */
/* 	__u16 comp; */
/* 	__u16 pixel_s:2; */
/* 	__u16 pallete:1; */
/* 	__u16 red_c:2; */
/* 	__u16 green_c:2; */
/* 	__u16 blue_c:2; */
/* 	__u16 alpha_c:3; */
/* 	__u16 byte_f:1; */
/* 	__u16 res0:3; */

	__be32 pix_fmt; /* hard coding pixel format */

	/* Word 1(32-bit) in DDR memory */
	__le32 addr;

	/* Word 2(32-bit) in DDR memory */
/* 	__u32 delta_xs:11; */
/* 	__u32 res1:1; */
/* 	__u32 delta_ys:11; */
/* 	__u32 res2:1; */
/* 	__u32 g_alpha:8; */
	__le32 src_size_g_alpha;

	/* Word 3(32-bit) in DDR memory */
/* 	__u32 delta_xi:11; */
/* 	__u32 res3:5; */
/* 	__u32 delta_yi:11; */
/* 	__u32 res4:3; */
/* 	__u32 flip:2; */
	__le32 aoi_size;

	/* Word 4(32-bit) in DDR memory */
	/*__u32 offset_xi:11;
	__u32 res5:5;
	__u32 offset_yi:11;
	__u32 res6:5;
	*/
	__le32 offset_xyi;

	/* Word 5(32-bit) in DDR memory */
	/*__u32 offset_xd:11;
	__u32 res7:5;
	__u32 offset_yd:11;
	__u32 res8:5; */
	__le32 offset_xyd;


	/* Word 6(32-bit) in DDR memory */
	__u8 ckmax_r;
	__u8 ckmax_g;
	__u8 ckmax_b;
	__u8 res9;

	/* Word 7(32-bit) in DDR memory */
	__u8 ckmin_r;
	__u8 ckmin_g;
	__u8 ckmin_b;
	__u8 res10;
/* 	__u32 res10:8; */

	/* Word 8(32-bit) in DDR memory */
	__le32 next_ad;

	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
	__u32 paddr;
} __attribute__ ((packed));

/* DIU register map */
struct diu {
	__be32 desc[3];
	__be32 gamma;
	__be32 pallete;
	__be32 cursor;
	__be32 curs_pos;
	__be32 diu_mode;
	__be32 bgnd;
	__be32 bgnd_wb;
	__be32 disp_size;
	__be32 wb_size;
	__be32 wb_mem_addr;
	__be32 hsyn_para;
	__be32 vsyn_para;
	__be32 syn_pol;
	__be32 thresholds;
	__be32 int_status;
	__be32 int_mask;
	__be32 colorbar[8];
	__be32 filling;
	__be32 plut;
} __attribute__ ((packed));

struct diu_hw {
	struct diu *diu_reg;
	spinlock_t reg_lock;

	__u32 mode;		/* DIU operation mode */
};

struct diu_addr {
	__u8 __iomem *vaddr;	/* Virtual address */
	dma_addr_t paddr;	/* Physical address */
	__u32 	   offset;
};

struct diu_pool {
	struct diu_addr ad;
	struct diu_addr gamma;
	struct diu_addr pallete;
	struct diu_addr cursor;
};

#define FSL_DIU_BASE_OFFSET	0x2C000	/* Offset of DIU */
#define INT_LCDC		64	/* DIU interrupt number */

#define FSL_AOI_NUM	6	/* 5 AOIs and one dummy AOI */
				/* 1 for plane 0, 2 for plane 1&2 each */

/* Minimum X and Y resolutions */
#define MIN_XRES	64
#define MIN_YRES	64

/* HW cursor parameters */
#define MAX_CURS		32

/* Modes of operation of DIU */
#define MFB_MODE0	0	/* DIU off */
#define MFB_MODE1	1	/* All three planes output to display */
#define MFB_MODE2	2	/* Plane 1 to display, planes 2+3 written back*/
#define MFB_MODE3	3	/* All three planes written back to memory */
#define MFB_MODE4	4	/* Color bar generation */

/* INT_STATUS/INT_MASK field descriptions */
#define INT_VSYNC	0x01	/* Vsync interrupt  */
#define INT_VSYNC_WB	0x02	/* Vsync interrupt for write back operation */
#define INT_UNDRUN	0x04	/* Under run exception interrupt */
#define INT_PARERR	0x08	/* Display parameters error interrupt */
#define INT_LS_BF_VS	0x10	/* Lines before vsync. interrupt */

/* Panels'operation modes */
#define MFB_TYPE_OUTPUT	0	/* Panel output to display */
#define MFB_TYPE_OFF	1	/* Panel off */
#define MFB_TYPE_WB	2	/* Panel written back to memory */
#define MFB_TYPE_TEST	3	/* Panel generate color bar */

#endif /* __KERNEL__ */
#endif /* __FSL_DIU_FB_H__ */
Commit	Line	Data
9b53a9e2 YS	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* Freescale DIU Frame Buffer device driver
	5	*
	6	* Authors: Hongjun Chen <hong-jun.chen@freescale.com>
	7	* Paul Widmer <paul.widmer@freescale.com>
	8	* Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
	9	* York Sun <yorksun@freescale.com>
	10	*
	11	* Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
	12	*
	13	* This program is free software; you can redistribute it and/or modify it
	14	* under the terms of the GNU General Public License as published by the
	15	* Free Software Foundation; either version 2 of the License, or (at your
	16	* option) any later version.
	17	*
	18	*/
	19
	20	#ifndef __FSL_DIU_FB_H__
	21	#define __FSL_DIU_FB_H__
	22
	23	/* Arbitrary threshold to determine the allocation method
	24	* See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
	25	*/
	26	#define MEM_ALLOC_THRESHOLD (10247684+32)
	27	/* Minimum value that the pixel clock can be set to in pico seconds
	28	* This is determined by platform clock/3 where the minimum platform
	29	* clock is 533MHz. This gives 5629 pico seconds.
	30	*/
	31	#define MIN_PIX_CLK 5629
	32	#define MAX_PIX_CLK 96096
	33
	34	#include <linux/types.h>
	35
	36	struct mfb_alpha {
	37	int enable;
	38	int alpha;
	39	};
	40
	41	struct mfb_chroma_key {
	42	int enable;
	43	__u8 red_max;
	44	__u8 green_max;
	45	__u8 blue_max;
	46	__u8 red_min;
	47	__u8 green_min;
	48	__u8 blue_min;
	49	};
	50
	51	struct aoi_display_offset {
	52	int x_aoi_d;
	53	int y_aoi_d;
	54	};
	55
	56	#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
9b53a9e2 YS	57	#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
	58
	59	#define MFB_SET_ALPHA 0x80014d00
	60	#define MFB_GET_ALPHA 0x40014d00
	61	#define MFB_SET_AOID 0x80084d04
	62	#define MFB_GET_AOID 0x40084d04
	63	#define MFB_SET_PIXFMT 0x80014d08
	64	#define MFB_GET_PIXFMT 0x40014d08
	65
	66	#define FBIOGET_GWINFO 0x46E0
	67	#define FBIOPUT_GWINFO 0x46E1
	68
	69	#ifdef __KERNEL__
	70	#include <linux/spinlock.h>
	71
	72	/*
	73	* These are the fields of area descriptor(in DDR memory) for every plane
	74	*/
	75	struct diu_ad {
	76	/* Word 0(32-bit) in DDR memory */
	77	/* __u16 comp; */
	78	/* __u16 pixel_s:2; */
	79	/* __u16 pallete:1; */
	80	/* __u16 red_c:2; */
	81	/* __u16 green_c:2; */
	82	/* __u16 blue_c:2; */
	83	/* __u16 alpha_c:3; */
	84	/* __u16 byte_f:1; */
	85	/* __u16 res0:3; */
	86
	87	__be32 pix_fmt; /* hard coding pixel format */
	88
	89	/* Word 1(32-bit) in DDR memory */
	90	__le32 addr;
	91
	92	/* Word 2(32-bit) in DDR memory */
	93	/* __u32 delta_xs:11; */
	94	/* __u32 res1:1; */
	95	/* __u32 delta_ys:11; */
	96	/* __u32 res2:1; */
	97	/* __u32 g_alpha:8; */
	98	__le32 src_size_g_alpha;
	99
	100	/* Word 3(32-bit) in DDR memory */
	101	/* __u32 delta_xi:11; */
	102	/* __u32 res3:5; */
	103	/* __u32 delta_yi:11; */
	104	/* __u32 res4:3; */
	105	/* __u32 flip:2; */
	106	__le32 aoi_size;
	107
	108	/* Word 4(32-bit) in DDR memory */
	109	/*__u32 offset_xi:11;
	110	__u32 res5:5;
	111	__u32 offset_yi:11;
	112	__u32 res6:5;
	113	*/
	114	__le32 offset_xyi;
	115
	116	/* Word 5(32-bit) in DDR memory */
	117	/*__u32 offset_xd:11;
	118	__u32 res7:5;
	119	__u32 offset_yd:11;
	120	__u32 res8:5; */
121	__le32 offset_xyd;
122
123
124	/* Word 6(32-bit) in DDR memory */
125	__u8 ckmax_r;
126	__u8 ckmax_g;
127	__u8 ckmax_b;
128	__u8 res9;
129
130	/* Word 7(32-bit) in DDR memory */
131	__u8 ckmin_r;
132	__u8 ckmin_g;
133	__u8 ckmin_b;
134	__u8 res10;
135	/* __u32 res10:8; */
136
137	/* Word 8(32-bit) in DDR memory */
138	__le32 next_ad;
139
140	/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
141	__u32 paddr;
142	} __attribute__ ((packed));
143
144	/* DIU register map */
145	struct diu {
146	__be32 desc[3];
147	__be32 gamma;
148	__be32 pallete;
149	__be32 cursor;
150	__be32 curs_pos;
151	__be32 diu_mode;
152	__be32 bgnd;
153	__be32 bgnd_wb;
154	__be32 disp_size;
155	__be32 wb_size;
156	__be32 wb_mem_addr;
157	__be32 hsyn_para;
158	__be32 vsyn_para;
159	__be32 syn_pol;
160	__be32 thresholds;
161	__be32 int_status;
162	__be32 int_mask;
163	__be32 colorbar[8];
164	__be32 filling;
165	__be32 plut;
166	} __attribute__ ((packed));
167
168	struct diu_hw {
169	struct diu *diu_reg;
170	spinlock_t reg_lock;
171
172	__u32 mode; /* DIU operation mode */
173	};
174
175	struct diu_addr {
176	__u8 __iomem vaddr; / Virtual address */
177	dma_addr_t paddr; /* Physical address */
178	__u32 offset;
179	};
180
181	struct diu_pool {
182	struct diu_addr ad;
183	struct diu_addr gamma;
184	struct diu_addr pallete;
185	struct diu_addr cursor;
186	};
187
188	#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
189	#define INT_LCDC 64 /* DIU interrupt number */
190
191	#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
192	/* 1 for plane 0, 2 for plane 1&2 each */
193
194	/* Minimum X and Y resolutions */
195	#define MIN_XRES 64
196	#define MIN_YRES 64
197
198	/* HW cursor parameters */
199	#define MAX_CURS 32
200
201	/* Modes of operation of DIU */
202	#define MFB_MODE0 0 /* DIU off */
203	#define MFB_MODE1 1 /* All three planes output to display */
204	#define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
205	#define MFB_MODE3 3 /* All three planes written back to memory */
206	#define MFB_MODE4 4 /* Color bar generation */
207
208	/* INT_STATUS/INT_MASK field descriptions */
209	#define INT_VSYNC 0x01 /* Vsync interrupt */
210	#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
211	#define INT_UNDRUN 0x04 /* Under run exception interrupt */
212	#define INT_PARERR 0x08 /* Display parameters error interrupt */
213	#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
214
215	/* Panels'operation modes */
216	#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
217	#define MFB_TYPE_OFF 1 /* Panel off */
218	#define MFB_TYPE_WB 2 /* Panel written back to memory */
219	#define MFB_TYPE_TEST 3 /* Panel generate color bar */
220
221	#endif /* __KERNEL__ */
222	#endif /* __FSL_DIU_FB_H__ */