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473f01f7 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
6a8c3be7 AT |
2 | /* |
3 | * FPGA Framework | |
4 | * | |
5cf0c7f6 AT |
5 | * Copyright (C) 2013-2016 Altera Corporation |
6 | * Copyright (C) 2017 Intel Corporation | |
6a8c3be7 | 7 | */ |
6a8c3be7 AT |
8 | #ifndef _LINUX_FPGA_MGR_H |
9 | #define _LINUX_FPGA_MGR_H | |
10 | ||
5cf0c7f6 AT |
11 | #include <linux/mutex.h> |
12 | #include <linux/platform_device.h> | |
13 | ||
6a8c3be7 | 14 | struct fpga_manager; |
baa6d396 | 15 | struct sg_table; |
6a8c3be7 AT |
16 | |
17 | /** | |
18 | * enum fpga_mgr_states - fpga framework states | |
19 | * @FPGA_MGR_STATE_UNKNOWN: can't determine state | |
20 | * @FPGA_MGR_STATE_POWER_OFF: FPGA power is off | |
21 | * @FPGA_MGR_STATE_POWER_UP: FPGA reports power is up | |
22 | * @FPGA_MGR_STATE_RESET: FPGA in reset state | |
23 | * @FPGA_MGR_STATE_FIRMWARE_REQ: firmware request in progress | |
24 | * @FPGA_MGR_STATE_FIRMWARE_REQ_ERR: firmware request failed | |
25 | * @FPGA_MGR_STATE_WRITE_INIT: preparing FPGA for programming | |
26 | * @FPGA_MGR_STATE_WRITE_INIT_ERR: Error during WRITE_INIT stage | |
27 | * @FPGA_MGR_STATE_WRITE: writing image to FPGA | |
28 | * @FPGA_MGR_STATE_WRITE_ERR: Error while writing FPGA | |
29 | * @FPGA_MGR_STATE_WRITE_COMPLETE: Doing post programming steps | |
30 | * @FPGA_MGR_STATE_WRITE_COMPLETE_ERR: Error during WRITE_COMPLETE | |
31 | * @FPGA_MGR_STATE_OPERATING: FPGA is programmed and operating | |
32 | */ | |
33 | enum fpga_mgr_states { | |
34 | /* default FPGA states */ | |
35 | FPGA_MGR_STATE_UNKNOWN, | |
36 | FPGA_MGR_STATE_POWER_OFF, | |
37 | FPGA_MGR_STATE_POWER_UP, | |
38 | FPGA_MGR_STATE_RESET, | |
39 | ||
40 | /* getting an image for loading */ | |
41 | FPGA_MGR_STATE_FIRMWARE_REQ, | |
42 | FPGA_MGR_STATE_FIRMWARE_REQ_ERR, | |
43 | ||
44 | /* write sequence: init, write, complete */ | |
45 | FPGA_MGR_STATE_WRITE_INIT, | |
46 | FPGA_MGR_STATE_WRITE_INIT_ERR, | |
47 | FPGA_MGR_STATE_WRITE, | |
48 | FPGA_MGR_STATE_WRITE_ERR, | |
49 | FPGA_MGR_STATE_WRITE_COMPLETE, | |
50 | FPGA_MGR_STATE_WRITE_COMPLETE_ERR, | |
51 | ||
52 | /* fpga is programmed and operating */ | |
53 | FPGA_MGR_STATE_OPERATING, | |
54 | }; | |
55 | ||
56 | /* | |
57 | * FPGA Manager flags | |
58 | * FPGA_MGR_PARTIAL_RECONFIG: do partial reconfiguration if supported | |
0fa20cdf | 59 | * FPGA_MGR_EXTERNAL_CONFIG: FPGA has been configured prior to Linux booting |
68f6be65 | 60 | * FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first |
b37fa560 | 61 | * FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed |
6a8c3be7 AT |
62 | */ |
63 | #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) | |
0fa20cdf | 64 | #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) |
0f4f0c8f | 65 | #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) |
68f6be65 | 66 | #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) |
b37fa560 | 67 | #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) |
6a8c3be7 | 68 | |
1df2865f AT |
69 | /** |
70 | * struct fpga_image_info - information specific to a FPGA image | |
71 | * @flags: boolean flags as defined above | |
72 | * @enable_timeout_us: maximum time to enable traffic through bridge (uSec) | |
73 | * @disable_timeout_us: maximum time to disable traffic through bridge (uSec) | |
42d5ec95 AT |
74 | * @config_complete_timeout_us: maximum time for FPGA to switch to operating |
75 | * status in the write_complete op. | |
5cf0c7f6 AT |
76 | * @firmware_name: name of FPGA image firmware file |
77 | * @sgt: scatter/gather table containing FPGA image | |
78 | * @buf: contiguous buffer containing FPGA image | |
79 | * @count: size of buf | |
571d78bd | 80 | * @region_id: id of target region |
5cf0c7f6 | 81 | * @dev: device that owns this |
61c32102 | 82 | * @overlay: Device Tree overlay |
1df2865f AT |
83 | */ |
84 | struct fpga_image_info { | |
85 | u32 flags; | |
86 | u32 enable_timeout_us; | |
87 | u32 disable_timeout_us; | |
42d5ec95 | 88 | u32 config_complete_timeout_us; |
5cf0c7f6 AT |
89 | char *firmware_name; |
90 | struct sg_table *sgt; | |
91 | const char *buf; | |
92 | size_t count; | |
571d78bd | 93 | int region_id; |
5cf0c7f6 | 94 | struct device *dev; |
61c32102 AT |
95 | #ifdef CONFIG_OF |
96 | struct device_node *overlay; | |
97 | #endif | |
1df2865f AT |
98 | }; |
99 | ||
6a8c3be7 AT |
100 | /** |
101 | * struct fpga_manager_ops - ops for low level fpga manager drivers | |
1d7f1589 | 102 | * @initial_header_size: Maximum number of bytes that should be passed into write_init |
6a8c3be7 | 103 | * @state: returns an enum value of the FPGA's state |
ecb5fbe2 | 104 | * @status: returns status of the FPGA, including reconfiguration error code |
6a8c3be7 AT |
105 | * @write_init: prepare the FPGA to receive confuration data |
106 | * @write: write count bytes of configuration data to the FPGA | |
baa6d396 | 107 | * @write_sg: write the scatter list of configuration data to the FPGA |
6a8c3be7 AT |
108 | * @write_complete: set FPGA to operating state after writing is done |
109 | * @fpga_remove: optional: Set FPGA into a specific state during driver remove | |
845089bb | 110 | * @groups: optional attribute groups. |
6a8c3be7 AT |
111 | * |
112 | * fpga_manager_ops are the low level functions implemented by a specific | |
113 | * fpga manager driver. The optional ones are tested for NULL before being | |
114 | * called, so leaving them out is fine. | |
115 | */ | |
116 | struct fpga_manager_ops { | |
1d7f1589 | 117 | size_t initial_header_size; |
6a8c3be7 | 118 | enum fpga_mgr_states (*state)(struct fpga_manager *mgr); |
ecb5fbe2 | 119 | u64 (*status)(struct fpga_manager *mgr); |
1df2865f AT |
120 | int (*write_init)(struct fpga_manager *mgr, |
121 | struct fpga_image_info *info, | |
6a8c3be7 AT |
122 | const char *buf, size_t count); |
123 | int (*write)(struct fpga_manager *mgr, const char *buf, size_t count); | |
baa6d396 | 124 | int (*write_sg)(struct fpga_manager *mgr, struct sg_table *sgt); |
1df2865f AT |
125 | int (*write_complete)(struct fpga_manager *mgr, |
126 | struct fpga_image_info *info); | |
6a8c3be7 | 127 | void (*fpga_remove)(struct fpga_manager *mgr); |
845089bb | 128 | const struct attribute_group **groups; |
6a8c3be7 AT |
129 | }; |
130 | ||
ecb5fbe2 WH |
131 | /* FPGA manager status: Partial/Full Reconfiguration errors */ |
132 | #define FPGA_MGR_STATUS_OPERATION_ERR BIT(0) | |
133 | #define FPGA_MGR_STATUS_CRC_ERR BIT(1) | |
134 | #define FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR BIT(2) | |
135 | #define FPGA_MGR_STATUS_IP_PROTOCOL_ERR BIT(3) | |
136 | #define FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR BIT(4) | |
137 | ||
99a560bd WH |
138 | /** |
139 | * struct fpga_compat_id - id for compatibility check | |
140 | * | |
141 | * @id_h: high 64bit of the compat_id | |
142 | * @id_l: low 64bit of the compat_id | |
143 | */ | |
144 | struct fpga_compat_id { | |
145 | u64 id_h; | |
146 | u64 id_l; | |
147 | }; | |
148 | ||
6a8c3be7 AT |
149 | /** |
150 | * struct fpga_manager - fpga manager structure | |
151 | * @name: name of low level fpga manager | |
152 | * @dev: fpga manager device | |
153 | * @ref_mutex: only allows one reference to fpga manager | |
154 | * @state: state of fpga manager | |
99a560bd | 155 | * @compat_id: FPGA manager id for compatibility check. |
6a8c3be7 AT |
156 | * @mops: pointer to struct of fpga manager ops |
157 | * @priv: low level driver private date | |
158 | */ | |
159 | struct fpga_manager { | |
160 | const char *name; | |
161 | struct device dev; | |
162 | struct mutex ref_mutex; | |
163 | enum fpga_mgr_states state; | |
99a560bd | 164 | struct fpga_compat_id *compat_id; |
6a8c3be7 AT |
165 | const struct fpga_manager_ops *mops; |
166 | void *priv; | |
167 | }; | |
168 | ||
169 | #define to_fpga_manager(d) container_of(d, struct fpga_manager, dev) | |
170 | ||
5cf0c7f6 AT |
171 | struct fpga_image_info *fpga_image_info_alloc(struct device *dev); |
172 | ||
173 | void fpga_image_info_free(struct fpga_image_info *info); | |
6a8c3be7 | 174 | |
5cf0c7f6 | 175 | int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info); |
6a8c3be7 | 176 | |
ebf877a5 AT |
177 | int fpga_mgr_lock(struct fpga_manager *mgr); |
178 | void fpga_mgr_unlock(struct fpga_manager *mgr); | |
179 | ||
6a8c3be7 AT |
180 | struct fpga_manager *of_fpga_mgr_get(struct device_node *node); |
181 | ||
9dce0287 AT |
182 | struct fpga_manager *fpga_mgr_get(struct device *dev); |
183 | ||
6a8c3be7 AT |
184 | void fpga_mgr_put(struct fpga_manager *mgr); |
185 | ||
7085e2a9 AT |
186 | struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name, |
187 | const struct fpga_manager_ops *mops, | |
188 | void *priv); | |
189 | void fpga_mgr_free(struct fpga_manager *mgr); | |
190 | int fpga_mgr_register(struct fpga_manager *mgr); | |
191 | void fpga_mgr_unregister(struct fpga_manager *mgr); | |
6a8c3be7 AT |
192 | |
193 | #endif /*_LINUX_FPGA_MGR_H */ |