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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
1531a6a6 | 27 | #include <linux/irqreturn.h> |
10e5247f | 28 | |
ba395927 | 29 | struct intel_iommu; |
29b61be6 | 30 | #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) |
2ae21010 SS |
31 | struct dmar_drhd_unit { |
32 | struct list_head list; /* list of drhd units */ | |
33 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
34 | u64 reg_base_addr; /* register base address*/ | |
35 | struct pci_dev **devices; /* target device array */ | |
36 | int devices_cnt; /* target device count */ | |
276dbf99 | 37 | u16 segment; /* PCI domain */ |
2ae21010 SS |
38 | u8 ignored:1; /* ignore drhd */ |
39 | u8 include_all:1; | |
40 | struct intel_iommu *iommu; | |
41 | }; | |
42 | ||
43 | extern struct list_head dmar_drhd_units; | |
44 | ||
45 | #define for_each_drhd_unit(drhd) \ | |
46 | list_for_each_entry(drhd, &dmar_drhd_units, list) | |
47 | ||
8f912ba4 DW |
48 | #define for_each_active_iommu(i, drhd) \ |
49 | list_for_each_entry(drhd, &dmar_drhd_units, list) \ | |
50 | if (i=drhd->iommu, drhd->ignored) {} else | |
51 | ||
52 | #define for_each_iommu(i, drhd) \ | |
53 | list_for_each_entry(drhd, &dmar_drhd_units, list) \ | |
54 | if (i=drhd->iommu, 0) {} else | |
55 | ||
2ae21010 | 56 | extern int dmar_table_init(void); |
2ae21010 SS |
57 | extern int dmar_dev_scope_init(void); |
58 | ||
59 | /* Intel IOMMU detection */ | |
60 | extern void detect_intel_iommu(void); | |
9d783ba0 | 61 | extern int enable_drhd_fault_handling(void); |
2ae21010 | 62 | |
2ae21010 SS |
63 | extern int parse_ioapics_under_ir(void); |
64 | extern int alloc_iommu(struct dmar_drhd_unit *); | |
65 | #else | |
66 | static inline void detect_intel_iommu(void) | |
67 | { | |
68 | return; | |
69 | } | |
70 | ||
71 | static inline int dmar_table_init(void) | |
72 | { | |
73 | return -ENODEV; | |
74 | } | |
29b61be6 SS |
75 | static inline int enable_drhd_fault_handling(void) |
76 | { | |
77 | return -1; | |
78 | } | |
2ae21010 SS |
79 | #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */ |
80 | ||
2ae21010 SS |
81 | struct irte { |
82 | union { | |
83 | struct { | |
84 | __u64 present : 1, | |
85 | fpd : 1, | |
86 | dst_mode : 1, | |
87 | redir_hint : 1, | |
88 | trigger_mode : 1, | |
89 | dlvry_mode : 3, | |
90 | avail : 4, | |
91 | __reserved_1 : 4, | |
92 | vector : 8, | |
93 | __reserved_2 : 8, | |
94 | dest_id : 32; | |
95 | }; | |
96 | __u64 low; | |
97 | }; | |
98 | ||
99 | union { | |
100 | struct { | |
101 | __u64 sid : 16, | |
102 | sq : 2, | |
103 | svt : 2, | |
104 | __reserved_3 : 44; | |
105 | }; | |
106 | __u64 high; | |
107 | }; | |
108 | }; | |
29b61be6 SS |
109 | #ifdef CONFIG_INTR_REMAP |
110 | extern int intr_remapping_enabled; | |
111 | extern int enable_intr_remapping(int); | |
b24696bc FY |
112 | extern void disable_intr_remapping(void); |
113 | extern int reenable_intr_remapping(int); | |
29b61be6 | 114 | |
b6fcb33a SS |
115 | extern int get_irte(int irq, struct irte *entry); |
116 | extern int modify_irte(int irq, struct irte *irte_modified); | |
117 | extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count); | |
118 | extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, | |
119 | u16 sub_handle); | |
120 | extern int map_irq_to_irte_handle(int irq, u16 *sub_handle); | |
121 | extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index); | |
122 | extern int flush_irte(int irq); | |
123 | extern int free_irte(int irq); | |
124 | ||
125 | extern int irq_remapped(int irq); | |
75c46fa6 | 126 | extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev); |
89027d35 | 127 | extern struct intel_iommu *map_ioapic_to_ir(int apic); |
2ae21010 | 128 | #else |
29b61be6 SS |
129 | static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
130 | { | |
131 | return -1; | |
132 | } | |
133 | static inline int modify_irte(int irq, struct irte *irte_modified) | |
134 | { | |
135 | return -1; | |
136 | } | |
137 | static inline int free_irte(int irq) | |
138 | { | |
139 | return -1; | |
140 | } | |
141 | static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
142 | { | |
143 | return -1; | |
144 | } | |
145 | static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, | |
146 | u16 sub_handle) | |
147 | { | |
148 | return -1; | |
149 | } | |
150 | static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) | |
151 | { | |
152 | return NULL; | |
153 | } | |
154 | static inline struct intel_iommu *map_ioapic_to_ir(int apic) | |
155 | { | |
156 | return NULL; | |
157 | } | |
b6fcb33a | 158 | #define irq_remapped(irq) (0) |
2ae21010 SS |
159 | #define enable_intr_remapping(mode) (-1) |
160 | #define intr_remapping_enabled (0) | |
161 | #endif | |
162 | ||
3460a6d9 KA |
163 | /* Can't use the common MSI interrupt functions |
164 | * since DMAR is not a pci device | |
165 | */ | |
166 | extern void dmar_msi_unmask(unsigned int irq); | |
167 | extern void dmar_msi_mask(unsigned int irq); | |
168 | extern void dmar_msi_read(int irq, struct msi_msg *msg); | |
169 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
170 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 171 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
3460a6d9 KA |
172 | extern int arch_setup_dmar_msi(unsigned int irq); |
173 | ||
9d783ba0 | 174 | #ifdef CONFIG_DMAR |
2ae21010 | 175 | extern int iommu_detected, no_iommu; |
10e5247f | 176 | extern struct list_head dmar_rmrr_units; |
10e5247f KA |
177 | struct dmar_rmrr_unit { |
178 | struct list_head list; /* list of rmrr units */ | |
1886e8a9 | 179 | struct acpi_dmar_header *hdr; /* ACPI header */ |
10e5247f KA |
180 | u64 base_address; /* reserved base address*/ |
181 | u64 end_address; /* reserved end address */ | |
182 | struct pci_dev **devices; /* target devices */ | |
183 | int devices_cnt; /* target device count */ | |
184 | }; | |
185 | ||
ba395927 KA |
186 | #define for_each_rmrr_units(rmrr) \ |
187 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
2ae21010 SS |
188 | /* Intel DMAR initialization functions */ |
189 | extern int intel_iommu_init(void); | |
ba395927 | 190 | #else |
ba395927 KA |
191 | static inline int intel_iommu_init(void) |
192 | { | |
2ae21010 SS |
193 | #ifdef CONFIG_INTR_REMAP |
194 | return dmar_dev_scope_init(); | |
195 | #else | |
ba395927 | 196 | return -ENODEV; |
2ae21010 | 197 | #endif |
1886e8a9 | 198 | } |
ba395927 | 199 | #endif /* !CONFIG_DMAR */ |
10e5247f | 200 | #endif /* __DMAR_H__ */ |