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10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
17 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> | |
18 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
19 | */ | |
20 | ||
21 | #ifndef __DMAR_H__ | |
22 | #define __DMAR_H__ | |
23 | ||
24 | #include <linux/acpi.h> | |
25 | #include <linux/types.h> | |
ba395927 | 26 | #include <linux/msi.h> |
10e5247f | 27 | |
2ae21010 | 28 | #if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP) |
ba395927 KA |
29 | struct intel_iommu; |
30 | ||
2ae21010 SS |
31 | struct dmar_drhd_unit { |
32 | struct list_head list; /* list of drhd units */ | |
33 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
34 | u64 reg_base_addr; /* register base address*/ | |
35 | struct pci_dev **devices; /* target device array */ | |
36 | int devices_cnt; /* target device count */ | |
37 | u8 ignored:1; /* ignore drhd */ | |
38 | u8 include_all:1; | |
39 | struct intel_iommu *iommu; | |
40 | }; | |
41 | ||
42 | extern struct list_head dmar_drhd_units; | |
43 | ||
44 | #define for_each_drhd_unit(drhd) \ | |
45 | list_for_each_entry(drhd, &dmar_drhd_units, list) | |
46 | ||
47 | extern int dmar_table_init(void); | |
48 | extern int early_dmar_detect(void); | |
49 | extern int dmar_dev_scope_init(void); | |
50 | ||
51 | /* Intel IOMMU detection */ | |
52 | extern void detect_intel_iommu(void); | |
53 | ||
54 | ||
55 | extern int parse_ioapics_under_ir(void); | |
56 | extern int alloc_iommu(struct dmar_drhd_unit *); | |
57 | #else | |
58 | static inline void detect_intel_iommu(void) | |
59 | { | |
60 | return; | |
61 | } | |
62 | ||
63 | static inline int dmar_table_init(void) | |
64 | { | |
65 | return -ENODEV; | |
66 | } | |
67 | #endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */ | |
68 | ||
69 | #ifdef CONFIG_INTR_REMAP | |
70 | extern int intr_remapping_enabled; | |
71 | extern int enable_intr_remapping(int); | |
72 | ||
73 | struct irte { | |
74 | union { | |
75 | struct { | |
76 | __u64 present : 1, | |
77 | fpd : 1, | |
78 | dst_mode : 1, | |
79 | redir_hint : 1, | |
80 | trigger_mode : 1, | |
81 | dlvry_mode : 3, | |
82 | avail : 4, | |
83 | __reserved_1 : 4, | |
84 | vector : 8, | |
85 | __reserved_2 : 8, | |
86 | dest_id : 32; | |
87 | }; | |
88 | __u64 low; | |
89 | }; | |
90 | ||
91 | union { | |
92 | struct { | |
93 | __u64 sid : 16, | |
94 | sq : 2, | |
95 | svt : 2, | |
96 | __reserved_3 : 44; | |
97 | }; | |
98 | __u64 high; | |
99 | }; | |
100 | }; | |
101 | #else | |
102 | #define enable_intr_remapping(mode) (-1) | |
103 | #define intr_remapping_enabled (0) | |
104 | #endif | |
105 | ||
106 | #ifdef CONFIG_DMAR | |
d94afc6c | 107 | extern const char *dmar_get_fault_reason(u8 fault_reason); |
3460a6d9 KA |
108 | |
109 | /* Can't use the common MSI interrupt functions | |
110 | * since DMAR is not a pci device | |
111 | */ | |
112 | extern void dmar_msi_unmask(unsigned int irq); | |
113 | extern void dmar_msi_mask(unsigned int irq); | |
114 | extern void dmar_msi_read(int irq, struct msi_msg *msg); | |
115 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
116 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
117 | extern int arch_setup_dmar_msi(unsigned int irq); | |
118 | ||
2ae21010 | 119 | extern int iommu_detected, no_iommu; |
10e5247f | 120 | extern struct list_head dmar_rmrr_units; |
10e5247f KA |
121 | struct dmar_rmrr_unit { |
122 | struct list_head list; /* list of rmrr units */ | |
1886e8a9 | 123 | struct acpi_dmar_header *hdr; /* ACPI header */ |
10e5247f KA |
124 | u64 base_address; /* reserved base address*/ |
125 | u64 end_address; /* reserved end address */ | |
126 | struct pci_dev **devices; /* target devices */ | |
127 | int devices_cnt; /* target device count */ | |
128 | }; | |
129 | ||
ba395927 KA |
130 | #define for_each_rmrr_units(rmrr) \ |
131 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
2ae21010 SS |
132 | /* Intel DMAR initialization functions */ |
133 | extern int intel_iommu_init(void); | |
134 | extern int dmar_disabled; | |
ba395927 | 135 | #else |
ba395927 KA |
136 | static inline int intel_iommu_init(void) |
137 | { | |
2ae21010 SS |
138 | #ifdef CONFIG_INTR_REMAP |
139 | return dmar_dev_scope_init(); | |
140 | #else | |
ba395927 | 141 | return -ENODEV; |
2ae21010 | 142 | #endif |
1886e8a9 | 143 | } |
ba395927 | 144 | #endif /* !CONFIG_DMAR */ |
10e5247f | 145 | #endif /* __DMAR_H__ */ |