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3b20eb23 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
10e5247f KA |
2 | /* |
3 | * Copyright (c) 2006, Intel Corporation. | |
4 | * | |
10e5247f KA |
5 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> |
6 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
7 | */ | |
8 | ||
9 | #ifndef __DMAR_H__ | |
10 | #define __DMAR_H__ | |
11 | ||
12 | #include <linux/acpi.h> | |
13 | #include <linux/types.h> | |
ba395927 | 14 | #include <linux/msi.h> |
1531a6a6 | 15 | #include <linux/irqreturn.h> |
3a5670e8 | 16 | #include <linux/rwsem.h> |
b2d09103 | 17 | #include <linux/rculist.h> |
10e5247f | 18 | |
6eea69dd AM |
19 | struct acpi_dmar_header; |
20 | ||
25357900 | 21 | #define DMAR_UNITS_SUPPORTED 1024 |
78d8e704 | 22 | |
41750d31 SS |
23 | /* DMAR Flags */ |
24 | #define DMAR_INTR_REMAP 0x1 | |
25 | #define DMAR_X2APIC_OPT_OUT 0x2 | |
89a6079d | 26 | #define DMAR_PLATFORM_OPT_IN 0x4 |
41750d31 | 27 | |
ba395927 | 28 | struct intel_iommu; |
694835dc | 29 | |
832bd858 DW |
30 | struct dmar_dev_scope { |
31 | struct device __rcu *dev; | |
32 | u8 bus; | |
33 | u8 devfn; | |
34 | }; | |
35 | ||
d3f13810 | 36 | #ifdef CONFIG_DMAR_TABLE |
41750d31 | 37 | extern struct acpi_table_header *dmar_tbl; |
2ae21010 SS |
38 | struct dmar_drhd_unit { |
39 | struct list_head list; /* list of drhd units */ | |
40 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
41 | u64 reg_base_addr; /* register base address*/ | |
4db96bfe | 42 | unsigned long reg_size; /* size of register set */ |
832bd858 | 43 | struct dmar_dev_scope *devices;/* target device array */ |
2ae21010 | 44 | int devices_cnt; /* target device count */ |
276dbf99 | 45 | u16 segment; /* PCI domain */ |
2ae21010 SS |
46 | u8 ignored:1; /* ignore drhd */ |
47 | u8 include_all:1; | |
b1012ca8 | 48 | u8 gfx_dedicated:1; /* graphic dedicated */ |
2ae21010 SS |
49 | struct intel_iommu *iommu; |
50 | }; | |
51 | ||
57384592 JR |
52 | struct dmar_pci_path { |
53 | u8 bus; | |
54 | u8 device; | |
55 | u8 function; | |
56 | }; | |
57 | ||
59ce0515 JL |
58 | struct dmar_pci_notify_info { |
59 | struct pci_dev *dev; | |
60 | unsigned long event; | |
61 | int bus; | |
62 | u16 seg; | |
63 | u16 level; | |
57384592 | 64 | struct dmar_pci_path path[]; |
59ce0515 JL |
65 | } __attribute__((packed)); |
66 | ||
3a5670e8 | 67 | extern struct rw_semaphore dmar_global_lock; |
2ae21010 SS |
68 | extern struct list_head dmar_drhd_units; |
69 | ||
02d715b4 AG |
70 | #define for_each_drhd_unit(drhd) \ |
71 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ | |
72 | dmar_rcu_check()) | |
2ae21010 | 73 | |
7c919779 | 74 | #define for_each_active_drhd_unit(drhd) \ |
f5152416 QC |
75 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
76 | dmar_rcu_check()) \ | |
7c919779 JL |
77 | if (drhd->ignored) {} else |
78 | ||
8f912ba4 | 79 | #define for_each_active_iommu(i, drhd) \ |
f5152416 QC |
80 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
81 | dmar_rcu_check()) \ | |
8f912ba4 DW |
82 | if (i=drhd->iommu, drhd->ignored) {} else |
83 | ||
84 | #define for_each_iommu(i, drhd) \ | |
02d715b4 AG |
85 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
86 | dmar_rcu_check()) \ | |
8f912ba4 DW |
87 | if (i=drhd->iommu, 0) {} else |
88 | ||
0e242612 JL |
89 | static inline bool dmar_rcu_check(void) |
90 | { | |
91 | return rwsem_is_locked(&dmar_global_lock) || | |
7ebb5f8e | 92 | system_state == SYSTEM_BOOTING; |
0e242612 JL |
93 | } |
94 | ||
95 | #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) | |
96 | ||
a760f8a6 QC |
97 | #define for_each_dev_scope(devs, cnt, i, tmp) \ |
98 | for ((i) = 0; ((tmp) = (i) < (cnt) ? \ | |
99 | dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \ | |
100 | (i)++) | |
101 | ||
102 | #define for_each_active_dev_scope(devs, cnt, i, tmp) \ | |
103 | for_each_dev_scope((devs), (cnt), (i), (tmp)) \ | |
104 | if (!(tmp)) { continue; } else | |
b683b230 | 105 | |
2ae21010 | 106 | extern int dmar_table_init(void); |
2ae21010 | 107 | extern int dmar_dev_scope_init(void); |
ec154bf5 | 108 | extern void dmar_register_bus_notifier(void); |
bb3a6b78 | 109 | extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); |
832bd858 | 110 | extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt); |
59ce0515 JL |
111 | extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, |
112 | void *start, void*end, u16 segment, | |
832bd858 | 113 | struct dmar_dev_scope *devices, |
59ce0515 JL |
114 | int devices_cnt); |
115 | extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, | |
832bd858 | 116 | u16 segment, struct dmar_dev_scope *devices, |
59ce0515 | 117 | int count); |
2ae21010 | 118 | /* Intel IOMMU detection */ |
78013eaa | 119 | void detect_intel_iommu(void); |
9d783ba0 | 120 | extern int enable_drhd_fault_handling(void); |
6b197249 JL |
121 | extern int dmar_device_add(acpi_handle handle); |
122 | extern int dmar_device_remove(acpi_handle handle); | |
8594d832 | 123 | |
c2a0b538 JL |
124 | static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg) |
125 | { | |
126 | return 0; | |
127 | } | |
128 | ||
914ff771 KMP |
129 | #ifdef CONFIG_DMAR_DEBUG |
130 | void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, | |
131 | unsigned long long addr, u32 pasid); | |
132 | #else | |
133 | static inline void dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, | |
134 | unsigned long long addr, u32 pasid) {} | |
135 | #endif | |
136 | ||
8594d832 JL |
137 | #ifdef CONFIG_INTEL_IOMMU |
138 | extern int iommu_detected, no_iommu; | |
139 | extern int intel_iommu_init(void); | |
6c3a44ed | 140 | extern void intel_iommu_shutdown(void); |
c2a0b538 JL |
141 | extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg); |
142 | extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg); | |
6b197249 | 143 | extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg); |
31a75cbb | 144 | extern int dmar_parse_one_satc(struct acpi_dmar_header *hdr, void *arg); |
6b197249 JL |
145 | extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg); |
146 | extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
8594d832 JL |
147 | extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info); |
148 | #else /* !CONFIG_INTEL_IOMMU: */ | |
149 | static inline int intel_iommu_init(void) { return -ENODEV; } | |
6c3a44ed | 150 | static inline void intel_iommu_shutdown(void) { } |
6b197249 | 151 | |
c2a0b538 JL |
152 | #define dmar_parse_one_rmrr dmar_res_noop |
153 | #define dmar_parse_one_atsr dmar_res_noop | |
6b197249 JL |
154 | #define dmar_check_one_atsr dmar_res_noop |
155 | #define dmar_release_one_atsr dmar_res_noop | |
31a75cbb | 156 | #define dmar_parse_one_satc dmar_res_noop |
6b197249 | 157 | |
8594d832 | 158 | static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
29b61be6 | 159 | { |
8594d832 | 160 | return 0; |
29b61be6 | 161 | } |
6b197249 JL |
162 | |
163 | static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
164 | { | |
165 | return 0; | |
166 | } | |
8594d832 JL |
167 | #endif /* CONFIG_INTEL_IOMMU */ |
168 | ||
6b197249 JL |
169 | #ifdef CONFIG_IRQ_REMAP |
170 | extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
171 | #else /* CONFIG_IRQ_REMAP */ | |
172 | static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
173 | { return 0; } | |
174 | #endif /* CONFIG_IRQ_REMAP */ | |
175 | ||
89a6079d LB |
176 | extern bool dmar_platform_optin(void); |
177 | ||
6b197249 JL |
178 | #else /* CONFIG_DMAR_TABLE */ |
179 | ||
180 | static inline int dmar_device_add(void *handle) | |
181 | { | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static inline int dmar_device_remove(void *handle) | |
186 | { | |
187 | return 0; | |
188 | } | |
189 | ||
89a6079d LB |
190 | static inline bool dmar_platform_optin(void) |
191 | { | |
192 | return false; | |
193 | } | |
194 | ||
78013eaa CH |
195 | static inline void detect_intel_iommu(void) |
196 | { | |
197 | } | |
198 | ||
8594d832 | 199 | #endif /* CONFIG_DMAR_TABLE */ |
2ae21010 | 200 | |
2ae21010 SS |
201 | struct irte { |
202 | union { | |
203 | struct { | |
b1fe7f2c PZ |
204 | union { |
205 | /* Shared between remapped and posted mode*/ | |
206 | struct { | |
207 | __u64 present : 1, /* 0 */ | |
208 | fpd : 1, /* 1 */ | |
209 | __res0 : 6, /* 2 - 6 */ | |
210 | avail : 4, /* 8 - 11 */ | |
211 | __res1 : 3, /* 12 - 14 */ | |
212 | pst : 1, /* 15 */ | |
213 | vector : 8, /* 16 - 23 */ | |
214 | __res2 : 40; /* 24 - 63 */ | |
215 | }; | |
216 | ||
217 | /* Remapped mode */ | |
218 | struct { | |
219 | __u64 r_present : 1, /* 0 */ | |
220 | r_fpd : 1, /* 1 */ | |
221 | dst_mode : 1, /* 2 */ | |
222 | redir_hint : 1, /* 3 */ | |
223 | trigger_mode : 1, /* 4 */ | |
224 | dlvry_mode : 3, /* 5 - 7 */ | |
225 | r_avail : 4, /* 8 - 11 */ | |
226 | r_res0 : 4, /* 12 - 15 */ | |
227 | r_vector : 8, /* 16 - 23 */ | |
228 | r_res1 : 8, /* 24 - 31 */ | |
229 | dest_id : 32; /* 32 - 63 */ | |
230 | }; | |
231 | ||
232 | /* Posted mode */ | |
233 | struct { | |
234 | __u64 p_present : 1, /* 0 */ | |
235 | p_fpd : 1, /* 1 */ | |
236 | p_res0 : 6, /* 2 - 7 */ | |
237 | p_avail : 4, /* 8 - 11 */ | |
238 | p_res1 : 2, /* 12 - 13 */ | |
239 | p_urgent : 1, /* 14 */ | |
240 | p_pst : 1, /* 15 */ | |
241 | p_vector : 8, /* 16 - 23 */ | |
242 | p_res2 : 14, /* 24 - 37 */ | |
243 | pda_l : 26; /* 38 - 63 */ | |
244 | }; | |
245 | __u64 low; | |
246 | }; | |
247 | ||
248 | union { | |
249 | /* Shared between remapped and posted mode*/ | |
250 | struct { | |
251 | __u64 sid : 16, /* 64 - 79 */ | |
252 | sq : 2, /* 80 - 81 */ | |
253 | svt : 2, /* 82 - 83 */ | |
254 | __res3 : 44; /* 84 - 127 */ | |
255 | }; | |
256 | ||
257 | /* Posted mode*/ | |
258 | struct { | |
259 | __u64 p_sid : 16, /* 64 - 79 */ | |
260 | p_sq : 2, /* 80 - 81 */ | |
261 | p_svt : 2, /* 82 - 83 */ | |
262 | p_res3 : 12, /* 84 - 95 */ | |
263 | pda_h : 32; /* 96 - 127 */ | |
264 | }; | |
265 | __u64 high; | |
266 | }; | |
3bf17472 | 267 | }; |
b1fe7f2c PZ |
268 | #ifdef CONFIG_IRQ_REMAP |
269 | __u128 irte; | |
270 | #endif | |
2ae21010 SS |
271 | }; |
272 | }; | |
423f0859 | 273 | |
bf56027f TG |
274 | static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src) |
275 | { | |
276 | dst->present = src->present; | |
277 | dst->fpd = src->fpd; | |
278 | dst->avail = src->avail; | |
279 | dst->pst = src->pst; | |
280 | dst->vector = src->vector; | |
281 | dst->sid = src->sid; | |
282 | dst->sq = src->sq; | |
283 | dst->svt = src->svt; | |
284 | } | |
285 | ||
3bf17472 TG |
286 | #define PDA_LOW_BIT 26 |
287 | #define PDA_HIGH_BIT 32 | |
288 | ||
3460a6d9 KA |
289 | /* Can't use the common MSI interrupt functions |
290 | * since DMAR is not a pci device | |
291 | */ | |
5c2837fb TG |
292 | struct irq_data; |
293 | extern void dmar_msi_unmask(struct irq_data *data); | |
294 | extern void dmar_msi_mask(struct irq_data *data); | |
3460a6d9 KA |
295 | extern void dmar_msi_read(int irq, struct msi_msg *msg); |
296 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
297 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 298 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
34742db8 JL |
299 | extern int dmar_alloc_hwirq(int id, int node, void *arg); |
300 | extern void dmar_free_hwirq(int irq); | |
3460a6d9 | 301 | |
10e5247f | 302 | #endif /* __DMAR_H__ */ |