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3b20eb23 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
10e5247f KA |
2 | /* |
3 | * Copyright (c) 2006, Intel Corporation. | |
4 | * | |
10e5247f KA |
5 | * Copyright (C) Ashok Raj <ashok.raj@intel.com> |
6 | * Copyright (C) Shaohua Li <shaohua.li@intel.com> | |
7 | */ | |
8 | ||
9 | #ifndef __DMAR_H__ | |
10 | #define __DMAR_H__ | |
11 | ||
12 | #include <linux/acpi.h> | |
13 | #include <linux/types.h> | |
ba395927 | 14 | #include <linux/msi.h> |
1531a6a6 | 15 | #include <linux/irqreturn.h> |
3a5670e8 | 16 | #include <linux/rwsem.h> |
b2d09103 | 17 | #include <linux/rculist.h> |
10e5247f | 18 | |
6eea69dd AM |
19 | struct acpi_dmar_header; |
20 | ||
78d8e704 JL |
21 | #ifdef CONFIG_X86 |
22 | # define DMAR_UNITS_SUPPORTED MAX_IO_APICS | |
23 | #else | |
24 | # define DMAR_UNITS_SUPPORTED 64 | |
25 | #endif | |
26 | ||
41750d31 SS |
27 | /* DMAR Flags */ |
28 | #define DMAR_INTR_REMAP 0x1 | |
29 | #define DMAR_X2APIC_OPT_OUT 0x2 | |
89a6079d | 30 | #define DMAR_PLATFORM_OPT_IN 0x4 |
41750d31 | 31 | |
ba395927 | 32 | struct intel_iommu; |
694835dc | 33 | |
832bd858 DW |
34 | struct dmar_dev_scope { |
35 | struct device __rcu *dev; | |
36 | u8 bus; | |
37 | u8 devfn; | |
38 | }; | |
39 | ||
d3f13810 | 40 | #ifdef CONFIG_DMAR_TABLE |
41750d31 | 41 | extern struct acpi_table_header *dmar_tbl; |
2ae21010 SS |
42 | struct dmar_drhd_unit { |
43 | struct list_head list; /* list of drhd units */ | |
44 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
45 | u64 reg_base_addr; /* register base address*/ | |
832bd858 | 46 | struct dmar_dev_scope *devices;/* target device array */ |
2ae21010 | 47 | int devices_cnt; /* target device count */ |
276dbf99 | 48 | u16 segment; /* PCI domain */ |
2ae21010 SS |
49 | u8 ignored:1; /* ignore drhd */ |
50 | u8 include_all:1; | |
b1012ca8 | 51 | u8 gfx_dedicated:1; /* graphic dedicated */ |
2ae21010 SS |
52 | struct intel_iommu *iommu; |
53 | }; | |
54 | ||
57384592 JR |
55 | struct dmar_pci_path { |
56 | u8 bus; | |
57 | u8 device; | |
58 | u8 function; | |
59 | }; | |
60 | ||
59ce0515 JL |
61 | struct dmar_pci_notify_info { |
62 | struct pci_dev *dev; | |
63 | unsigned long event; | |
64 | int bus; | |
65 | u16 seg; | |
66 | u16 level; | |
57384592 | 67 | struct dmar_pci_path path[]; |
59ce0515 JL |
68 | } __attribute__((packed)); |
69 | ||
3a5670e8 | 70 | extern struct rw_semaphore dmar_global_lock; |
2ae21010 SS |
71 | extern struct list_head dmar_drhd_units; |
72 | ||
02d715b4 AG |
73 | #define for_each_drhd_unit(drhd) \ |
74 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ | |
75 | dmar_rcu_check()) | |
2ae21010 | 76 | |
7c919779 | 77 | #define for_each_active_drhd_unit(drhd) \ |
f5152416 QC |
78 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
79 | dmar_rcu_check()) \ | |
7c919779 JL |
80 | if (drhd->ignored) {} else |
81 | ||
8f912ba4 | 82 | #define for_each_active_iommu(i, drhd) \ |
f5152416 QC |
83 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
84 | dmar_rcu_check()) \ | |
8f912ba4 DW |
85 | if (i=drhd->iommu, drhd->ignored) {} else |
86 | ||
87 | #define for_each_iommu(i, drhd) \ | |
02d715b4 AG |
88 | list_for_each_entry_rcu(drhd, &dmar_drhd_units, list, \ |
89 | dmar_rcu_check()) \ | |
8f912ba4 DW |
90 | if (i=drhd->iommu, 0) {} else |
91 | ||
0e242612 JL |
92 | static inline bool dmar_rcu_check(void) |
93 | { | |
94 | return rwsem_is_locked(&dmar_global_lock) || | |
95 | system_state == SYSTEM_BOOTING; | |
96 | } | |
97 | ||
98 | #define dmar_rcu_dereference(p) rcu_dereference_check((p), dmar_rcu_check()) | |
99 | ||
a760f8a6 QC |
100 | #define for_each_dev_scope(devs, cnt, i, tmp) \ |
101 | for ((i) = 0; ((tmp) = (i) < (cnt) ? \ | |
102 | dmar_rcu_dereference((devs)[(i)].dev) : NULL, (i) < (cnt)); \ | |
103 | (i)++) | |
104 | ||
105 | #define for_each_active_dev_scope(devs, cnt, i, tmp) \ | |
106 | for_each_dev_scope((devs), (cnt), (i), (tmp)) \ | |
107 | if (!(tmp)) { continue; } else | |
b683b230 | 108 | |
2ae21010 | 109 | extern int dmar_table_init(void); |
2ae21010 | 110 | extern int dmar_dev_scope_init(void); |
ec154bf5 | 111 | extern void dmar_register_bus_notifier(void); |
ada4d4b2 | 112 | extern int dmar_parse_dev_scope(void *start, void *end, int *cnt, |
832bd858 | 113 | struct dmar_dev_scope **devices, u16 segment); |
bb3a6b78 | 114 | extern void *dmar_alloc_dev_scope(void *start, void *end, int *cnt); |
832bd858 | 115 | extern void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt); |
59ce0515 JL |
116 | extern int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, |
117 | void *start, void*end, u16 segment, | |
832bd858 | 118 | struct dmar_dev_scope *devices, |
59ce0515 JL |
119 | int devices_cnt); |
120 | extern int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, | |
832bd858 | 121 | u16 segment, struct dmar_dev_scope *devices, |
59ce0515 | 122 | int count); |
2ae21010 | 123 | /* Intel IOMMU detection */ |
480125ba | 124 | extern int detect_intel_iommu(void); |
9d783ba0 | 125 | extern int enable_drhd_fault_handling(void); |
6b197249 JL |
126 | extern int dmar_device_add(acpi_handle handle); |
127 | extern int dmar_device_remove(acpi_handle handle); | |
8594d832 | 128 | |
c2a0b538 JL |
129 | static inline int dmar_res_noop(struct acpi_dmar_header *hdr, void *arg) |
130 | { | |
131 | return 0; | |
132 | } | |
133 | ||
8594d832 JL |
134 | #ifdef CONFIG_INTEL_IOMMU |
135 | extern int iommu_detected, no_iommu; | |
136 | extern int intel_iommu_init(void); | |
6c3a44ed | 137 | extern void intel_iommu_shutdown(void); |
c2a0b538 JL |
138 | extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg); |
139 | extern int dmar_parse_one_atsr(struct acpi_dmar_header *header, void *arg); | |
6b197249 | 140 | extern int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg); |
31a75cbb | 141 | extern int dmar_parse_one_satc(struct acpi_dmar_header *hdr, void *arg); |
6b197249 JL |
142 | extern int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg); |
143 | extern int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
8594d832 JL |
144 | extern int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info); |
145 | #else /* !CONFIG_INTEL_IOMMU: */ | |
146 | static inline int intel_iommu_init(void) { return -ENODEV; } | |
6c3a44ed | 147 | static inline void intel_iommu_shutdown(void) { } |
6b197249 | 148 | |
c2a0b538 JL |
149 | #define dmar_parse_one_rmrr dmar_res_noop |
150 | #define dmar_parse_one_atsr dmar_res_noop | |
6b197249 JL |
151 | #define dmar_check_one_atsr dmar_res_noop |
152 | #define dmar_release_one_atsr dmar_res_noop | |
31a75cbb | 153 | #define dmar_parse_one_satc dmar_res_noop |
6b197249 | 154 | |
8594d832 | 155 | static inline int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
29b61be6 | 156 | { |
8594d832 | 157 | return 0; |
29b61be6 | 158 | } |
6b197249 JL |
159 | |
160 | static inline int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
161 | { | |
162 | return 0; | |
163 | } | |
8594d832 JL |
164 | #endif /* CONFIG_INTEL_IOMMU */ |
165 | ||
6b197249 JL |
166 | #ifdef CONFIG_IRQ_REMAP |
167 | extern int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert); | |
168 | #else /* CONFIG_IRQ_REMAP */ | |
169 | static inline int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) | |
170 | { return 0; } | |
171 | #endif /* CONFIG_IRQ_REMAP */ | |
172 | ||
89a6079d LB |
173 | extern bool dmar_platform_optin(void); |
174 | ||
6b197249 JL |
175 | #else /* CONFIG_DMAR_TABLE */ |
176 | ||
177 | static inline int dmar_device_add(void *handle) | |
178 | { | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static inline int dmar_device_remove(void *handle) | |
183 | { | |
184 | return 0; | |
185 | } | |
186 | ||
89a6079d LB |
187 | static inline bool dmar_platform_optin(void) |
188 | { | |
189 | return false; | |
190 | } | |
191 | ||
8594d832 | 192 | #endif /* CONFIG_DMAR_TABLE */ |
2ae21010 | 193 | |
2ae21010 SS |
194 | struct irte { |
195 | union { | |
3bf17472 | 196 | /* Shared between remapped and posted mode*/ |
2ae21010 | 197 | struct { |
3bf17472 TG |
198 | __u64 present : 1, /* 0 */ |
199 | fpd : 1, /* 1 */ | |
200 | __res0 : 6, /* 2 - 6 */ | |
201 | avail : 4, /* 8 - 11 */ | |
202 | __res1 : 3, /* 12 - 14 */ | |
203 | pst : 1, /* 15 */ | |
204 | vector : 8, /* 16 - 23 */ | |
205 | __res2 : 40; /* 24 - 63 */ | |
206 | }; | |
207 | ||
208 | /* Remapped mode */ | |
209 | struct { | |
210 | __u64 r_present : 1, /* 0 */ | |
211 | r_fpd : 1, /* 1 */ | |
212 | dst_mode : 1, /* 2 */ | |
213 | redir_hint : 1, /* 3 */ | |
214 | trigger_mode : 1, /* 4 */ | |
215 | dlvry_mode : 3, /* 5 - 7 */ | |
216 | r_avail : 4, /* 8 - 11 */ | |
217 | r_res0 : 4, /* 12 - 15 */ | |
218 | r_vector : 8, /* 16 - 23 */ | |
219 | r_res1 : 8, /* 24 - 31 */ | |
220 | dest_id : 32; /* 32 - 63 */ | |
221 | }; | |
222 | ||
223 | /* Posted mode */ | |
224 | struct { | |
225 | __u64 p_present : 1, /* 0 */ | |
226 | p_fpd : 1, /* 1 */ | |
227 | p_res0 : 6, /* 2 - 7 */ | |
228 | p_avail : 4, /* 8 - 11 */ | |
229 | p_res1 : 2, /* 12 - 13 */ | |
230 | p_urgent : 1, /* 14 */ | |
231 | p_pst : 1, /* 15 */ | |
232 | p_vector : 8, /* 16 - 23 */ | |
233 | p_res2 : 14, /* 24 - 37 */ | |
234 | pda_l : 26; /* 38 - 63 */ | |
2ae21010 SS |
235 | }; |
236 | __u64 low; | |
237 | }; | |
238 | ||
239 | union { | |
3bf17472 | 240 | /* Shared between remapped and posted mode*/ |
2ae21010 | 241 | struct { |
3bf17472 TG |
242 | __u64 sid : 16, /* 64 - 79 */ |
243 | sq : 2, /* 80 - 81 */ | |
244 | svt : 2, /* 82 - 83 */ | |
245 | __res3 : 44; /* 84 - 127 */ | |
246 | }; | |
247 | ||
248 | /* Posted mode*/ | |
249 | struct { | |
250 | __u64 p_sid : 16, /* 64 - 79 */ | |
251 | p_sq : 2, /* 80 - 81 */ | |
252 | p_svt : 2, /* 82 - 83 */ | |
253 | p_res3 : 12, /* 84 - 95 */ | |
254 | pda_h : 32; /* 96 - 127 */ | |
2ae21010 SS |
255 | }; |
256 | __u64 high; | |
257 | }; | |
258 | }; | |
423f0859 | 259 | |
bf56027f TG |
260 | static inline void dmar_copy_shared_irte(struct irte *dst, struct irte *src) |
261 | { | |
262 | dst->present = src->present; | |
263 | dst->fpd = src->fpd; | |
264 | dst->avail = src->avail; | |
265 | dst->pst = src->pst; | |
266 | dst->vector = src->vector; | |
267 | dst->sid = src->sid; | |
268 | dst->sq = src->sq; | |
269 | dst->svt = src->svt; | |
270 | } | |
271 | ||
3bf17472 TG |
272 | #define PDA_LOW_BIT 26 |
273 | #define PDA_HIGH_BIT 32 | |
274 | ||
3460a6d9 KA |
275 | /* Can't use the common MSI interrupt functions |
276 | * since DMAR is not a pci device | |
277 | */ | |
5c2837fb TG |
278 | struct irq_data; |
279 | extern void dmar_msi_unmask(struct irq_data *data); | |
280 | extern void dmar_msi_mask(struct irq_data *data); | |
3460a6d9 KA |
281 | extern void dmar_msi_read(int irq, struct msi_msg *msg); |
282 | extern void dmar_msi_write(int irq, struct msi_msg *msg); | |
283 | extern int dmar_set_interrupt(struct intel_iommu *iommu); | |
1531a6a6 | 284 | extern irqreturn_t dmar_fault(int irq, void *dev_id); |
34742db8 JL |
285 | extern int dmar_alloc_hwirq(int id, int node, void *arg); |
286 | extern void dmar_free_hwirq(int irq); | |
3460a6d9 | 287 | |
10e5247f | 288 | #endif /* __DMAR_H__ */ |